MCF51QE128 MCF51QE64 MCF51QE32 Reference Manual ColdFire Microcontrollers MCF51QE128RM Rev. 3 09/2007 freescale.com Get the latest version from freescale.
MCF51QE128 Series Features • 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V, and 20-MHz CPU at 2.1V to 1.8V across temperature range of -40°C to 85°C – Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.
MCF51QE128 Reference Manual Covers MCF51QE128 MCF51QE64 MCF51QE32 Related Documentation: • MCF51QE128 (Data Sheet) Contains pin assignments and diagrams, all electrical specififications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. Get the latest version from freescale.com MCF51QE128RM Rev.
MCF51QE128 MCU Series Reference Manual, Rev. 3 6 Freescale Semiconductor Get the latest version from freescale.
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 1.4 Devices in the MCF51QE128/64/32 Series ....................................................................................23 MCU Block Diagram ......................................................................................................................24 V1 ColdFire Core ............................................................................................................................26 System Clocks ........
Section Number 3.7 3.8 3.9 Title Page Wait Modes ......................................................................................................................................50 3.7.1 Wait Mode .........................................................................................................................50 3.7.2 Low-Power Wait Mode (LPwait) ......................................................................................50 3.7.2.1 BDM in Low-Power Wait Mode ......................
Section Number 4.6 Title Page 4.5.4.1 Wait Mode .......................................................................................................88 4.5.4.2 Stop Modes .....................................................................................................88 4.5.4.3 Background Debug Mode ...............................................................................88 4.5.5 Security ........................................................................................................
Section Number Title Page Chapter 6 Parallel Input/Output Control 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Port Data and Data Direction ........................................................................................................113 Pull-up, Slew Rate, and Drive Strength ........................................................................................114 6.2.1 Port Internal Pull-up Enable ...........................................................................................114 6.2.
Section Number 6.7.5 6.7.6 6.7.7 6.7.8 6.7.9 6.7.10 6.7.11 Title Page 6.7.4.2 Port D Data Direction Register (PTDDD) ....................................................127 6.7.4.3 Port D Pull Enable Register (PTDPE) ..........................................................127 6.7.4.4 Port D Slew Rate Enable Register (PTDSE) ................................................128 6.7.4.5 Port D Drive Strength Selection Register (PTDDS) .....................................128 Port E Registers .......
Section Number Title Page 6.7.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) ................................142 6.7.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) ..............................................142 6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) ...........................................143 Chapter 7 ColdFire Core 7.1 7.2 7.3 Introduction ..................................................................................................................................
Section Number 7.3.4.5 7.3.4.6 Title Page Miscellaneous Instruction Execution Times .................................................171 Branch Instruction Execution Times .............................................................172 Chapter 8 Interrupt Controller (CF1_INTC) 8.1 8.2 8.3 8.4 8.5 8.6 Introduction ...................................................................................................................................173 8.1.1 Overview .......................................
Section Number 9.4 9.5 9.6 Title Page 9.3.2.2 RGPIO Data (RGPIO_DATA) ......................................................................200 9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) ..............................................................201 9.3.2.4 RGPIO Clear Data (RGPIO_CLR) ...............................................................201 9.3.2.5 RGPIO Set Data (RGPIO_SET) ...................................................................202 9.3.2.6 RGPIO Toggle Data (RGPIO_TOG) .............
Section Number Title Page 11.1.5 Block Diagram ................................................................................................................219 11.2 External Signal Description ..........................................................................................................220 11.2.1 Analog Power (VDDAD) ..................................................................................................221 11.2.2 Analog Ground (VSSAD) ............................................
Section Number Title Page 11.6.1.3 Analog Input Pins .........................................................................................237 11.6.2 Sources of Error ..............................................................................................................238 11.6.2.1 Sampling Error ..............................................................................................238 11.6.2.2 Pin Leakage Error ............................................................................
Section Number Title Page 12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................257 12.4.6 Internal Reference Clock ................................................................................................257 12.4.7 External Reference Clock ...............................................................................................257 12.4.8 Fixed Frequency Clock ...................................................................................
Section Number Title Page 13.6 Interrupts .......................................................................................................................................275 13.6.1 Byte Transfer Interrupt ....................................................................................................275 13.6.2 Address Detect Interrupt .................................................................................................275 13.6.3 Arbitration Lost Interrupt ..........................
Section Number Title Page 15.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................300 15.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................301 15.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................303 15.2.6 SCI Control Register 3 (SCIxC3) ..............................................................
Section Number Title Page 16.4.4 SPI Status Register (SPIxS) ............................................................................................324 16.4.5 SPI Data Register (SPIxD) .............................................................................................325 16.5 Functional Description ..................................................................................................................325 16.5.1 SPI Clock Formats ...................................................
Section Number Title Page 17.6.2 Description of Interrupt Operation .................................................................................353 17.6.2.1 Timer Overflow Interrupt (TOF) Description ...............................................353 17.6.2.1.1Normal Case .............................................................................353 17.6.2.1.2Center-Aligned PWM Case ......................................................354 17.6.2.2 Channel Event Interrupt Description .............
Section Number Title Page 18.4.1.5.8NOP ..........................................................................................397 18.4.1.5.9READ_CREG ..........................................................................397 18.4.1.5.10READ_DREG ........................................................................398 18.4.1.5.11READ_MEM.sz, READ_MEM.sz_WS ................................398 18.4.1.5.12READ_PSTB .........................................................................399 18.4.1.
Chapter 1 Device Overview The MCF51QE128, MCF51QE64, and MCF51QE32 are members of the low-cost, low-power, high-performance Version 1 (V1) ColdFire family of 32-bit microcontroller units (MCUs). All MCUs in the family use the enhanced V1 ColdFire core and are available with a variety of modules, memory sizes, and package types. CPU clock rates on these devices can reach 50.33 MHz. Peripherals operate up to 25.165 MHz. 1.
Chapter 1 Device Overview Table 1-1. MCF51QE128 Series Features by MCU and Package (continued) Feature MCF51QE128 MCF51QE64 External IRQ yes Low-Voltage Detect (LVD) yes TPM1 channels 3 TPM2 channels 3 TPM3 channels 6 XOSC MCF51QE32 yes 1 Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only PTA4/ACMP1O/BKGD/MS. 2 16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module. 1.
Chapter 1 Device Overview PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge PORT B PTE7/RGPIO7/TPM3CLK PTE6/RGPIO6 PTE5/RGPIO5 PTE4/RGPIO4 PTE3/RGPIO3/SS1 PTE2/RGPIO2/MISO1 PTE1/RGPIO1/MOSI1 PTE0/RGPIO0/TPM2CLK/SPSCK1 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP1
Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules Table 1-2. Module Versions Module 1.
Chapter 1 Device Overview Optional External Reference Clock Source Block RANGE HGO EREFS EREFSTEN RTC ICSERCLK ERCLKEN IRCLKEN IREFSTEN ICSIRCLK CLKS BDIV / 2n Internal Reference Clock 9 IREFS ICSOUT n=0-3 LP DCO DCOOUT /2 ICSLCLK TRIM ICSFFCLK 9 / 2n RDIV_CLK Filter n=0-7 FLL RDIV Internal Clock Source Block Figure 1-2. Simplified ICS Block Diagram 1.4.2 System Clock Distribution Figure 1-3 shows a simplified clock connection diagram.
Chapter 1 Device Overview TPM1CLK EXTAL XTAL XOSC RTC OSCOUT COP TPM1 TPM2CLK TPM3CLK TPM2 TPM3 SCI1 & SCI2 SPI1 & SPI2 ACMP1 & ACMP2 FLASH GPIO ICSIRCLK ICSERCLK 1KHz LPO ICSFFCLK LPOCLK FFCLK* ÷2 SYNC* ICS ICSOUT BUSCLK ÷2 ICSLCLK CPU & RGPIO Debug RAM BDC IIC1 & IIC2 * The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. PMC ADC ADC has min and max frequency requirements.
Chapter 1 Device Overview The ADC module also has an internally generated asynchronous clock that allows it to run in stop mode (ADACK). This signal is not available externally and is not shown in this figure. 1.4.3 ICS Modes of Operation There are seven modes of operation for the internal clock source (ICS) module: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. These are shown in Figure 1-4. The IREFS and CLKS fields are contained within the ICS module definition.
Chapter 1 Device Overview IREFS=1 CLKS=00 LP=0 FLL Engaged Internal (FEI) IREFS=0 CLKS=10 LP=0 FLL Bypassed External LowPower(FBELP) FLL Bypassed External (FBE) IREFS=1 CLKS=01 LP=0 FLL Bypassed Internal (FBI) FLL Bypassed Internal LowPower(FBILP) IREFS=1 CLKS=01 LP=1 IREFS=0 CLKS=10 LP=1 FLL Engaged External (FEE) IREFS=0 CLKS=00 LP=0 Entered from any state when MCU enters stop with ENBDM=0. Stop Returns to state that was active before MCU entered stop, unless reset occurs while in stop.
MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 31 Get the latest version from freescale.
Chapter 1 Device Overview MCF51QE128 MCU Series Reference Manual, Rev. 3 32 Freescale Semiconductor Get the latest version from freescale.
Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 shows the 80-pin assignments for the MCF51QE128 devices. Figure 2-2 shows the 64-pin assignments for the MCF51QE128/64/32 devices. MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 33 Get the latest version from freescale.
PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH3 PTH2 PTH1 PTH0 PTC7/RGPIO15 /TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTG4/ADP20 PTG5/ADP21 PTG6/ADP22 PTG7/ADP23 PTC6/RGPIO14/RxD2/ACMP2+ PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/A
PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH1 PTH0 PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTC6/RGPIO14/RxD2/ACMP2+ PTC7/RGPIO15/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 4
Chapter 2 Pins and Connections CBYAD 0.1 μF VDDAD MCF51QE128 VREFH PORT A VREFL VSSAD CBY 0.1 μF VDD VSS SYSTEM POWER + 3V VDD CBLK + 10 μF PORT B CBY 0.
Chapter 2 Pins and Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections NOTE The RESET pin does not contain a clamp diode to VDD and should not be driven above VDD. NOTE In EMC-sensitive applications, an external RC filter is recommended on the RESET pin, if enabled. See Figure 2-3 for an example. After a power-on reset (POR), the PTC4/RGPIO12/TPM3CH4/RSTO pin defaults to a general-purpose port pin, PTC4. Setting RSTOPE in SOPT1 configures the pin as an open drain with internal pullup acting as reset out (RSTO).
Chapter 2 Pins and Connections Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD/MS pin. 2.2.
Chapter 2 Pins and Connections Table 2-1.
Table 2-1.
Chapter 2 Pins and Connections 2 IIC1 pins (SCL1 and SDA1) can be repositioned using SOPT2[IIC1PS]. Default locations are PTA3 and PTA2, respectively. 3 PTA4/ACMP1O/BKGD/MS is limited to output-only for the port I/O function. MCF51QE128 MCU Series Reference Manual, Rev. 3 42 Freescale Semiconductor Get the latest version from freescale.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MCF51QE128/64/32 are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. The overall system mode is generally a function of a number of separate, but inter-related variables: debug mode, security mode, power mode, and clock mode. Clock modes were discussed in Section 1.4.3, “ICS Modes of Operation”.
Chapter 3 Modes of Operation 3.3 Overview The ColdFire CPU has two primary user modes of operation, run and stop. (The CPU also supports a halt mode that is used strictly for debug operations.) The STOP instruction is used to invoke stop and wait modes for this family of devices. If the WAITE control bit is set when STOP is executed, the wait mode is entered. Otherwise, if the STOPE bit is set, the CPU enters one of the stop modes.
Chapter 3 Modes of Operation Table 3-1. CPU / Power Mode Selections x LPrun mode with low voltage detect disabled processor and peripherals clocked at low frequency2. Low voltage detects are not active. x x LPwait mode - processor clock is inactive, peripherals are clocked at low frequency and the PMC is loosely regulating. Low voltage detects are not active.
Chapter 3 Modes of Operation Stop3 Stop4 Run Wait Stop2 LPrun Mode Regulator State Run Full On Wait Full On Stop4 Full On LPrun Standby LPwait Standby Stop3 Standby Stop2 Partial Power Off LPwait Figure 3-2. Allowable Power Mode Transitions for Mission Mode MCF51QE128/64/32 Figure 3-2 illustrates mission mode state transitions allowed between the legal states shown in Table 3-1. PTA5/IRQ/TPM1CLK/RESET must be asserted low to exit stop2.
Chapter 3 Modes of Operation Stop4 Stop3 8 4 9 7 1 10 Halt Run Stop2 LPrun 2 6 11 Wait 5 LPwait 3 Figure 3-3. All Allowable Power Mode Transitions for MCF51QE128/64/32 Table 3-2 defines triggers for the various state transitions shown in Figure 3-2. Table 3-2.
Chapter 3 Modes of Operation Table 3-2. Triggers for Transitions Shown in Figure 3-2 (continued) Transition # From To Stop3 Run Run Stop3 Stop4 Halt Halt Stop4 Halt Run GO instruction issued via BDM Run Halt When a BACKGROUND command is received through the BKGD/MS pin OR When a HALT instruction is executed OR When encountering a BDM breakpoint Wait Halt When a BACKGROUND command is received through the BKGD/MS pin (ENBDM must equal one). Halt Wait Not supported.
Chapter 3 Modes of Operation 3.6 3.6.1 Run Modes Run Mode Run mode is the normal operating mode for the MCF51QE128/64/32. This mode is selected when the BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches the supervisor SR and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 in the memory map and executes code starting at the newly set value of the PC. 3.6.
Chapter 3 Modes of Operation 3.7 3.7.1 Wait Modes Wait Mode Wait mode is entered by executing a STOP instruction after configuring the device as per Table 3-1. Upon execution of the STOP instruction, the CPU enters a low-power state in which it is not clocked. The V1 ColdFire core does not differentiate between stop and wait modes. Both are stop from the core’s perspective. The difference between the two is at the device level. In stop mode, most peripheral clocks are shut down.
NOTE If neither the WAITE nor STOPE bit is set when the CPU executes a STOP instruction, the MCU does not enter either of the stop modes. Instead, the MCU initiates an illegal opcode reset if CPUCR[IRD] is cleared or an illegal instruction exception if CPUCR[IRD] is set. The stop modes are selected by setting the appropriate bits in the system power management status and control 2 (SPMSC2) register. Table 3-1 shows all of the control bits that affect mode selection under various conditions.
Chapter 3 Modes of Operation In addition to the above, upon waking up from stop2, SPMSC2[PPDF] is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to SPMSC2[PPDACK]. Wakeup from stop2 can be initiated with an RTC interrupt. Unlike most other modules on the chip, the RTC is not reset as a result of exiting stop2. This implies that the RTC interrupt is asserted (although masked) upon exit from stop2.
Chapter 3 Modes of Operation Stop4 is also entered if SPMSC1[LVDE, LVDSE] are set, enabling low voltage detect when the STOP instruction is executed. The LVD may only be used when the on-chip regulator is in full regulation mode. Thus, stop3 and stop2 modes are not compatible with use of the LVD. The LVD system is capable of generating an interrupt or a reset when the supply voltage drops below the LVD voltage.
Chapter 3 Modes of Operation Table 3-4.
Chapter 3 Modes of Operation 3 FBELP refers to the ICS FLL bypassed external low-power state. See Chapter 12, “Internal Clock Source (S08ICSV3),” for more details. 4 The PTA5/IRQ/TPM1CLK/RESET pin also has a direct connection to the on-chip regulator wakeup input. Asserting this pin low while in stop2 triggers the PMC to wakeup. As a result, the device undergoes a power-on-reset sequence. MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 55 Get the latest version from freescale.
Chapter 3 Modes of Operation MCF51QE128 MCU Series Reference Manual, Rev. 3 56 Freescale Semiconductor Get the latest version from freescale.
Chapter 4 Memory 4.1 MCF51QE128/64/32 Memory Map As shown in Figure 4-1, on-chip memory in the MCF51QE128/64/32 series of MCUs consists of RAM and flash program memory for nonvolatile code and data storage, plus I/O and control/status registers. NOTE Version 1 ColdFire devices contain 24-bit internal address buses, while previous ColdFire cores have 32-bit internal address buses.
Chapter 4 Memory Regions within the memory map are subject to restrictions with regard to the types of allowable accesses. These are outlined in Table 4-1. Non-supported access types terminate the bus cycle with an error and would typically generate a system reset in response to the error termination. Table 4-1.
Chapter 4 Memory NOTE Peripheral register locations for MCF51QE128/64/32 are shifted 0x(FF)FF_8000 compared with the MC9S08QE128/64/32 devices. • • The ColdFire interrupt controller module is mapped in the peripheral space and occupies a 64-byte space at the upper end of memory. Accordingly, its address decode is defined as 0x(FF)FF_FFC0–0x(FF)FF_FFFF. This 64-byte space includes the program-visible registers as well as the space used for interrupt acknowledge (IACK) cycles.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-3.
Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-4. Reserved Flash Memory Addresses MSB1 (0x0) Address NVOPT Reserved 0x(00)00_040C 2 Reserved (0x1) 0x(00)00_0408 1 (0x2) LSB2 (0x3) Reserved NVPROT MSB = most significant byte LSB = least significant byte Table 4-5.
Chapter 4 Memory to disengage security is by mass-erasing the flash (normally through the background debug interface) and verifying the flash is blank. 4.2.2 ColdFire Rapid GPIO Memory Map The rapid GPIO module is mapped into a 16-byte area starting at location 0x(00)C0_0000. Its memory map is shown below in Table 4-6. Table 4-6.
Chapter 4 Memory Table 4-7. V1 ColdFire Interrupt Controller Memory Map (continued) 4.
Chapter 4 Memory Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The flash module includes a memory controller that executes commands to modify flash memory contents. Array read access time is one bus cycle for bytes, aligned words, and aligned longwords. Multiple accesses are needed for misaligned words and longword operands.
Chapter 4 Memory • • • • • Command interface for fast program and erase operation Up to 100,000 program/erase cycles at typical voltage and temperature Flexible block protection (on any 2-Kbyte memory boundary) Security feature to prevent unauthorized access to on-chip memory and resources Auto power-down for low-frequency read accesses 4.4.2 Register Descriptions The flash module contains a set of 16 control and status registers located between 0x(00)00_0000 and 0x(00)00_000F.
Chapter 4 Memory The FOPT register is loaded from the flash configuration field (see Section 4.2.1) during the reset sequence, indicated by F in Figure 4-4. The security feature in the flash module is described in Section 4.5.5, “Security”. 7 6 R KEYEN 5 4 3 2 0 0 0 0 0 0 0 0 1 0 SEC W Reset F F F F Figure 4-4. Flash Options Register (FOPT) Table 4-10. FOPT Field Descriptions Field Description 7–6 KEYEN Backdoor Key Security Enable Bits.
Chapter 4 Memory Table 4-11. FCNFG Field Descriptions Field 7–6 5 KEYACC 4–0 4.4.2.4 Description Reserved, should be cleared. Enable Security Key Writing 0 Writes to the flash block are interpreted as the start of a command write sequence. 1 Writes to the flash block are interpreted as keys to open the backdoor. Reserved, should be cleared. Flash Protection Register (FPROT and NVPROT) The FPROT register defines which flash sectors are protected against program or erase operations.
Table 4-13. Flash Protection Address Range (continued) Protected Address Range Relative to Flash Array Base Protected Size 0x00–0x3F 0x0_0000–0x1_FFFF 128 Kbytes 0x40 0x0_0000–0x1_F7FF 126 Kbytes 0x41 0x0_0000–0x1_EFFF 124 Kbytes 0x0_0000–0x1_E7FF 122 Kbytes 0x43 0x0_0000–0x1_DFFF 120 Kbytes 0x44 0x0_0000–0x1_D7FF 118 Kbytes 0x45 0x0_0000–0x1_CFFF 116 Kbytes 0x46 0x0_0000-0x1_C7FF 114 Kbytes 0x47 0x0_0000–0x1_BFFF 112 Kbytes ... ... ...
Chapter 4 Memory 4.4.2.5 Flash Status Register (FSTAT) The FSTAT register defines the operational status of the flash module. FCBEF, FPVIOL and FACCERR are readable and writable. FBLANK is readable and not writable. The remaining bits read 0 and are not writable. 7 6 5 4 3 2 1 0 R FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 W w1c w1c w1c 0 0 0 0 0 0 Reset 1 1 Figure 4-7. Flash Status Register (FSTAT) Table 4-14.
Chapter 4 Memory Table 4-14. FSTAT Field Descriptions (continued) Field Description 2 FBLANK Flag Indicating the Erase Verify Operation Status. When the FCCF flag is set after completion of an erase verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is cleared by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to the FBLANK flag has no effect on FBLANK. 0 Flash block verified as not erased.
Chapter 4 Memory 4. Effects resulting from illegal flash command write sequences or aborting flash operations 4.5.1.1 Writing the FCDIV Register Prior to issuing any flash command after a reset, write the FCDIV register to divide the bus clock down to 150–200 kHz. The FCDIV[PRDIV8, FDIV] bits must be set as described in Figure 4-9. For example, if the bus clock frequency is 25 MHz, FCDIV[FDIV] should be set to 0x0F (001111) and the FCDIV[PRDIV8] bit set to 1.
Chapter 4 Memory START PRDIV8 = 0 (reset) bus_clock 0.3MHz? yes ALL PROGRAM AND ERASE COMMANDS IMPOSSIBLE no bus_clock ≥ 12.8MHz? no yes set PRDIV8 = 1 PRDCLK = bus_clock/8 PRDCLK[kHz]/200 an integer? yes PRDCLK = bus_clock no set FDIV[5:0] = INT(PRDCLK[kHz]/200) set FDIV[5:0] = PRDCLK[kHz]/200-1 FCLK = (PRDCLK)/(1+FDIV[5:0]) END Note: • FCLK is the clock of the flash timing control block • INT(x) is the integer part of x (e.g. INT(4.323) = 4) Figure 4-9.
Chapter 4 Memory 2. Write a valid command to the FCMD register. 3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the command. After a command is launched, the completion of the command operation is indicated by the setting of FSTAT[FCCF]. The FCCF flag sets upon completion of all active and buffered burst program commands. 4.5.2 Flash Commands Table 4-16 summarizes the valid flash commands along with the effects of the commands on the flash block. Table 4-16.
Chapter 4 Memory START Read: FCDIV register Clock Register Written Check yes Note: FCDIV needs to be set after each reset no FDIVLD Set? Write: FCDIV register Read: FSTAT register no FCBEF Set? Command Buffer Empty Check yes Access Error and Protection Violation Check FACCERR/FPVIOL Set? no yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
Chapter 4 Memory If an address to be programmed is in a protected area of the flash block, FSTAT[FPVIOL] sets and the program command does not launch. After the program command has successfully launched and the program operation has completed, FSTAT[FCCF] is set.
Chapter 4 Memory 4.5.2.3 Burst Program Command The burst program operation programs previously erased data in the flash memory using an embedded algorithm. While burst programming, two internal data registers operate as a buffer and a register (2-stage FIFO) so that a second burst programming command along with the necessary data can be stored to the buffers while the first burst programming command remains in progress.
Chapter 4 Memory START Read: FCDIV register Clock Register Written Check yes Note: FCDIV needs to be set after each reset no FDIVLD Set? Write: FCDIV register Read: FSTAT register FCBEF Set? Command Buffer Empty Check no yes Access Error and Protection Violation Check FACCERR/FPVIOL Set? no yes 1. Write: Flash Array Address and Program Data 2. Write: FCMD register Burst Program Command 0x25 3.
Chapter 4 Memory An example flow to execute the sector erase operation is shown in Figure 4-13. The sector erase command write sequence is as follows: 1. Write to an aligned flash block address to start the command write sequence for the sector erase command. The flash address written determines the sector to be erased while the data written is ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3.
Chapter 4 Memory 4.5.2.5 Mass Erase Command The mass erase operation erases the entire flash array memory using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 4-14. The mass erase command write sequence is as follows: 1. Write to an aligned flash block address to start the command write sequence for the mass erase command. The address and data written is ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3.
NOTE The BDM can also perform a mass erase and verify command. See Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for details. 4.5.3 4.5.3.1 Illegal Flash Operations Flash Access Violations The FACCERR flag is set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a flash address before initializing the FCDIV register. 2. Writing a byte, word, or misaligned longword to a valid flash address. 3.
Chapter 4 Memory 4.5.3.2 Flash Protection Violations The FPVIOL flag is set after the command is written to the FCMD register if any of the following illegal operations are attempted: 1. Writing the program command if the address written in the command write sequence was in a protected area of the flash array. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the flash array. 3.
Chapter 4 Memory 4.5.5 Security The flash module provides the necessary security information to the MCU. During each reset sequence, the flash module determines the security state of the MCU as defined in Section 4.2.1, “Flash Module Reserved Memory Locations”. The contents of the flash security byte in the flash configuration field (see Section 4.4.2.
Chapter 4 Memory 5. If any of the keys are written on successive MCU clock cycles. 6. Executing a STOP instruction before all keys have been written. After the backdoor keys have been correctly matched, the MCU is unsecured. After the MCU is unsecured, the flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, you have full control of the contents of the backdoor keys by programming the associated addresses in the flash configuration field (see Section 4.2.
Chapter 4 Memory One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these timing pulses are used by the command processor to complete a program or erase command. Program and erase times are given in the MCF51QE128 Data Sheet, order number MCF51QE128DS. 4.6 Security The MCF51QE128/64/32 includes circuitry to prevent unauthorized access to the contents of flash and RAM memory.
Chapter 4 Memory Secure state unknown/unpowered N = number of cycles for SIM to release internal reset. Adder of 16 imposed by ColdFire core. Hold BKGD=0, apply power, wait N+16 cycles for POR to deassert BKGD=0 during reset ensures that ENBDM comes up ‘1’. Secure state unknown, CPU halted, FEI 10 MHz clock, SYNC required FLL enabled, internal reference (FEI) at 10MHz is reset default for the ICS.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt on the MCF51QE128/64/32. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this document. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control 5.3.1 Computer Operating Properly (COP) Watchdog The COP watchdog forces a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point.
Chapter 5 Resets, Interrupts, and General System Control 5.3.2 Illegal Operation Reset By default, the V1 ColdFire core generates a MCU reset when attempting to execute an illegal instruction (except for the ILLEGAL opcode), illegal line-A instruction, illegal line-F instruction, or a supervisor instruction while in user mode (privilege violation). The user may set CPUCR[IRD] to generate the appropriate exception instead of forcing a reset.
Chapter 5 Resets, Interrupts, and General System Control NOTE This pin does not contain a clamp diode to VDD and should not be driven above VDD. NOTE The voltage measured on the internally pulled up RESET pin is not pulled to VDD. The internal gates connected to this pin are pulled to VDD. The RESET pullup should not be used to pull up components external to the MCU. 5.4.1.2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels.
Chapter 5 Resets, Interrupts, and General System Control 5.5.2 LVD Reset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. SRS[LVD] is set following an LVD reset or POR. 5.5.
Chapter 5 Resets, Interrupts, and General System Control Refer to Chapter 4, “Memory”, for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation.
Chapter 5 Resets, Interrupts, and General System Control Table 5-2. IRQSC Register Field Descriptions (continued) Field Description 1 IRQIE IRQ Interrupt Enable. This read/write control bit determines whether IRQ events generate an interrupt request. 0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested when IRQF is set. 0 IRQMOD 5.7.2 IRQ Detection Mode. This read/write control bit selects edge-only detection or edge-and-level detection.
Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions (continued) Field Description 4 ILOP Illegal Opcode. Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes any illegal instruction (except the ILLEGAL (0x4AFC) opcode) or a privilege violation (execution of a supervisor instruction in user mode. The STOP instruction is considered illegal if SOPT1[STOPE,WAITE] are cleared.
Table 5-4. SOPT1 Register Field Descriptions Field Description 7 COPE COP Watchdog Enable. This write-once bit selects whether the COP watchdog is enabled. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 COPT COP Watchdog Timeout. This write-once bit selects the timeout period of the COP. COPT along with SOPT2[COPCLKS] defines the COP timeout period. 0 Short timeout period selected. 1 Long timeout period selected. 5 STOPE Stop Mode Enable.
Chapter 5 Resets, Interrupts, and General System Control Table 5-5. SOPT2 Register Field Descriptions Field 7 COPCLKS 6–4 3 SPI1PS Description COP Watchdog Clock Select. This write-once bit selects the clock source of the COP watchdog. 0 Internal 1-kHz clock is source to COP. 1 Bus clock is source to COP. Reserved, should be cleared. SPI1 Pin Select. This bit selects the location of the SPSCLK1, MOSI1, MISO1, and SS1 pins of the SPI1 module.
Chapter 5 Resets, Interrupts, and General System Control 7 6 5 4 3 2 R 1 0 0 0 ID[11:8] W Reset: — — — — 1 1 Figure 5-5. System Device Identification Register High (SDIDH) Table 5-6. SDIDH Register Field Descriptions Field 7–4 Reserved 3–0 ID[11:8] Description Reserved. Reading these bits results in an indeterminate value; writes have no effect. Part Identification Number. Each derivative in the ColdFire family has a unique identification number.
Chapter 5 Resets, Interrupts, and General System Control Table 5-8. SPMSC1 Register Field Descriptions Field 7 LVDF 6 LVDACK Description Low-Voltage Detect Flag. If LVDE is set, this read-only status bit indicates a low-voltage detect event. Low-Voltage Detect Acknowledge. This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads always return 0. 5 LVDIE Low-Voltage Detect Interrupt Enable. This bit enables hardware interrupt requests for LVDF.
Chapter 5 Resets, Interrupts, and General System Control Table 5-9. SPMSC2 Register Field Descriptions Field Description 7 LPR Low-Power Regulator Control. The LPR bit controls entry into the low-power run and low-power wait modes in which the voltage regulator is put into standby. This bit cannot be set if PPDC=1. If PPDC and LPR are set in a single write instruction, only PPDC is actually set. LPR is cleared when an interrupt occurs in low-power mode and the LPWUI bit is 1.
Chapter 5 Resets, Interrupts, and General System Control R 7 6 LVWF 0 W 5 4 3 LVDV LVWV LVWIE 2 1 0 0 0 0 LVWACK POR: 0 1 0 0 0 0 0 0 0 LVR: 01 0 U U 0 0 0 0 Any other reset: 01 0 U U 0 0 0 0 1 LVWF is set when VSupply transitions below the trip point or after reset and VSupply is already below VLVW. Figure 5-9. System Power Management Status and Control 3 Register (SPMSC3) Table 5-10.
Chapter 5 Resets, Interrupts, and General System Control 5.7.9 System Clock Gating Control 1 Register (SCGC1) This high page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IICx, and SCIx modules. Gating off the clocks to unused peripherals reduces the MCU’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information. 7 6 5 4 3 2 1 0 TPM3 TPM2 TPM1 ADC IIC2 IIC1 SCI2 SCI1 1 1 1 1 1 1 1 1 R W Reset: Figure 5-10.
Chapter 5 Resets, Interrupts, and General System Control 7 R 6 5 4 3 2 1 0 FLS IRQ KBIx ACMPx RTC SPI2 SPI1 1 1 1 1 1 1 1 1 W Reset: 1 Figure 5-11. System Clock Gating Control 2 Register (SCGC2) Table 5-13. SCGC2 Register Field Descriptions Field 7 Description Reserved, must be set. 6 FLS FTSR Clock Gate Control. This bit controls the bus clock gate to the flash registers. This bit does not affect normal program execution from the flash array.
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Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MCF51QE128/64 devices have up to nine parallel I/O ports that include a total of 70 I/O pins and one input-only and one output-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins.
Chapter 6 Parallel Input/Output Control It is good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin is not driven for a short time with an old data value that happened to be in the port data register. PTxDDn Data Direction Control D Output Enable Q PTxDn Port Data Register D Q Output Data 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure 6-1. Classic Parallel I/O Block Diagram 6.
Chapter 6 Parallel Input/Output Control 6.2.3 Port Drive Strength Select An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, ensure that the total current source and sink limits for the MCU are not exceeded.
Chapter 6 Parallel Input/Output Control The set/clear/toggle functionality allows software to affect an individual bit with a single write instruction, rather than using a read-modify-write sequence. 6.3.1 Port Data Set Registers The port data set registers (PTxSET) are write-only registers associated with ports C and E. Writing to these registers has the result: PortData = PortData || SetPattern. A subsequent port data register (PTxD) read reflects the changed result. 6.3.
Chapter 6 Parallel Input/Output Control BUSCLK KBACK 1 KBIxP0 RESET VDD 0 S KBF D CLRQ KBIPE0 SYNCHRONIZER CK KBEDG0 KEYBOARD INTERRUPT FF 1 KBIxPn 0 S KBIPEn STOP STOP BYPASS KBI INTERRUPT REQUEST KBIMOD KBIE KBEDGn Figure 6-3. Port Interrupt Block Diagram Writing to the KBIPEn bits in the keyboard x interrupt pin enable register (KBIxPE) independently enables or disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on KBIxSC[KBIMOD].
Chapter 6 Parallel Input/Output Control 6.5.4 Keyboard Interrupt Initialization When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt request during pin interrupt initialization, do the following: 1. Mask interrupts by clearing KBIxSC[KBIE]. 2. Select the pin polarity by setting the appropriate KBIxES[KBEDGn] bits. 3. If using internal pull-up/pull-down device, configure the associated pull enable bits in KBIxPE. 4.
Chapter 6 Parallel Input/Output Control The PTA4 and PTA5 pins are unique. PTA4 is an output only, so the control bits for the input functions do not have any effect on this pin. PTA5, when configured as an output, is open drain. Therefore, the drive strength and slew rate controls have no effect on this pin. 6.7.1.
Chapter 6 Parallel Input/Output Control 7 6 5 4 3 2 1 0 PTAPE7 PTAPE6 PTAPE5 PTAPE41 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 0 0 0 0 R W Reset: 1 PTAPE4 has no effect on the output-only PTA4 pin. Figure 6-6. Internal Pull Enable for Port A Register (PTAPE) Table 6-3. PTAPE Register Field Descriptions Field Description 7–0 PTAPEn Internal Pull Enable for Port A Bits.
Table 6-5. PTADS Register Field Descriptions Field Description 7–0 PTADSn Output Drive Strength Selection for Port A Bits. Each of these control bits selects between low and high output drive for the associated PTA pin. For port A pins configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. 6.7.2 Port B Registers Port B is controlled by the registers listed below. 6.7.2.
Chapter 6 Parallel Input/Output Control Table 6-7. PTBDD Register Field Descriptions Field Description 7–0 PTBDDn Data Direction for Port B Bits. These read/write bits control the direction of port B pins and what is read for PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. 6.7.2.
Chapter 6 Parallel Input/Output Control 6.7.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-13. Drive Strength Selection for Port B Register (PTBDS) Table 6-10. PTBDS Register Field Descriptions Field Description 7–0 PTBDSn Output Drive Strength Selection for Port B Bits. Each of these control bits selects between low and high output drive for the associated PTB pin.
Chapter 6 Parallel Input/Output Control 6.7.3.2 Port C Data Direction Register (PTCDD) 7 6 5 4 3 2 1 0 PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-15. Port C Data Direction Register (PTCDD) Table 6-12. PTCDD Register Field Descriptions Field Description 7–0 PTCDDn Data Direction for Port C Bits. These read/write bits control the direction of port C pins and what is read for PTCD reads.
Chapter 6 Parallel Input/Output Control Table 6-14. PTCCLR Register Field Descriptions Field Description 7–0 PTCCLRn 6.7.3.5 Data Clear for Port C Bits. Writing 0 to any bit in this location clears the corresponding bit in the data register. Writing a one to any bit in this register has no effect. 0 Corresponding PTCDn maintains current value. 1 Corresponding PTCDn is cleared.
Chapter 6 Parallel Input/Output Control 6.7.3.7 Port C Slew Rate Enable Register (PTCSE) 7 6 5 4 3 2 1 0 PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-20. Slew Rate Enable for Port C Register (PTCSE) Table 6-17. PTCSE Register Field Descriptions Field Description 7–0 PTCSEn Output Slew Rate Enable for Port C Bits. Each of these control bits determines if the output slew rate control is enabled for the associated PTC pin.
Chapter 6 Parallel Input/Output Control Table 6-19. PTDD Register Field Descriptions Field Description 7–0 PTDDn Port D Data Register Bits. For port D pins configured as inputs, reads return the logic level on the pin. For port D pins configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins configured as outputs, the logic level is driven out the corresponding MCU pin.
Chapter 6 Parallel Input/Output Control 6.7.4.4 Port D Slew Rate Enable Register (PTDSE) 7 6 5 4 3 2 1 0 PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-25. Slew Rate Enable for Port D Register (PTDSE) Table 6-22. PTDSE Register Field Descriptions Field Description 7–0 PTDSEn Output Slew Rate Enable for Port D Bits. Each of these control bits determines if the output slew rate control is enabled for the associated PTD pin.
Chapter 6 Parallel Input/Output Control Table 6-24. PTED Register Field Descriptions Field Description 7–0 PTEDn Port E Data Register Bits. For port E pins configured as inputs, reads return the logic level on the pin. For port E pins configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port E pins configured as outputs, the logic level is driven out the corresponding MCU pin.
Chapter 6 Parallel Input/Output Control 6.7.5.4 Port E Data Clear Register (PTECLR) 7 6 5 4 3 2 1 0 PTECLR7 PTECLR6 PTECLR5 PTECLR4 PTECLR3 PTECLR2 PTECLR1 PTECLR0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-30. Port E Data Clear Register (PTECLR) Table 6-27. PTECLR Register Field Descriptions Field Description 7–0 PTECLRn 6.7.5.5 Data Clear for Port E Bits. Writing 0 to any bit in this location clears the corresponding bit in the data register.
Table 6-29. PTEPE Register Field Descriptions Field Description 7–0 PTEPEn Internal Pull Enable for Port E Bits. Each of these control bits determines if the internal pull-up device is enabled for the associated PTE pin. For port E pins configured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port E bit n. 1 Internal pull-up device enabled for port E bit n. 6.7.5.
Chapter 6 Parallel Input/Output Control 6.7.6 Port F Registers Port F is controlled by the registers listed below. 6.7.6.1 Port F Data Register (PTFD) 7 6 5 4 3 2 1 0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-35. Port F Data Register (PTFD) Table 6-32. PTFD Register Field Descriptions Field Description 7–0 PTFDn Port F Data Register Bits. For port F pins configured as inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 7 6 5 4 3 2 1 0 PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-37. Internal Pull Enable for Port F Register (PTFPE) Table 6-34. PTFPE Register Field Descriptions Field Description 7–0 PTFPEn Internal Pull Enable for Port F Bits. Each of these control bits determines if the internal pull-up device is enabled for the associated PTF pin.
Chapter 6 Parallel Input/Output Control Table 6-36. PTFDS Register Field Descriptions Field Description 7–0 PTFDSn Output Drive Strength Selection for Port F Bits. Each of these control bits selects between low and high output drive for the associated PTF pin. For port F pins configured as inputs, these bits have no effect. 0 Low output drive strength selected for port F bit n. 1 High output drive strength selected for port F bit n. 6.7.
Chapter 6 Parallel Input/Output Control 6.7.7.3 Port G Pull Enable Register (PTGPE) The port G pull enable register enables pull-ups on the corresponding PTG pin. In some cases, a pull-down device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI). 7 6 5 4 3 2 1 0 PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-42. Internal Pull Enable for Port G Register (PTGPE) Table 6-39.
Chapter 6 Parallel Input/Output Control Table 6-41. PTGDS Register Field Descriptions Field Description 7–0 PTGDSn Output Drive Strength Selection for Port G Bits. Each of these control bits selects between low and high output drive for the associated PTG pin. For port G pins configured as inputs, these bits have no effect. 0 Low output drive strength selected for port G bit n. 1 High output drive strength selected for port G bit n. 6.7.
Chapter 6 Parallel Input/Output Control 6.7.8.3 Port H Pull Enable Register (PTHPE) The port H pull enable register enables pull-ups on the corresponding PTH pin. In some cases, a pull-down device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI). 7 6 5 4 3 2 1 0 PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-47. Internal Pull Enable for Port H Register (PTHPE) Table 6-44.
Chapter 6 Parallel Input/Output Control Table 6-46. PTHDS Register Field Descriptions Field Description 7–0 PTHDSn Output Drive Strength Selection for Port H Bits. Each of these control bits selects between low and high output drive for the associated PTH pin. For port H pins configured as inputs, these bits have no effect. 0 Low output drive strength selected for port H bit n. 1 High output drive strength selected for port H bit n. 6.7.
Chapter 6 Parallel Input/Output Control 6.7.9.3 Port J Pull Enable Register (PTJPE) The port J pull enable register enables pull-ups on the corresponding PTJ pin. In some cases, a pull-down device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI). 7 6 5 4 3 2 1 0 PTJPE7 PTJPE6 PTJPE5 PTJPE4 PTJPE3 PTJPE2 PTJPE1 PTJPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-52. Internal Pull Enable for Port J Register (PTJPE) Table 6-49.
Chapter 6 Parallel Input/Output Control Table 6-51. PTJDS Register Field Descriptions Field Description 7–0 PTJDSn Output Drive Strength Selection for Port J Bits. Each of these control bits selects between low and high output drive for the associated PTJ pin. For port J pins configured as inputs, these bits have no effect. 0 Low output drive strength selected for port J bit n. 1 High output drive strength selected for port J bit n. 6.7.
Chapter 6 Parallel Input/Output Control 6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-56. KBI1 Interrupt Pin Select Register (KBI1PE) Table 6-54. KBI1PE Register Field Descriptions Field 7–0 KBIPEn 6.7.10.3 Description KBI1 Interrupt Pin Selects. Each of the KBIPEn bits enable the corresponding KBI1 interrupt pin. 0 Pin not enabled as interrupt.
Chapter 6 Parallel Input/Output Control 6.7.11.1 R KBI2 Interrupt Status and Control Register (KBI2SC) 7 6 5 4 3 2 0 0 0 0 KBF 0 W Reset: 1 0 KBIE KBIMOD 0 0 KBACK 0 0 0 0 0 0 Figure 6-58. KBI2 Interrupt Status and Control Register (KBI2SC) Table 6-57. KBI2SC Register Field Descriptions Field Description 7–4 Reserved, should be cleared. 3 KBF KBI2 Interrupt Flag. KBF indicates when a KBI2 interrupt is detected. Writes have no effect on KBF. 0 No KBI2 interrupt detected.
6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) 7 6 5 4 3 2 1 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-60. KBI2 Edge Select Register (KBI2ES) Table 6-59. KBI2ES Register Field Descriptions Field Description 7–0 KBEDGn KBI2 Edge Selects. Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled.
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Chapter 7 ColdFire Core 7.1 Introduction This section describes the organization of the Version 1 (V1) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the ColdFire Family Programmer’s Reference Manual. 7.1.1 Overview As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.
ColdFire Core instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
ColdFire Core • • • • 16-bit status register (SR) 32-bit supervisor stack pointer (SSP) 32-bit vector base register (VBR) 32-bit CPU configuration register (CPUCR) Table 7-1. ColdFire Core Programming Model BDM Command1 Width (bits) Register Access Reset Value Written with Section/Page MOVEC2 Supervisor/User Access Registers Load: 0x60 Store: 0x40 Data Register 0 (D0) 32 R/W 0xCF10_0029 No 7.2.1/7-147 Load: 0x61 Store: 0x41 Data Register 1 (D1) 32 R/W 0x1090_0050 No 7.2.
ColdFire Core NOTE Registers D0 and D1 contain hardware configuration details after reset. See Section 7.3.3.14, “Reset Exception” for more details. BDM: Load: 0x60 + n; n = 0-7 (Dn) Store: 0x40 + n; n = 0-7 (Dn) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 Data W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – (D2-D7) Reset (D0, D1) See Section 7.3.3.14, “Reset Exception” Figure 7-2.
ColdFire Core To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay,USP;move to USP move.l USP,Ax;move from USP These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register. NOTE The USP must be initialized using the move.l entry into user mode.
ColdFire Core Table 7-2. CCR Field Descriptions Field 7–5 Description Reserved, must be cleared. 4 X Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified result. 3 N Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if result equals zero; otherwise cleared. 1 V Overflow condition code bit.
ColdFire Core BDM: 0x801 (VBR) Load: 0xE1 (VBR) Store: 0xC1 (VBR) Access: Supervisor read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 0 0 0 0 0 0 0 0 Base Address W 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7-7. Vector Base Register (VBR) 7.2.
ColdFire Core Table 3. CPUCR Field Descriptions (continued) Field Description 27 BWD Buffered peripheral bus write disable. 0 Peripheral bus writes are buffered and the bus cycle is terminated immediately and does not wait for the peripheral bus termination status. 1 Disables the buffering of peripheral bus writes and does not terminate the bus cycle until a registered version of the peripheral bus termination is received.
ColdFire Core Table 7-4. SR Field Descriptions (continued) Field Description 10–8 I Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to current level, except edge-sensitive level 7 requests, which cannot be masked. 7–0 CCR Refer to Section 7.2.4, “Condition Code Register (CCR)”. 7.3 7.3.
ColdFire Core Table 7-5. Instruction Enhancements over Revision ISA_A (continued) Instruction Move from USP Move to USP User Stack Pointer → Destination register Source register → User Stack Pointer MVS.{B,W} Sign-extends source operand and moves it to destination register. MVZ.{B,W} Zero-fills source operand and moves it to destination register. SATS.L Performs saturation operation for signed arithmetic and updates destination register, depending on CCR[V] and bit 31 of the register. TAS.
ColdFire Core 3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure 7-10, the processor uses a simplified fixed-length stack frame for all exceptions.
ColdFire Core Table 7-6.
ColdFire Core Table 7-7. Format Field Encodings • Original SSP @ Time of Exception, Bits 1:0 SSP @ 1st Instruction of Handler Format Field 00 Original SSP - 8 0100 01 Original SSP - 9 0101 10 Original SSP - 10 0110 11 Original SSP - 11 0111 There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 7-8. Table 7-8.
ColdFire Core Table 7-9.
ColdFire Core 7.3.3 7.3.3.1 Processor Exceptions Access Error Exception The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an access error (also known as a bus error) is detected. If CPUCR[ARD] is set, the reset is disabled and a processor exception is generated as detailed below. The exact processor response to an access error depends on the memory reference being performed.
ColdFire Core 7.3.3.3 Illegal Instruction Exception The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is generated as detailed below. There is one special case involving the ILLEGAL opcode (0x4AFC); attempted execution of this instruction always generates an illegal instruction exception, regardless of the state of the CPUCR[IRD] bit.
ColdFire Core In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors associated with illegal opwords in these two lines. Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4).
ColdFire Core If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2. Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types.
ColdFire Core The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a format error on a ColdFire processor.
ColdFire Core 7.3.3.14 Reset Exception Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.
ColdFire Core Table 7-11. D0 Hardware Configuration Info Field Description Field Description 31–24 PF Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present. 23–20 VER ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core. 0001 V1 ColdFire core (This is the value used for this device.) 0010 V2 ColdFire core 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V5 ColdFire core Else Reserved for future use.
ColdFire Core Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
ColdFire Core 7.3.4 Instruction Execution Timing This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where: • C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.
ColdFire Core 7.3.4.2 MOVE Instruction Execution Times Table 7-14 lists execution times for MOVE.{B,W} instructions; Table 7-15 lists timings for MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode. ET with { = (d16,PC)} equals ET with { = (d16,An)} ET with { = (d8,PC,Xi*SF)} equals ET with { = (d8,An,Xi*SF)} The nomenclature xxx.
ColdFire Core Table 7-15. MOVE Long Execution Times (continued) Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl (d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — — 7.3.4.
ColdFire Core 7.3.4.4 Standard Two Operand Instruction Execution Times Table 7-17. Two Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx ADD.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ADD.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ADDI.L #imm,Dx 1(0/0) — — — — — — — ADDQ.
ColdFire Core Table 7-17. Two Operand Instruction Execution Times (continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx SUB.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBI.L #imm,Dx 1(0/0) — — — — — — — SUBQ.L #imm, 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBX.
ColdFire Core Table 7-18. Miscellaneous Instruction Execution Times (continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx TPF.W 1(0/0) — — — — — — — TPF.L 1(0/0) — — — — — — — UNLK Ax 2(1/0) — — — — — — — WDDATA — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — WDEBUG — 5(2/0) — — 5(2/0) — — — 1 The n is the number of registers moved by the MOVEM opcode. If a MOVE.
Chapter 8 Interrupt Controller (CF1_INTC) 8.1 Introduction This interrupt controller (CF1_INTC) is intended for use in low-cost microcontroller designs using the Version 1 (V1) ColdFire processor core. In keeping with the general philosophy for devices based on this low-end 32-bit processor, the interrupt controller generally supports less programmability compared to similar modules in other ColdFire microcontrollers and embedded microprocessors.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-1. Exception Processing Comparison (continued) Attribute HCS08 V1 ColdFire Software IACK No Yes Exit Instruction from ISR RTI RTE 8.1.1 Overview Interrupt exception processing includes interrupt recognition, aborting the current instruction execution stream, storing of an 8-byte exception stack frame in memory, calculation of the appropriate vector, and passing control to the specified interrupt service routine.
Chapter 8 Interrupt Controller (CF1_INTC) • type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next). For interrupts, the stacked PC is always the address of the next instruction to be executed. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1-Mbyte boundary.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-2.
Chapter 8 Interrupt Controller (CF1_INTC) means the 30 sources are mapped to a sparsely-populated two-dimensional ColdFire array of seven interrupt levels and nine priorities within the level.
Chapter 8 Interrupt Controller (CF1_INTC) • • • • • • 8.1.
Chapter 8 Interrupt Controller (CF1_INTC) The programming model follows the definition from previous ColdFire interrupt controllers. This compatibility accounts for the various memory holes in this module’s memory map. 8.3.1 Memory Map The CF1_INTC module is based at address 0x(FF)FF_FFC0 (referred to as CF1_INTC_BASE throughout the chapter) and occupies the upper 64 bytes of the peripheral space. The module memory map is shown in Table 8-3. Table 8-3.
Chapter 8 Interrupt Controller (CF1_INTC) NOTE Take special notice of the bit numbers within this register, 39–32. This is for compatibility with previous ColdFire interrupt controllers. Offset: CF1_INTC_BASE + 0x13 (INTC_FRC) 39 R Access: Read/Write 38 37 36 35 34 33 32 LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 0 0 0 0 0 0 0 0 W Reset 0 Figure 8-2. INTC_FRC Register Table 8-4. INTC_FRC Field Descriptions Field 39 Description Reserved, must be cleared.
Chapter 8 Interrupt Controller (CF1_INTC) NOTE The requests associated with the INTC_FRC register have a fixed level and priority that cannot be altered. The INTC_PL6P7 register specifies the highest-priority, maskable interrupt request, which is defined as the level six, priority seven request. The INTC_PL6P6 register specifies the second-highest-priority, maskable interrupt request defined as the level six, priority six request. Reset clears both registers, disabling any request re-mapping.
Chapter 8 Interrupt Controller (CF1_INTC) The interrupt controller's wake-up signal is defined as: wake-up = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK]) Reset state of the INTC_WCR is disabled, so this register must be written to enable the wake-up condition before the core executes any STOP instructions. Offset: CF1_INTC_BASE + 0x1B (INTC_WCR) 7 R Access: Read/Write 6 5 4 3 0 0 0 0 2 1 ENB 0 MASK W Reset 0 0 0 0 0 0 0 0 Figure 8-4.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-7. INTC_SFRC Field Descriptions Field Description 7–6 Reserved, must be cleared. 5–0 SET For data values within the 32–38 range, the corresponding bit in the INTC_FRC register is set, as defined below. 0x20 Bit 32, INTC_FRC[LVL7] is set. 0x21 Bit 33, INTC_FRC[LVL6] is set. 0x22 Bit 34, INTC_FRC[LVL5] is set. 0x23 Bit 35, INTC_FRC[LVL4] is set. 0x24 Bit 36, INTC_FRC[LVL3] is set. 0x25 Bit 37, INTC_FRC[LVL2] is set. 0x26 Bit 38, INTC_FRC[LVL1] is set.
Chapter 8 Interrupt Controller (CF1_INTC) 8.3.2.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) The eight read-only interrupt acknowledge (IACK) registers can be explicitly addressed via memory-mapped accesses or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing when CPUCR[IAE] is set. In either case, the interrupt controller's actions are very similar. First, consider an IACK cycle to a specific level, a level-n IACK.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-9. INTC_SWIACK, INTC_LVLnIACK Field Descriptions Field Description 7 Reserved, must be cleared. 6–0 VECN Vector number. Indicates the appropriate vector number. For the SWIACK register, it is the highest-level, highest-priority request currently being asserted in the CF1_INTC module. If there are no pending requests, VECN is zero. For the LVLnIACK register, it is the highest priority request within the specified level-n.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-11.
Chapter 8 Interrupt Controller (CF1_INTC) Table 8-12.
Chapter 8 Interrupt Controller (CF1_INTC) special case. The edge-sensitive nature of these requests means the encoded 3-bit level input from the CF1_INTC to the V1 ColdFire core must change state before the CPU detects an interrupt. A non-maskable interrupt (NMI) is generated each time the encoded interrupt level changes to level seven (regardless of the SR[I] field) and each time the SR[I] mask changes from seven to a lower value while the encoded request level remains at seven. 8.
Chapter 8 Interrupt Controller (CF1_INTC) To emulate the HCS08’s 1-level IRQ nesting mechanisms, the ColdFire implementation enables interrupts by clearing SR[I] (typically when using RTE to return to a process) and disables interrupts upon entering every interrupt service routine by one of three methods: 1. Execution of STLDSR #0x2700 as the first instruction of an ISR. 2. Execution of MOVE.w #0x2700,SR as the first instruction of an ISR. 3.
Chapter 8 Interrupt Controller (CF1_INTC) align 4 irqxx_entry: 00588: 4fef fff0 lea -16(sp),sp 0058c: 48d7 0303 movem.l #0x0303,(sp) # allocate stack space # save d0/d1/a0/a1 on stack irqxx_alternate_entry: 00590: .... 005c0: 005c4: 005c8: 005ca: 005cc: 005d0: 71b8 0c00 6f0a 91c8 2270 4ee9 irqxx_swiack: ffe0 mvz.b INTC_SWIACK.w,d0 0041 cmpi.b #0x41,d0 ble.b irqxx_exit sub.l a0,a0 0c00 move.l 0(a0,d0.l*4),a1 0008 jmp 8(a1) align 4 irqxx_exit: 005d4: 4cd7 0303 movem.
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Chapter 9 Rapid GPIO (RGPIO) 9.1 Introduction The Rapid GPIO (RGPIO) module provides a 16-bit general-purpose I/O module directly connected to the processor’s high-speed 32-bit local platform bus. This connection to the processor’s high-speed platform bus plus support for single-cycle, zero wait-state data transfers allows the RGPIO module to provide improved pin performance when compared to more traditional GPIO modules located on the internal slave peripheral bus.
Chapter 9 Rapid GPIO (RGPIO) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME COUNTER (RTC)
Chapter 9 Rapid GPIO (RGPIO) 9.1.1 Overview The RGPIO module provides 16-bits of high-speed GPIO functionality, mapped to the processor’s platform bus.
Chapter 9 Rapid GPIO (RGPIO) V1 ColdFire core IFP IA Generation IAG Instruction Fetch Cycle IC Address, Attributes FIFO Instruction Buffer IB Local Bus Controller Read Data OEP DSOC Decode & Select, Operand Fetch AGEX Address Generation, Execute Write Data BDC/Debug Internal Bus Flash Controller BKGD Flash Array RAM Controller SRAM Array RGPIO Controller RGPIO Pins Peripheral Bridge Peripheral Bus Figure 9-2. V1 ColdFire Block Diagram MCF51QE128 MCU Series Reference Manual, Rev.
Chapter 9 Rapid GPIO (RGPIO) A simplified block diagram of the RGPIO module is shown in Figure 9-3. The details of the pin muxing and pad logic are device-specific. RGPIO module data to module 0 16 0 16 31 31 Pin Enables 31 15 Direction decode address Control Write D ata mux 0 Read D ata 16 15 31 rgpio_enable rgpio_direction rgpio_data_out rgpio_data_in 0 31 data from module Pin Muxing + Pad Logic On-platform Bus RGPIO_DATA[15:0] Figure 9-3. RGPIO Block Diagram 9.1.
Chapter 9 Rapid GPIO (RGPIO) – Register for reading current pin state – The two data registers (read, write) are mapped to a single program-visible location — Alternate addresses to perform data set, clear, and toggle functions using simple writes — Separate read and write programming model views enable simplified driver software – Support for any access size (byte, word, or longword) 9.1.3 Modes of Operation The RGPIO module does not support any special modes of operation.
Chapter 9 Rapid GPIO (RGPIO) 9.3 Memory Map/Register Definition The RGPIO module provides a compact 16-byte programming model based at a system memory address of 0x(00)C0_0000 (noted as RGPIO_BASE throughout the chapter). As previously noted, the programming model views are different between reads and writes as this enables simplified software for manipulation of the RGPIO pins. Additionally, the programming model can be referenced using any operand size access (byte, word, longword). 9.3.
Chapter 9 Rapid GPIO (RGPIO) 9.3.2 Register Descriptions The RGPIO module provides 16 bits of high-speed general-purpose input/output functionality via a connection to the processor’s 32-bit local bus. As a result, the RGPIO programming model is defined with a 32-bit organization. The basic size of each program-visible register is 16 bits, but the programming model may be referenced using byte (8-bit), word (16-bit), or longword (32-bit) accesses. Performance is typically maximized using 32-bit accesses.
Chapter 9 Rapid GPIO (RGPIO) Offset: RGPIO_Base + 0x2 (RGPIO_DATA) RGPIO_Base + 0x6 RGPIO_Base + 0xA RGPIO_Base + 0xE 15 14 13 12 11 Access: Read/write Read/Indirect Write Read/Indirect Write Read/Indirect Write 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DATA W Reset 7 0 0 0 0 0 0 0 0 Figure 9-5. RGPIO Data Register (RGPIO_DATA) Table 9-6. RGPIO_DATA Field Descriptions Field Description 15–0 DATA RGPIO data.
Chapter 9 Rapid GPIO (RGPIO) Offset: RGPIO_Base + 0x6 (RGPIO_CLR) 15 14 13 12 11 Access: Write-only 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — R W Reset CLR — — — — — — — — Figure 9-7. RGPIO Clear Data Register (RGPIO_CLR) Table 9-8. RGPIO_CLR Field Descriptions Field 15–0 CLR Description RGPIO clear data. 0 Clears the corresponding bit in the RGPIO_DATA register. 1 No effect. 9.3.2.
Chapter 9 Rapid GPIO (RGPIO) Offset: RGPIO_Base + 0xE (RGPIO_TOG) 15 14 13 12 11 Access: Write-only 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — R W Reset TOG — — — — — — — — Figure 9-9. RGPIO Toggle Data Register (RGPIO_TOG) Table 9-10. RGPIO_TOG Field Descriptions Field 15–0 TOG 9.4 Description RGPIO Toggle Data. 0 No effect.
Chapter 9 Rapid GPIO (RGPIO) • • BCHG_LOOP: In this loop, a bit change instruction was executed using the GPIO data byte as the operand. This instruction performs a read-modify-write operation and inverts the addressed bit. A pulse counter is decremented until the appropriate number of square-wave pulses have been generated. SET+CLR_LOOP: For this construct, two store instructions are executed: one to set the GPIO data pin and another to clear it.
Chapter 9 Rapid GPIO (RGPIO) align 16 send_16b_spi_message_rgpio: 00510: 4fef fff4 lea -12(%sp),%sp # 00514: 48d7 008c movm.l &0x8c,(%sp) # 00518: 3439 0080 0582 mov.w RAM_BASE+message2,%d2 0051e: 760f movq.l &15,%d3 # 00520: 7e10 movq.l &16,%d7 # 00522: 207c 00c0 0003 mov.l &RGPIO_DATA+1,%a0 # 00528: 203c 0000 ffff mov.l &0xffff,%d0 # 0052e: 3140 fffd mov.w %d0,-3(%a0) # 00532: 3140 0001 mov.
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Chapter 10 Analog Comparator 3V (ACMPVLPV1) 10.1 Introduction MCF51QE128 Series MCUs have two independent analog comparators (ACMPs), named ACMP1 and ACMP2. The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation).
Chapter 10 Analog Comparator 3V (ACMPVLPV1) 10.1.4 Interrupt Vectors ACMP1 and ACMP2 share a single interrupt vector. When interrupts are enabled for both ACMPs, the ACF bit in ACMP1SC and ACMP2SC must be polled to determine which ACMP caused the interrupt. See Chapter 8, “Interrupt Controller (CF1_INTC),” for the ACMP interrupt vector assignment. MCF51QE128 MCU Series Reference Manual, Rev. 3 208 Freescale Semiconductor Get the latest version from freescale.
Chapter 10 Analog Comparator 3V (ACMPVLPV1) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME
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Analog Comparator (S08ACMPVLPV1) 10.1.5 Features The ACMP has the following features: • Full rail-to-rail supply operation • Less than 40 mV of input offset • Less than 15 mV of hysteresis • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output • Option to compare to fixed internal bandgap reference voltage 10.1.6 10.1.6.1 Modes of Operation Wait Mode Operation During wait mode the ACMP, if enabled, continues to operate normally.
Analog Comparator (S08ACMPVLPV1) Internal Bus Internal Reference ACIE ACBGS Status & Control Register ACPE ACO AC IRQ ACF + SET ACF ACMP1 ACMOD2 ACMOD1 ACOPE Interrupt Control – ACMPx0 ACMP0 Figure 10-2. Analog Comparator Module Block Diagram 10.2 External Signal Description The ACMP has two analog input pins: ACMP0 and ACMP1. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU.
Analog Comparator (S08ACMPVLPV1) Table 10-1. ACMPxSC Field Descriptions Field 7 ACME 6 ACBGS Description Analog Comparator Module Enable — The ACME bit enables the ACMP module. When the module is not enabled, it remains in a low power state. 0 Analog Comparator disabled. 1 Analog Comparator enabled. Analog Comparator Bandgap Select — The ACBGS bit selects the internal bandgap as the comparator reference. 0 External pin ACMP1 selected as comparator non-inverting input.
Analog Comparator (S08ACMPVLPV1) ACIE bit or the ACF bit. The ACIE bit is cleared by writing a logic zero and the ACF bit is cleared by writing a logic one. MCF51QE128 MCU Series Reference Manual, Rev.
Chapter 11 Analog-to-Digital Converter (S08ADC12V1) 11.1 Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. Figure 11-1 shows the MCF51QE128 Series with the ADC module and pins highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MCF51QE128 device does not support it. 11.1.
Chapter 11 Analog-to-Digital Converter (S08ADC12V1) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) R
Chapter 11 Analog-to-Digital Converter (S08ADC12V1) 11.1.2 Module Configurations This section provides device-specific information for configuring the ADC on the MCF51QE128 Series. 11.1.2.1 Channel Assignments The ADC channel assignments for the MCF51QE128 Series devices are shown in Table 11-1. Reserved channels convert to an unknown value. Table 11-1.
Chapter 11 Analog-to-Digital Converter (S08ADC12V1) 11.1.2.3 Hardware Trigger The ADC may initiate a conversion via software or a hardware trigger. The RTC can be enabled as the hardware trigger for the ADC module by setting ADCSC2[ADTRG]. When enabled, the ADC is triggered each time RTCINT matches RTCMOD. The RTC interrupt does not have to be enabled to trigger the ADC. The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3. 11.1.2.
Analog-to-Digital Converter (S08ADC12V1) 11.1.
Analog-to-Digital Converter (S08ADC12V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 11-2.
Analog-to-Digital Converter (S08ADC12V1) 11.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 11.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Analog-to-Digital Converter (S08ADC12V1) 7 R 6 5 AIEN ADCO 0 0 4 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 Figure 11-3. Status and Control Register (ADCSC1) Table 11-3. ADCSC1 Field Descriptions Field Description 7 COCO Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Analog-to-Digital Converter (S08ADC12V1) 11.3.2 Status and Control Register 2 (ADCSC2) The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module. 7 R 6 5 4 ADTRG ACFE ACFGT 0 0 0 ADACT 3 2 0 0 0 0 1 0 R1 R1 0 0 W Reset: 0 Figure 11-4. Status and Control Register 2 (ADCSC2) 1 Bits 1 and 0 are reserved bits that must always be written to 0. Table 11-5.
Analog-to-Digital Converter (S08ADC12V1) If the MODE bits are changed, any data in ADCRH becomes invalid. R 7 6 5 4 3 2 1 0 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0 0 0 0 0 0 0 0 W Reset: Figure 11-5. Data Result High Register (ADCRH) 11.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion.
Analog-to-Digital Converter (S08ADC12V1) In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 – ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare. 11.3.6 Compare Value Low Register (ADCCVL) This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value.
Analog-to-Digital Converter (S08ADC12V1) Table 11-6. ADCCFG Register Field Descriptions (continued) Field Description 3:2 MODE Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 11-8. 1:0 ADICLK Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See Table 11-9. Table 11-7.
Analog-to-Digital Converter (S08ADC12V1) used to control the pins associated with channels 0–7 of the ADC module. 7 6 5 4 3 2 1 0 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 0 0 0 0 0 0 0 0 R W Reset: Figure 11-10. Pin Control 1 Register (APCTL1) Table 11-10. APCTL1 Register Field Descriptions Field Description 7 ADPC7 ADC Pin Control 7. ADPC7 controls the pin associated with channel AD7.
Analog-to-Digital Converter (S08ADC12V1) Table 11-11. APCTL2 Register Field Descriptions Field Description 7 ADPC15 ADC Pin Control 15. ADPC15 controls the pin associated with channel AD15. 0 AD15 pin I/O control enabled 1 AD15 pin I/O control disabled 6 ADPC14 ADC Pin Control 14. ADPC14 controls the pin associated with channel AD14. 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADPC13 ADC Pin Control 13. ADPC13 controls the pin associated with channel AD13.
Analog-to-Digital Converter (S08ADC12V1) Table 11-12. APCTL3 Register Field Descriptions Field Description 7 ADPC23 ADC Pin Control 23. ADPC23 controls the pin associated with channel AD23. 0 AD23 pin I/O control enabled 1 AD23 pin I/O control disabled 6 ADPC22 ADC Pin Control 22. ADPC22 controls the pin associated with channel AD22. 0 AD22 pin I/O control enabled 1 AD22 pin I/O control disabled 5 ADPC21 ADC Pin Control 21. ADPC21 controls the pin associated with channel AD21.
Analog-to-Digital Converter (S08ADC12V1) 11.4.1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. • The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of the bus clock.
Analog-to-Digital Converter (S08ADC12V1) 11.4.4.1 Initiating Conversions A conversion is initiated: • Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected. • Following the transfer of the result to the data registers when continuous conversion is enabled.
Analog-to-Digital Converter (S08ADC12V1) 11.4.4.4 Power Control The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, the ADACK clock generator is also enabled. Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value for fADCK (see the electrical specifications). 11.4.4.
Analog-to-Digital Converter (S08ADC12V1) example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: Conversion time = 23 ADCK Cyc 8 MHz/1 + 5 bus Cyc 8 MHz = 3.5 ms Number of bus cycles = 3.5 ms x 8 MHz = 28 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. 11.4.
Analog-to-Digital Converter (S08ADC12V1) 11.4.7 MCU Stop3 Mode Operation Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 11.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.
Analog-to-Digital Converter (S08ADC12V1) NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 11.5.1 ADC Module Initialization Example 11.5.1.1 Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1.
Analog-to-Digital Converter (S08ADC12V1) ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 Check COCO=1? No Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue Figure 11-13. Initialization Flowchart for Example 11.
Analog-to-Digital Converter (S08ADC12V1) 11.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) available as separate pins on some devices. VSSAD is shared on the same pin as the MCU digital VSS on some devices. On other devices, VSSAD and VDDAD are shared with the MCU digital supply pins.
Analog-to-Digital Converter (S08ADC12V1) For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are straight-line linear conversions.
Analog-to-Digital Converter (S08ADC12V1) • — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC.
Analog-to-Digital Converter (S08ADC12V1) • • • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 241 Get the latest version from freescale.
Analog-to-Digital Converter (S08ADC12V1) MCF51QE128 MCU Series Reference Manual, Rev. 3 242 Freescale Semiconductor Get the latest version from freescale.
Chapter 12 Internal Clock Source (S08ICSV3) 12.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock. The ICSTRM and FTRIM bits are normally reset to the factory trim values on any reset.
Chapter 12 Internal Clock Source (S08ICSV3) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME
Chapter 12 Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 245 Get the latest version from freescale.
Chapter 12 Internal Clock Source (S08ICSV3) MCF51QE128 MCU Series Reference Manual, Rev. 3 246 Freescale Semiconductor Get the latest version from freescale.
Internal Clock Source (S08ICSV3) 12.1.
Internal Clock Source (S08ICSV3) 12.1.4 Block Diagram Figure 12-2 is the ICS block diagram. External Reference Clock HGO EREFS ERCLKEN EREFSTEN IRCLKEN ICSERCLK ICSIRCLK RANGE CLKS BDIV IREFSTEN / 2n Internal Reference Clock DCOOUT LP ICSDCLK FLL n=0–10 RDIV /2 ICSLCLK DCOL Filter DCOM DCOH / 2n FTRIM TRIM ICSOUT n=0–3 IREFS DMX32 DRS ICSFFCLK DRST IREFST CLKST OSCINIT Internal Clock Source Block Figure 12-2. Internal Clock Source (ICS) Block Diagram 12.1.
Internal Clock Source (S08ICSV3) 12.1.5.4 FLL Bypassed Internal Low Power (FBILP) In FLL bypassed internal low-power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. 12.1.5.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock.
Internal Clock Source (S08ICSV3) 12.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 12-3. ICS Control Register 1 (ICSC1) Table 12-2. ICSC1 Field Descriptions Field Description 7:6 CLKS Clock Source Select. Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits. 00 Output of FLL is selected. 01 Internal reference clock is selected.
Internal Clock Source (S08ICSV3) 12.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 12-4. ICS Control Register 2 (ICSC2) Table 12-4. ICSC2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider. Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency.
Internal Clock Source (S08ICSV3) Table 12-5. ICSTRM Field Descriptions Field Description 7:0 TRIM ICS Trim Setting. The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ affects are binary weighted (bit 1 adjusts twice as much as bit 0). Increasing the binary value in TRIM increases the period and decreasing the value decreases the period. An additional fine trim bit is available in ICSSC as the FTRIM bit. 12.3.
Internal Clock Source (S08ICSV3) Table 12-6. ICSSC Field Descriptions (continued) Field Description 1 OSCINIT OSC Initialization. If EREFS is set and the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared. 0 FTRIM ICS Fine Trim.
Internal Clock Source (S08ICSV3) 12.4 Functional Description 12.4.
Internal Clock Source (S08ICSV3) 12.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: • • • CLKS bits are written to 00. IREFS bit is written to 0. RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock controlled by the external reference clock.
Internal Clock Source (S08ICSV3) In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The external reference clock controls the FLL clock, and the FLL loop locks the FLL frequency to the FLL factor times the external reference frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external reference clock is enabled. 12.4.1.
Internal Clock Source (S08ICSV3) 12.4.4 Low Power Bit Usage The low-power bit (LP) is provided to allow the FLL to be disabled and conserve power when it is not being used. The DRS bits can not be written while LP bit is 1. However, in some applications, it may be desirable to allow the FLL to be enabled and to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 12.4.5 DCO Maximum Frequency with 32.
Internal Clock Source (S08ICSV3) 12.4.8 Fixed Frequency Clock 12.4.9 The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Local Clock The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low-power (FBILP) and FLL bypassed external low-power (FBELP) modes.
Chapter 13 Inter-Integrated Circuit (S08IICV2) 13.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of bus clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
Chapter 13 Inter-Integrated Circuit (S08IICV2) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME CO
Chapter 13 Inter-Integrated Circuit (S08IICV2) MCF51QE128 MCU Series Reference Manual, Rev. 3 Freescale Semiconductor 261 Get the latest version from freescale.
13.1.
13.1.5 Block Diagram Figure 13-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.
Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0 0 0 0 0 0 R 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-3.
Table 13-3. IICF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
Table 13-5.
13.3.3 IIC Control Register (IICC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-5. IIC Control Register (IICC1) Table 13-6. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested.
13.3.4 IIC Status Register (IICS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. IIC Status Register (IICS) Table 13-7. IICS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.
13.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 13-7. IIC Data I/O Register (IICD) Table 13-8. IICD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Table 13-9. IICC2 Field Descriptions Field Description 7 GCAEN General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2–0 AD[10:8] Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme.
msb SCL 1 lsb 2 3 4 5 6 7 8 msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W SDA Calling Address Start Signal 1 3 4 5 6 7 8 Start Signal Calling Address 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 1 XX Read/ Ack Write Bit Repeated Start Signal 9 No Ack Bit msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W SDA 2 Data Byte lsb 2 1 Read/ Ack Write Bit msb SCL XXX lsb Stop Signal lsb 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W New Calling Address Read/ Write No Ack Bit St
13.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 13-9.
the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the SCL line low until the clock high state is reached.
13.4.2 10-bit Address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 13.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 13-10).
13.4.3 General Call Address General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after the first byte transfer to determine whether the address matches is its own slave address or a general call.
Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it.
13.7 Initialization/Application Information 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7.
Clear IICIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 TX/RX ? Generate Stop Signal (MST = 0) Y Set TX Mode RX TX N (Write) N N Data Transfer See Note 2 ACK from Receiver ? N Switch to Rx Mode Dummy Read fro
MCF51QE128 MCU Series Reference Manual, Rev.
MCF51QE128 MCU Series Reference Manual, Rev.
Chapter 14 Real-Time Counter (S08RTCV1) 14.1 Introduction The real-time counter (RTC) consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar, or any task scheduling functions. It can also serve as a cyclic wake up from low-power modes without the need of external components. 14.1.
Chapter 14 Real-Time Counter (S08RTCV1) 14.1.5 Interrupt Vector See Chapter 8, “Interrupt Controller (CF1_INTC),” for the RTC interrupt vector assignment. MCF51QE128 MCU Series Reference Manual, Rev. 3 282 Freescale Semiconductor Get the latest version from freescale.
Chapter 14 Real-Time Counter (S08RTCV1) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME COU
14.1.6 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 14.1.7 Modes of Operation This section defines the operation in stop, wait and background debug modes. 14.1.7.
14.1.8 Block Diagram The block diagram for the RTC module is shown in Figure 14-1. LPO Clock Source Select ERCLK IRCLK 8-Bit Modulo (RTCMOD) RTCLKS VDD RTCLKS[0] Q D Background Mode RTCPS Prescaler Divide-By E 8-Bit Comparator RTC Clock RTC Interrupt Request RTIF R Write 1 to RTIF 8-Bit Counter (RTCCNT) RTIE Figure 14-1. Real-Time Counter (RTC) Block Diagram 14.2 External Signal Description The RTC does not include any off-chip signals. 14.
14.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 0 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 Figure 14-2. RTC Status and Control Register (RTCSC) Table 14-2.
14.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 RTCCNT W Reset: 0 0 0 0 Figure 14-3. RTC Counter Register (RTCCNT) Table 14-4. RTCCNT Field Descriptions Field Description 7:0 RTCCNT RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register.
RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 14-6 shows different prescaler period values. Table 14-6. Prescaler Period RTCPS 1-kHz Internal Clock (RTCLKS = 00) 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250 μs 32 ms 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.
Internal 1-kHz Clock Source RTC Clock (RTCPS = 0x2) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 14-5. RTC Counter Overflow Example In the example of Figure 14-5, the selected clock source is the internal clock source. The prescaler (RTCPS) is set to 0x2 or divide-by-4. The modulo value in the RTCMOD register is set to 0x55. When the counter, RTCCNT, reaches the modulo value of 0x55, the counter overflows to 0x00 and continues counting.
Notes : Interrupt service routine for RTC module. **********************************************************************/ #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.
Chapter 15 Serial Communications Interface (S08SCIV4) 15.1 Introduction Figure 15-1 shows the MCF51QE128 Series block diagram with the SCI highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MCF51QE128 device does not support it. 15.1.1 SCI Clock Gating The bus clock to SCI1 and SCI2 can be gated on and off using the SCGC1[SCI1,SCI2] bits, respectively. These bits are set after any reset, which enables the bus clock to these modules.
Chapter 15 Serial Communications Interface (S08SCIV4) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2)
Chapter 15 Serial Communications Interface (S08SCIV4) Module Initialization: Write: SCIxBDH:SCIxBDL to set baud rate Write: SCIxC1 to configure 1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used. Write; SCIxC2 to configure interrupts, enable Rx and Tx, RWU Enable Rx wakeup, SBK sends break character Write: SCIxC3 to enable Rx error interrupt sources. Also controls pin direction in 1-wire modes. R8 and T8 only used in 9-bit data modes.
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15.1.
15.1.5 Block Diagram Figure 15-3 shows the transmitter portion of the SCI.
Figure 15-4 shows the receiver portion of the SCI.
15.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the memory chapter of this document or the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.2.
Table 15-2. SCIxBDL Field Descriptions Field Description 7–0 SBR[7:0] Baud Rate Modulo Divisor. These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply current. When BR is 1 – 8191, the SCI baud rate equals BUSCLK/(16×BR). See also BR bits in Table 15-1. 15.2.
Table 15-3. SCIxC1 Field Descriptions (continued) Field Description 1 PE Parity Enable. Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 PT Parity Type. Provided parity is enabled (PE = 1), this bit selects even or odd parity.
Table 15-4. SCIxC2 Field Descriptions (continued) Field 2 RE Description Receiver Enable. When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS is set the RxD pin reverts to being a general-purpose I/O pin even if RE is set. 0 Receiver off. 1 Receiver on. 1 RWU Receiver Wakeup Control. This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition.
Table 15-5. SCIxS1 Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag. RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF set and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. 4 IDLE Idle Line Flag. IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity.
15.2.5 SCI Status Register 2 (SCIxS2) This register contains one read-only status flag. 7 6 5 LBKDIF RXEDGIF 0 0 R 4 3 2 1 RXINV RWUID BRK13 LBKDE 0 0 0 0 0 0 RAF W Reset 0 0 Figure 15-10. SCI Status Register 2 (SCIxS2) Table 15-6. SCIxS2 Field Descriptions Field Description 7 LBKDIF LIN Break Detect Interrupt Flag. LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a 1 to it.
framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol. 15.2.6 SCI Control Register 3 (SCIxC3) 7 R 6 5 4 3 2 1 0 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0 0 0 0 0 0 0 R8 W Reset 0 Figure 15-11. SCI Control Register 3 (SCIxC3) Table 15-7. SCIxC3 Field Descriptions Field 1 Description 7 R8 Ninth Data Bit for Receiver.
15.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 15-12. SCI Data Register (SCIxD) 15.
15.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure 15-3. The transmitter output (TxD) idle state defaults to logic high (TXINV is cleared following reset). The transmitter output is inverted by setting TXINV. The transmitter is enabled by setting the TE bit in SCIxC2.
Table 15-8. Break Character Length 15.3.3 BRK13 M Break Character Length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times Receiver Functional Description In this section, the receiver block diagram (Figure 15-4) is a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained.
level for that bit, the noise flag (NF) is set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame.
15.3.3.2.2 Address-Mark Wakeup When wake is set, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit when M is cleared and ninth bit when M is set). Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag is set instead of the data along with any associated NF, FE, or PF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by writing a 1 to it. This function does depend on the receiver being enabled (RE = 1). 15.3.
internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 15.3.5.4 Single-Wire Operation When LOOPS is set, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode implements a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a general-purpose port I/O pin.
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Chapter 16 Serial Peripheral Interface (S08SPIV3) 16.1 Introduction Figure 16-1 shows the MCF51QE128 Series block diagram with the SPI highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MCF51QE128 device does not support it. 16.1.1 SPI Clock Gating The bus clock to SPI1 and SPI2 can be gated on and off using the SPI1 and SPI2 bits, respectively, in SCGC2. These bits are set after any reset, which enables the bus clock to this module.
Chapter 16 Serial Peripheral Interface (S08SPIV3) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REA
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16.1.3 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable msb-first or lsb-first shifting 16.1.
Figure 16-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 16.1.4.2 SPI Module Block Diagram Figure 16-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Pin Control M SPE MOSI (MOMI) S Tx Buffer (Write SPIxD) Enable SPI System M Shift Out SPI Shift Register Shift In MISO (SISO) S SPC0 Rx Buffer (Read SPIxD) BIDIRO Shift Direction LSBFE Shift Clock Rx Buffer Full Tx Buffer Empty Master Clock SPIxBR Bus Rate Clock Clock Generator MSTR Clock Logic Slave Clock Master/Slave M SPSCK S Master/ Slave Mode Select MODFEN SSOE Mode Fault Detection SS SPRF SPTEF SPTIE MODF SPIE SPI Interrupt Request Figure 16-3.
Bus Clock Prescaler Clock Rate Divider Divide By 1, 2, 3, 4, 5, 6, 7, or 8 Divide By 2, 4, 8, 16, 32, 64, 128, or 256 SPIxBR[SPPR] SPIxBR[SPR] Master SPI Bit Rate Figure 16-4. SPI Baud Rate Generation 16.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPIxC1[SPE] is cleared), these four pins revert to being general-purpose port I/O pins that are not controlled by the SPI. 16.
output enable bit determines whether this pin acts as the mode fault input (SPIxC1[SSOE] = 0) or as the slave select output (SSOE = 1). 16.3 Modes of Operation 16.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During stop2 mode, the SPI module is fully powered down. Upon wake-up from stop2 mode, the SPI module is in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Table 16-1. SPIxC1 Field Descriptions (continued) Field Description 5 SPTIE SPI Transmit Interrupt Enable. This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity.
R 7 6 5 0 0 0 4 3 MODFEN BIDIROE 0 0 2 1 0 SPISWAI SPC0 0 0 0 W Reset 0 0 0 0 Figure 16-6. SPI Control Register 2 (SPIxC2) Table 16-3. SPIxC2 Register Field Descriptions Field 7–5 Description Reserved, should be cleared. 4 MODFEN Master Mode-Fault Function Enable. When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 16-2 for more details).
Table 16-4. SPIxBR Register Field Descriptions Field 7 6–4 SPPR Description Reserved, should be cleared. SPI Baud Rate Prescale Divisor. This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as shown below. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Figure 16-4). SPPR Prescaler Divisor 3 2–0 SPR 16.4.
Table 16-5. SPIxS Register Field Descriptions Field Description 5 SPTEF SPI Transmit Buffer Empty Flag. This bit is set when there is room in the transmit data buffer. It is cleared by reading SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxD. SPIxS must be read with SPTEF set before writing data to SPIxD or the SPIxD write is ignored. SPTEF generates a CPU interrupt request if SPIxC1[SPTIE] is also set.
indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts. During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the master’s shift register.
Bit Time # (REFERENCE) 1 2 ... 6 7 8 BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) msb FIRST lsb FIRST MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 16-10. SPI Clock Formats (CPHA = 1) When CPHA is set, the slave begins to drive its MISO output when SS asserts, but the data is not defined until the first SPSCK edge.
BIT TIME # (REFERENCE) 1 2 BIT 7 BIT 0 BIT 6 BIT 1 ... 6 7 8 BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) msb FIRST lsb FIRST ... ... MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 16-11. SPI Clock Formats (CPHA = 0) When CPHA is cleared, the slave begins to drive its MISO output with the first data bit value (msb or lsb depending on LSBFE) when SS asserts.
16.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) sets when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is configured as the mode fault input signal when MSTR and MODFEN is set, and SSOE is clear. The mode fault detection feature is used in a system where more than one SPI device might become a master at the same time.
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Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) 17.1 Introduction Figure 17-1 shows the MCF51QE128 Series block diagram with the TPM highlighted. 17.1.1 ACMP/TPM Configuration Information The ACMP modules can be configured to connect the output of the analog comparator to a TPM input capture channel 0 by setting the corresponding SOPT2[ACICx] bit. With ACICx set, the TPMxCH0 pin is not available externally regardless of the configuration of the TPMx module.
Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 96K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REA
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Timer/PWM Module (S08TPMV3) 17.1.
Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. You may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
Timer/PWM Module (S08TPMV3) Bus Clock Clock Source Select Fixed System Clock SYNC External Clock Prescale and Select OFF, Bus, Fixed System Clock, Ext ÷1, 2, 4, 8, 16, 32, 64, or 128 CLKSB:CLKSA PS[2:0] CPWMS 16-Bit Counter TOF Counter Reset TOIE Interrupt Logic 16-Bit Comparator TPMxMODH:TPMxMODL Channel 0 ELS0B ELS0A Port Logic TPMxCH0 16-Bit Comparator TPMxC0VH:TPMxC0VL CH0F Interrupt Logic 16-Bit Latch Internal Bus Channel 1 MS0B MS0A ELS1B ELS1A CH0IE Port Logic TPMxCH1
Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
Timer/PWM Module (S08TPMV3) 17.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow you to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock that drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM. The bus clock clocks the synchronizer.
Timer/PWM Module (S08TPMV3) pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... 2 ... TPMxCHn CHnF Bit TOF Bit Figure 17-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ...
Timer/PWM Module (S08TPMV3) TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... TPMxCHn CHnF Bit TOF Bit Figure 17-6. Low-True Pulse of a Center-Aligned PWM 17.3 Register Definition This section consists of register descriptions in address order. 17.3.
Timer/PWM Module (S08TPMV3) Table 17-2. TPMxSC Field Descriptions (continued) Field Description 5 CPWMS Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
Timer/PWM Module (S08TPMV3) little-endian order that makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write.
Timer/PWM Module (S08TPMV3) The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC) so the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active.
Timer/PWM Module (S08TPMV3) Table 17-5. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
Timer/PWM Module (S08TPMV3) Table 17-6. Mode, Edge, and Level Selection (continued) CPWMS MSnB:MSnA ELSnB:ELSnA Mode 10 1 Center-aligned PWM XX X1 17.3.5 Configuration High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions.
Timer/PWM Module (S08TPMV3) • If CLKSB and CLKSA are not cleared and in EPWM or CPWM modes, the registers are updated after the both bytes were written, and the TPM counter changes from TPMxMODH:TPMxMODL − 1 to TPMxMODH:TPMxMODL. If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not).
Timer/PWM Module (S08TPMV3) Table 17-7. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock used for all internal MCU activities including operation of the CPU and buses.
Timer/PWM Module (S08TPMV3) 17.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If CLKSB:CLKSA are cleared, the registers are updated when the second byte is written • If CLKSB:CLKSA are not cleared, the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written.
Timer/PWM Module (S08TPMV3) • If CLKSB and CLKSA are not cleared, the registers are updated after both bytes are written, and the TPM counter changes from TPMxMODH:TPMxMODL − 1 to TPMxMODH:TPMxMODL. If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 17.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1).
Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS is set. Because the TPM is connected to an 8-bit peripheral bus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths.
Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 17-8, showing the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 17-8.
Timer/PWM Module (S08TPMV3) 17.6.2.1.2 Center-Aligned PWM Case When CPWMS is set, TOF is set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case, TOF corresponds to the end of a PWM period. 17.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 17.6.2.2.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.1 Introduction This chapter describes the capabilities defined by the Version 1 ColdFire debug architecture. The Version 1 ColdFire core supports BDM functionality using the HCS08’s single-pin interface. The traditional 3-pin full-duplex ColdFire BDM serial communication protocol based on 17-bit data packets is replaced with the HCS08 protocol where all communications are based on an 8-bit data packet using a single package pin (BKGD).
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Version 1 ColdFire Core (CF1Core) Central Processing Unit (CF1Cpu) addr IFP RESET IPL_B[2:0] OEP rdata wdata Debug (CF1Dbg) PST/ DDATA BDC BKGD CFx BDM RTD IFP OEP BDC CFxBDM PST/DDATA RTD — Instruction fetch pipeline — Operand execution pipeline — Background debug controller — ColdFire background debug module — Processor status/debug data — Real-time debug Figure 18-1. Simplified Version 1 ColdFire Core Block Diagram 18.1.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) • concurrent operation of the processor and BDM-initiated memory commands. In addition, the option is provided to allow interrupts to occur. See Section 18.4.2, “Real-Time Debug Support”. Program trace support—The ability to determine the dynamic execution path through an application is fundamental for debugging.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) When operating in secure mode, as defined by a 2-bit field in the flash memory examined at reset, BDM access to debug resources is extremely restricted. It is possible to tell that the device has been secured, and to clear security, which involves mass erasing the on-chip flash memory. No other debug access is allowed. Secure mode can be used in conjunction with each of the wait and stop low-power modes.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) CPU clock/2 is used as the BDM clock (POR or BDFR=1) with BKGD=0 or BDFR and BFHBR= 1 Debug Halt ENBDM=1 CLKSW=1 Return to Halt via BACKGROUND command, HALT instruction, or BDM GO BDM breakpoint trigger command Normal Operation ENBDM=1 Any State POR with BKGD=1 or BDFR, BFHBR, and BKGD=1 or BDFR=1 and BFHBR=0 or any other reset clear ENBDM via BDM CLKSW=0 Debug not enabled BDM & CPU clocks are not enabled in STOP modes Debug is enabled CPU clocks co
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.3 Memory Map/Register Definition In addition to the BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains a number of registers. Most of these registers (all except the PST/DDATA trace buffer) are also accessible (write-only) from the processor’s supervisor programming model by executing the WDEBUG instruction.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-4. Debug Module Memory Map (continued) DRc Register Name Width (bits) Access Reset Value Section/ Page 0x18 PC breakpoint register 1 (PBR1) 32 W PBR1[0] = 0 18.3.8/18-376 0x1A PC breakpoint register 2 (PBR2) 32 W PBR2[0] = 0 18.3.8/18-376 0x1B PC breakpoint register 3 (PBR3) 32 W PBR3[0] = 0 18.3.8/18-376 32 R (BDM)3 Undefined, Unaffected 18.4.3.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc[4:0]: 0x00 (CSR) 31 R 30 Access: Supervisor write-only BDM read/write 29 28 BSTAT 27 FOF 26 25 24 23 22 TRG HALT BKPT 21 20 HRL 19 0 W Reset R 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 W Reset 0 TRC 0 0 0 DDC 0 UHE 0 0 0 0 1 7 6 5 4 0 BTB 0 1 0 0 NPL IPI SSM 0 0 0 0 18 BKD 17 0 16 IPW 0 0 0 1 0 FID DDH 0 0 3 2 0 0 0 0 Figure 18-3.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-5. CSR Field Descriptions (continued) Field 18 BKD 17 16 IPW 15 14 TRC 13 12–11 DDC Description Breakpoint disable. Disables the normal BKPT input signal and BACKGROUND command functionality, and allows the assertion of this pin (or execution of the BACKGROUND command) to generate a debug interrupt.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-5. CSR Field Descriptions (continued) Field 5 IPI Description Ignore pending interrupts when in single-step mode. 0 Core services any pending interrupt requests signalled while in single-step mode. 1 Core ignores any pending interrupt requests signalled while in single-step mode. 4 SSM Single-step mode enable. 0 Normal mode. 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x01 (XCSR) 31 30 Access: Supervisor write-only BDM read/write 29 28 27 R CPU CPU HALT STOP CSTAT W ESEQC Reset R 26 25 CLKSW SEC 24 ENBDM 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 ERASE 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset APCSC 0 0 APCE NB 0 Figure 18-4.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-7. XCSR Field Descriptions (continued) Field Description 29–27 During reads, indicates the BDM command status. CSTAT (R) 000 Command done, no errors ESEQC (W) 001 Command done, data invalid 01x Command done, illegal 1xx Command busy, overrun If an overrun is detected (CSTAT = 1xx), the following sequence is suggested to clear the source of the error: 1. Issue a SYNC command to reset the BDC channel. 2. The host issues a BDM NOP command. 3.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-7. XCSR Field Descriptions (continued) Field Description 2–1 APCSC Automatic PC synchronization control. Determines the periodic interval of PC address captures, if XCSR[APCENB] is set. When the selected interval is reached, a SYNC_PC command is sent to the ColdFire CPU. For more information on the SYNC_PC operation, see the APCENB description.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-8. CSR2 Reference Summary (continued) Method Reference Details WRITE_DREG Writes CSR2[31–0] from the BDM interface. Classified as a non-intrusive BDM command. WDEBUG Instruction Writes CSR2[23–0] during the core’s execution of WDEBUG instruction. This instruction is a privileged supervisor-mode instruction.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-9. CSR2 Field Descriptions (continued) Field 22–21 PSTBST 20 Description PST trace buffer state. Indicates the current state of the PST trace buffer recording. 00 PSTB disabled 01 PSTB enabled and waiting for the start condition 10 PSTB enabled, recording and waiting for the stop condition 11 PSTB enabled, completed recording after the stop condition was reached Reserved, must be cleared. 19–16 D1HRL Debug 1-pin hardware revision level.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-9. CSR2 Field Descriptions (continued) Field Description 4–3 PSTBRM PST trace buffer recording mode. Defines the trace buffer recording mode. The start and stop recording conditions are defined by the PSTBSS field. 00 Normal recording mode 01 Continuous, normal recordingReserved 10 PC profile recordingReserved 11 Continuous PC profile recordingReserved 2–0 PSTBSS PST trace buffer start/stop definition.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x03 (CSR3) R 31 30 0 BFC DIV8 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R Access: Supervisor write-only BDM read/write 29 28 27 26 25 24 BFCDIV 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 18-6. Configuration/Status Register 3 (CSR3) Table 18-11.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x05 (BAAR) Access: Supervisor write-only BDM write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R SZ TT TM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 18-7. BDM Address Attribute Register (BAAR) Table 18-12.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-13. AATR Field Descriptions (continued) Field Description 14–13 SZM Size mask. Masks the corresponding SZ bit in address comparisons. 12–11 TTM Transfer type mask. Masks the corresponding TT bit in address comparisons. 10–8 TMM Transfer modifier mask. Masks the corresponding TM bit in address comparisons. 7 R Read/write. R is compared with the R/W signal of the processor’s local bus. 6–5 SZ Size.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x07 (TDR) Access: Supervisor write-only BDM write-only Second Level Trigger 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W Reset TRC 0 L2EBL 0 0 L2ED 0 0 0 0 L2DI 0 0 0 L2EA L2EPC L2PCI 0 0 0 0 0 0 5 4 3 2 1 0 First Level Trigger 15 14 13 12 11 10 0 0 0 9 8 7 6 0 0 0 R W L2T Reset 0 L1T L1EBL 0 0 L1ED 0 L1DI 0 L1EA 0 0 L1EPC L1PCI 0 0 0 Figure 18-9.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-14. TDR Field Descriptions (continued) Field Description 20–18 L2EA Enable level 2 address breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all three bits disables the breakpoint. TDR Bit Description 20 Address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR. 19 Address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-14. TDR Field Descriptions (continued) Field Description 5 L1DI Level 1 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. 4–2 L1EA Enable level 1 address breakpoint. Setting an L1EA bit enables the corresponding address breakpoint.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x08 (PBR0) Access: Supervisor write-only BDM write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 18-10. Program Counter Breakpoint Register 0 (PBR0) Table 18-15. PBR0 Field Descriptions Field Description 31–0 PC breakpoint address. The address to be compared with the PC as a breakpoint trigger.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-17. PBMR Field Descriptions Field Description 31–0 Mask PC breakpoint mask. 0 The corresponding PBR0 bit is compared to the appropriate PC bit. 1 The corresponding PBR0 bit is ignored. 18.3.9 Address Breakpoint Registers (ABLR, ABHR) The ABLR and ABHR define regions in the processor’s data address space that can be used as part of the trigger.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-19. ABHR Field Description Field Description 31–0 High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address 18.3.10 Data Breakpoint and Mask Registers (DBR, DBMR) DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-22. Access Size and Operand Data Location Address[1–0] Access Size Operand Location 00 Byte D[31–24] 01 Byte D[23–16] 10 Byte D[15–8] 11 Byte D[7–0] 0x Word D[31–16] 1x Word D[15–0] xx Longword D[31–0] 18.3.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) The BDC provides a single-wire debug interface to the target MCU. As shown in the Version 1 ColdFire core block diagram of Figure 18-1, the BDC module interfaces between the single-pin (BKGD) interface and the remaining debug modules, including the ColdFire background debug logic, the real-time debug hardware, and the PST/DDATA trace logic. This interface provides a convenient means for programming the on-chip flash and other non-volatile memories.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-23. CPU Halt Sources (continued) Halt Source Halt Timing Description Hardware breakpoint trigger Pending Halt is made pending in the processor. The processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-23. CPU Halt Sources (continued) Halt Source BKGD held low for ≥2 bus clocks after reset negated for POR or BDM reset Halt Timing Description Flash unsecure Enters debug mode with XCSR[ENBDM, CLKSW] set. The full set of BDM commands is available and debug can proceed. If the core is reset into a debug halt condition, the processor’s response to the GO command depends on the BDM command(s) performed while it was halted.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) When a development system is connected, it can pull BKGD and RESET low, release RESET to select active background (halt) mode rather than normal operating mode, and then release BKGD. It is not necessary to reset the target MCU to communicate with it through the background debug interface. There is also a mechanism to generate a reset event in response to setting CSR2[BDFR]. 18.4.1.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 18-16. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 18-17 shows the host receiving a logic 0 from the target MCU.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE SPEEDUP PULSE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 18-17. BDM Target-to-Host Serial Bit Timing (Logic 0) 18.4.1.4 BDM Command Set Descriptions This section presents detailed descriptions of the BDM commands.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Miscellaneous Commands W 7 6 5 4 0 0 R/W 0 3 2 1 0 1 0 MSCMD Optional Command Extension Byte (Data) R/W Memory Commands W 7 6 5 4 0 0 R/W 1 W if addr, R/W if data 3 2 SZ MCMD Command Extension Bytes (Address, Data) Core Register Commands 7 W 6 5 CRG 4 3 R/W R/W 2 1 0 1 0 CRN Command Extension Bytes (Data) PST Trace Buffer Read Commands W 7 6 5 4 0 1 0 1 3 R Trace Buffer Data[31–24] R Trace Buffer
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-24. BDM Command Code Field Descriptions Field 5 R/W Description Read/Write. 0 Command is performing a write operation. 1 Command is performing a read operation. 3–0 Miscellaneous command. Defines the miscellaneous command to be performed.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5 BDM Command Set Summary Table 18-25 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. The nomenclature below is used in Table 18-25 to describe the structure of the BDM commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / d ad24 rd8 rd16 rd32 rd.sz wd8 wd16 wd32 wd.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-25. BDM Command Summary (continued) Command Mnemonic Command ACK Classification if Enb?1 Command Structure Description DUMP_MEM.sz_WS Non-Intrusive No (0x33+4 x sz)/d/ss/rd.sz Dump (read) memory based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large blocks of memory. An initial READ_MEM{_WS} is executed to set up the starting address of the block and to retrieve the first result.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-25. BDM Command Summary (continued) Command Mnemonic Command ACK Classification if Enb?1 SYNC_PC Command Structure Description Non-Intrusive Yes 0x01/d WRITE_CREG Active Background Yes (0xC0+CRN)/wd32/d Write one of the CPU’s control registers WRITE_DREG Non-Intrusive Yes (0x80+CRN)/wd32/d Write one of the debug module’s control registers WRITE_MEM.sz Non-Intrusive Yes (0x10+4 x sz)/ad24/wd.sz/d WRITE_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 2. 3. 4. 5. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. Drives BKGD low for 128 BDC clock cycles. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5.4 BACKGROUND Enter active background mode (if enabled) Non-intrusive 0x04 host → target D L Y Provided XCSR[ENBDM] is set (BDM enabled), the BACKGROUND command causes the target MCU to enter active background (halt) mode as soon as the current CPU instruction finishes. If ENBDM is cleared (its default value), the BACKGROUND command is ignored.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) DUMP_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 0x12 Memory data[7-0] host → target host → target 0x16 Memory data[15-8] Memory data[7-0] host → target host → target host → target 0x1A Memory data[31-24] Memory data[23-16] Memory data[15-8] Memory data[7-0] host → target host → target host → target host → target host → target D L Y D L Y D L Y FILL_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) NOTE FILL_MEM_{WS} does not check for a valid address; it is a valid command only when preceded by NOP, WRITE_MEM_{WS}, or another FILL_MEM{_WS} command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field (sz) is examined each time a FILL_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the FILL_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) If the processor is halted, this command reads the selected control register and returns the 32-bit result. This register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor control registers are always 32-bits wide, regardless of implemented register width. The register is addressed through the core register number (CRN). See Table 18-24 for the CRN details when CRG is 11.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) READ_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5.13 READ_Rn Read general-purpose CPU register 0x60+CRN host → target D L Y Active Background Rn data [31–24] Rn data [23–16] Rn data [15–8] Rn data [7–0] target → host target → host target → host target → host If the processor is halted, this command reads the selected CPU general-purpose register (An, Dn) and returns the 32-bit result. See Table 18-24 for the CRN details when CRG is 01.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5.17 SYNC_PC Synchronize PC to PST/DDATA Signals Non-intrusive 0x01 host → target D L Y Capture the processor’s current PC (program counter) and display it on the PST/DDATA signals. After the debug module receives the command, it sends a signal to the ColdFire core that the current PC must be displayed. The core responds by forcing an instruction fetch to the next PC with the address being captured by the DDATA logic.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5.19 WRITE_DREG Write debug control register Non-intrusive 0x80+CRN DREG data [31–24] DREG data [23–16] DREG data [15–8] DREG data [7–0] host → target host → target host → target host → target host → target D L Y This command writes the 32-bit operand to the selected debug control register. This grouping includes all the debug control registers ({X}CSRn, BAAR, AATR, TDR, PBRn, PBMR, ABxR, DBR, DBMR).
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) WRITE_MEM.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.1.5.22 WRITE_XCSR_BYTE Write XCSR Status Byte 0x0D XCSR Data [31–24] host → target host → target Always Available Write the special status byte of XCSR (XCSR[31–24]). This command can be executed in any mode. 18.4.1.5.23 WRITE_CSR2_BYTE Write CSR2 Status Byte 0x0E CSR2 Data [31–24] host → target host → target Always Available Write the most significant byte of CSR2 (CSR2[31–24]). This command can be executed in any mode. 18.4.1.5.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th BDC clock cycle of the last bit. This minimum delay assures enough time for the host to recognize the ACK pulse. Note that there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends on the CPU bus frequency, which in some cases could be very slow compared to the serial communication rate.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the data-read portion of the command. TARGET BKGD PIN READ_MEM.B BYTE IS RETRIEVED ADDRESS[23–0] HOST HOST TARGET NEW BDC COMMAND HOST TARGET BDC ISSUES THE ACK PULSE (NOT TO SCALE) DEBUG DECODES THE COMMAND CPU EXECUTES THE READ_MEM.B COMMAND Figure 18-20.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) any of the stop modes. If the host aborts a command by sending the sync pulse, it should then read XCSR[CSTAT] after the sync response is issued by the target, checking for CSTAT cleared, before attempting to send any new command that requires CPU execution. This prevents the new command from being discarded at the debug/CPU interface, due to the pending command being executed by the CPU. Any new command should be issued only after XCSR[CSTAT] is cleared.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) READ_MEM.B CMD IS ABORTED BY THE SYNC REQUEST (NOT TO SCALE) BKGD PIN READ_MEM.B ADDRESS[23-0] HOST SYNC RESPONSE FROM THE TARGET (NOT TO SCALE) READ_XCSR_BYTE TARGET HOST TARGET NEW BDC COMMAND HOST TARGET NEW BDC COMMAND BDC DECODES AND CPU TRYS TO EXECUTE THE READ_MEM.B CMD Figure 18-21. ACK Abort Procedure at the Command Level Figure 18-22 a shows a conflict between the ACK pulse and the sync request pulse.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) • ACK_DISABLE — Disables the ACK pulse protocol. In this case, the host should verify the state of XCSR[CSTAT] in order to evaluate if there are pending commands and to check if the CPU’s operating state has changed to or from active background mode via XCSR[31–30]. The default state of the protocol, after reset, is hardware handshake protocol disabled.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) For the V1 ColdFire core and its single debug signal, support for trace functionality is completely redefined. The V1 solution provides an on-chip PST/DDATA trace buffer (known as the PSTB) to record the stream of PST and DDATA values. Even with the application of a PST trace buffer, problems associated with the PST bandwidth and associated fill rate of the buffer remain.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-26. Processor Status Encodings (continued) PST[4:0] Definition 0x08–0x0B Indicates the number of data bytes to be displayed as DDATA on subsequent processor clock cycles. This marker value is driven as the PST one processor clock cycle before the data is displayed on DDATA. The capturing of peripheral bus data references is controlled by CSR[DDC].
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) loaded, which is indicated by the PST marker value immediately preceding the DDATA entry in the PSTB that begins the address entries. Multiple byte DDATA values are displayed in least-to-most-significant order.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.4.3.2 PST Trace Buffer (PSTB) As PST and DDATA values are captured and loaded in the trace buffer, each entry is 6 bits in size so the type of the entry can easily be determined when post-processing the PSTB. See Figure 18-24. 5 4 3 2 1 0 — — PSTB[PST] 0 PST[4:0] Data PSTB[DDATA] 1 R/W Data[3:0] Address PSTB[DDATA] 1 0 Address[3:0] Reset: — — — — Figure 18-24. V1 PST/DDATA Trace Buffer Entry Format 18.4.3.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) # pst = 1c, 1c, 05, 0d # ddata = 2a, 23, 28, 20 # trg_addr = 083a << 1 # trg_addr = 1074 01074: 01078: 0107a: 0107c: 01080: 01082: 01088: 0108e: 01092: 46fc 2f08 2f00 302f e488 0280 207c 52b0 11c0 _isr: mov.w mov.l mov.l 0008 mov.w lsr.l 0000 00ff andi.l 0080 1400 mov.l 0c00 addq.l a021 mov.b 2700 &0x2700,%sr %a0,-(%sp) %d0,-(%sp) (8,%sp),%d0 &2,%d0 &0xff,%d0 &int_count,%a0 &1,(0,%a0,%d0.l*4) %d0,IGCR0+1.w 01096: 1038 a020 mov.b IGCR0.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) where the {...} definition is optional operand information defined by the setting of the CSR. The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST value {0x08, 0x09, or 0x0B} identifies the size and presence of valid data to follow in the PST trace buffer (PSTB) {1, 2, or 4 bytes}.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA btst.{b,l} Dy,x PST = 0x01, {PST = 0x08, DD = source operand} byterev.l Dx PST = 0x01 clr.b x PST = 0x01, {PST = 0x08, DD = destination operand} clr.l x PST = 0x01, {PST = 0x0B, DD = destination operand} clr.w x PST = 0x01, {PST = 0x09, DD = destination operand} cmp.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA movea.w y,Ax PST = 0x01, {PST = 0x09, DD = source} movem.l #list,x PST = 0x01, {PST = 0x0B, DD = destination},... movem.l y,#list PST = 0x01, {PST = 0x0B, DD = source},... moveq.l #,Dx PST = 0x01 muls.l y,Dx PST = 0x01, {PST = 0x0B, DD = source operand} muls.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax tpf PST/DDATA PST = 0x01 tpf.l # PST = 0x01 tpf.w # PST = 0x01 trap # PST = 0x011 tst.b x PST = 0x01, {PST = 0x08, DD = source operand} tst.l y PST = 0x01, {PST = 0x0B, DD = source operand} tst.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Table 18-28. PST/DDATA Specification for Supervisor-Mode Instructions Instruction Operand Syntax halt PST/DDATA PST = 0x01, PST = 0x0F move.l Ay,USP PST = 0x01 move.l USP,Ax PST = 0x01 move.w SR,Dx PST = 0x01 move.w {Dy,#},SR PST = 0x01, {PST = 0x03} movec.l Ry,Rc PST = 0x01 rte PST = 0x07, {PST = 0x0B, DD = source operand}, {PST = 0x03}, {PST = 0x0B, DD = source operand}, PST = 0x05, {[PST = 0x0{DE}], DD = target address} stldsr.
Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) MCF51QE128 MCU Series Reference Manual, Rev. 3 420 Freescale Semiconductor Get the latest version from freescale.
Appendix A Revision History This appendix describes corrections to the MCF51QE128 Reference Manual. For convenience, the corrections are grouped by revision. A.1 Changes between Rev. 2 and Rev. 3 Table 29. MCF51QE128RM Rev. 2 to Rev. 3 Changes Chapter Throughout Device Overview ColdFire Core Analog Comparator Description Formatting, layout, spelling, and grammar corrections. Added information about the MCF51QE32 device. Changed the SRAM size for the MCF51QE64 device (was 4 Kbytes, is 8 Kbytes).
Revision History MCF51QE128 MCU Series Reference Manual, Rev.
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