Integrated Microcontroller Reference Manual

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MCF52211 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52210

MCF52211

MCF52212

MCF52213

Document Number: MCF52211RM

Rev. 2

09/2007

Summary of content (576 pages)

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MCF52211 ColdFire® Integrated Microcontroller Reference Manual Devices Supported: MCF52210 MCF52211 MCF52212 MCF52213 Document Number: MCF52211RM Rev.
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How to Reach Us: Home Page: http://www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.
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Chapter 1 Overview 1.1 1.2 1.3 1.2 MCF52211 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Part Numbers and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.14 2.15 2.16 2.17 Pulse-Width Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.2 5.3 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.
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Chapter 8 Power Management 8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2.
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10.6.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Chapter 11 Real-Time Clock 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . .
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13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.5 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.5.1 Ports Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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15.5 OTG and Host Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7 On-The-Go Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.1 OTG Dual Role A Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.
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18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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21.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5.1 GPT[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.5.2 GPT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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22.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.2.
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24.2 24.3 24.4 24.5 24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . .
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25.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.4.
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Chapter 27 Pulse-Width Modulation (PWM) Module 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.2.1 PWM Enable Register (PWME) . . .
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28.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.
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Chapter 1 Overview This chapter provides an overview of the major features and functional components of the MCF52211 family of microcontrollers. The MCF52211 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52210, MCF52212, and MCF52213. The differences between these parts are summarized in Table 1-1. This document is written from the perspective of the MCF52211.
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Overview 1.1 MCF52211 Family Configurations Table 1-1. MCF52211 Family Configurations Module 52210 52211 52212 52213 Version 2 ColdFire Core with MAC (Multiply-Accumulate Unit) • • • • System Clock Performance (Dhrystone 2.
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Overview 1.2 Block Diagram The superset device in the MCF52211 family comes in a 100-lead leaded quad flat package (LQFP). Figure 1-1 shows a top-level block diagram of the MCF52211.
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Overview Table 1-2.
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Overview • • • • • • — Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used (except backup watchdog timer) — Software controlled disable of
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Overview — — — — — • • • • • 12-bit resolution Minimum 1.125 μs conversion time Simultaneous sampling of two channels for motor control applications Single-scan or continuous operation Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit — Unused analog channels can be used as digital I/O Four 32-bit timers with DMA support — 12.
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Overview • • • • • • — Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions Software watchdog timer — 32-bit counter — Low-power mode support Backup watchdog timer (BWT) — Independent timer that can be used to help software recover from runaway code — 16-bit counter — Low-power mode support Clock generation features — One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference options — Trimmed relaxation oscillator — Two to 10 MHz ref
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Overview • • • 1.2.
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Overview real-time tracing capability is provided on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register.
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Overview 1.2.4 1.2.4.1 On-Chip Memories SRAM The dual-ported SRAM module provides a general-purpose 8- or 16-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 8- or 16-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack.
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Overview 1.2.7 UARTs The MCF52211 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions. 1.2.8 I2C Bus The MCF52211 includes two I2C modules. The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices.
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Overview register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers. 1.2.12 General Purpose Timer (GPT) The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare.
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Overview 1.2.17 Backup Watchdog Timer The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock. 1.2.
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Overview 1.2.22 GPIO Nearly all pins on the MCF52211 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Signal Descriptions Chapter 2 Signal Descriptions 2.1 Introduction This chapter describes signals implemented on this device and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used. NOTE The terms assertion and negation are used to avoid confusion when dealing with a mixture of active-low and active-high signals.
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Signal Descriptions Slave Mode Access (CIM_IBO/EzPort) AN QSPI M3 M1 Arbiter M2 M0 TMS TDI TDO TRST TCLK SDAn Interrupt Controller SCLn PADI – Pin Muxing UTXDn BDM PORT UART 0 JTAG TAP UART 2 UART 1 I2C QSPI Watch Dog URXDn URTSn UCTSn PWMn DTINn/DTOUTn GPT TMR 0 JTAG_EN TMR 1 TMR 2 TMR 3 RTC RCON_B I2C ALLPST PST USB On-The-Go DDATA V2 ColdFire CPU 4 CH DMA USB TCVR PMM USBD+ USBDIPS Bus Gasket ADC AN[7:0] CIM_IBO 16 Kbytes SRAM (2K×32)×2 Backup Watchdog TIM VSTBY Edg
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MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 2-1.
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Drive Slew Rate / Pull-up / Strength / 1 2 Control Pull-down Control1 Freescale Semiconductor MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 2-1.
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Freescale Semiconductor MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Signal Descriptions 2.4 Reset Signals Table 2-2 describes signals that are used to reset the chip or as a reset indication. Table 2-2. Reset Signals 2.5 Signal Name Abbreviation Function I/O Reset In RSTI Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals. I Reset Out RSTO Driven low for 512 CPU clocks after the reset source has deasserted and PLL locked.
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Signal Descriptions Table 2-5. Clocking Modes 2.
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Signal Descriptions I2C I/O Signals 2.9 Table 2-8 describes the I2C serial interface module signals. Table 2-8. I2C I/O Signals 2.10 Signal Name Abbreviation Function I/O Serial Clock SCLn Open-drain clock signal for the for the I2C interface. It is driven by the I2C module when the bus is in master mode or it becomes the clock input when the I2C is in slave mode. I/O Serial Data SDAn Open-drain signal that serves as the data input/output for the I2C interface.
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Signal Descriptions 2.12 ADC Signals Table 2-11 describes the signals of the analog-to-digital converter. Table 2-11. ADC Signals Signal Name Abbreviation Analog Inputs AN[7:0] Analog Reference VRH Function Inputs to the ADC. I Reference voltage high and low inputs. I VRL Analog Supply I/O I Isolate the ADC circuitry from power supply noise VDDA — — VSSA 2.13 General Purpose Timer Signals Table 2-12 describes the general purpose timer signals. Table 2-12.
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Signal Descriptions Table 2-14. Debug Support Signals (continued) Signal Name Abbreviation Function I/O Test Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK. I Test Data Output TDO Serial output for test instructions and data. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK. O Development Serial Clock DSCLK Development Serial Clock.
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Signal Descriptions 2.16 EzPort Signal Descriptions Table 2-15 contains a list of EzPort external signals Table 2-15. EzPort Signal Descriptions Signal Name Abbreviation Function I/O EzPort Clock EZPCK Shift clock for EzPort transfers I EzPort Chip Select EZPCS Chip select for signaling the start and end of serial transfers I EzPort Serial Data In EZPD EZPD is sampled on the rising edge of EZPCK I EzPort Serial Data Out EZPQ EZPQ transitions on the falling edge of EZPCK O 2.
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Signal Descriptions MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 3 ColdFire Core 3.1 Introduction This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual. 3.1.1 Overview As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.
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ColdFire Core instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
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ColdFire Core The supervisor-programming model is intended to be used only by system control software to implement restricted operating system functions, I/O control, and memory management.
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ColdFire Core Table 3-1. ColdFire Core Programming Model (continued) 1 BDM1 Register Width (bits) Access Reset Value 0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Written with Section/Page MOVEC Yes 3.2.8/3-8 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 28, “Debug Module”. 3.2.
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ColdFire Core hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following: if SR[S] = 1 then A7 = Supervisor Stack Pointer else A7 = User Stack Pointer OTHER_A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Pointer The BDM programming model supports direct reads and writes to A7 and OTHER_A7.
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ColdFire Core BDM: LSB of Status Register (SR) R Access: User read/write BDM read/write 7 6 5 0 0 0 4 3 2 1 0 X N Z V C — — — — — W Reset: 0 0 0 Figure 3-5. Condition Code Register (CCR) Table 3-2. CCR Field Descriptions Field 7–5 Description Reserved, must be cleared. 4 X Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified result. 3 N Negative condition code bit.
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ColdFire Core not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary. BDM: 0x801 (VBR) Access: Supervisor read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address W 8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-7. Vector Base Register (VBR) 3.2.
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ColdFire Core Table 3-3. SR Field Descriptions (continued) Field Description 10–8 I Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to current level, except edge-sensitive level 7 requests, which cannot be masked. 7–0 CCR Refer to Section 3.2.4, “Condition Code Register (CCR)”. 3.2.
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ColdFire Core DSOC AGEX RGF Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
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ColdFire Core For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle.
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ColdFire Core Operand Execution Pipeline DSOC AGEX RGF y Ay Opword Core Bus Address d16 Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 3-12. V2 OEP Embedded-Load Part 1 Operand Execution Pipeline DSOC AGEX Rx RGF new Rx Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 y Core Bus Read Data Figure 3-13.
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ColdFire Core For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time. Operand Execution Pipeline DSOC AGEX Ax RGF Ry x Core Bus Address Opword Extension 1 d16 Core Bus Write Data Extension 2 Core Bus Read Data Figure 3-14. V2 OEP Register-to-Memory The pipeline timing diagrams of Figure 3-15 depict the execution templates for these three classes of instructions.
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ColdFire Core Core clock Register-to-Register OEP.DSOC OC OEP.AGEX next EX Core Bus Embedded-Load OEP.DSOC DS OEP.AGEX OC AG Core Bus next EX op read Register-to-Memory (Store) OEP.DSOC OEP.AGEX DSOC next AGEX op write Core Bus Figure 3-15. V2 OEP Pipeline Execution Templates 3.3.2 Instruction Set Architecture (ISA_A+) The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code.
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ColdFire Core Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details see the ColdFire Family Programmer’s Reference Manual. Table 3-4. Instruction Enhancements over Revision ISA_A Instruction Description BITREV The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old Dn[0], new Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
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ColdFire Core fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next). 4. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 Mbyte boundary.
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ColdFire Core Table 3-5. Exception Vector Assignments (continued) 1 Vector Number(s) Vector Offset (Hex) Stacked Program Counter Assignment 64–255 0x100–0x3FC Next Device-specific interrupts Fault refers to the PC of the instruction that caused the exception. Next refers to the PC of the instruction that follows the instruction that caused the fault. All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
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ColdFire Core Table 3-7.
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ColdFire Core execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction. 3.3.4.2 Address Error Exception Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception. Any attempted use of a word-sized index register (Xn.
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ColdFire Core Table 3-8.
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ColdFire Core 3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step. If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2.
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ColdFire Core 3.3.4.11 TRAP Instruction Exception The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode. 3.3.4.12 Unsupported Instruction Exception If execution of a valid instruction is attempted but the required hardware is not present in the processor, an unsupported instruction exception is generated.
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ColdFire Core ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM to determine the hardware configuration. Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-18.
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ColdFire Core Table 3-9. D0 Hardware Configuration Info Field Description (continued) Field Description 11 MMU MMU present. This bit signals if the optional virtual memory management unit (MMU) is present in processor core. 0 MMU execute engine not present in core. (This is the value used for this device.) 1 MMU execute engine is present in core. 10–8 Reserved. 7–4 ISA ISA revision. This 4-bit field defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
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ColdFire Core Table 3-10. D1 Hardware Configuration Information Field Description Field Description 31–30 CLSZ Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. 29–28 CCAS Configurable cache associativity. 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use 27–24 CCSZ Configurable cache size. Indicates the amount of instruction/data cache.
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ColdFire Core 3.3.5 Instruction Execution Timing This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where: • C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.
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ColdFire Core 3.3.5.2 MOVE Instruction Execution Times Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode. ET with { = (d16,PC)} equals ET with { = (d16,An)} ET with { = (d8,PC,Xi*SF)} equals ET with { = (d8,An,Xi*SF)} The nomenclature xxx.
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ColdFire Core Table 3-13. MOVE Long Execution Times (continued) Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl (d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — — 3.3.5.
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ColdFire Core 3.3.5.4 Standard Two Operand Instruction Execution Times Table 3-15. Two Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx ADD.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ADD.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ADDI.L #imm,Dx 1(0/0) — — — — — — — ADDQ.
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ColdFire Core Table 3-15. Two Operand Instruction Execution Times (continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx REMS.L ,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — REMU.L ,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — SUB.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBI.
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ColdFire Core Table 3-16. Miscellaneous Instruction Execution Times (continued) Effective Address Opcode WDEBUG Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx — 5(2/0) — — 5(2/0) — — — 1 The n is the number of registers moved by the MOVEM opcode. If a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0). 3 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
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ColdFire Core 3.3.5.7 Branch Instruction Execution Times Table 3-18. General Branch Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d16,PC) (d8,An,Xi*SF) (d8,PC,Xi*SF) xxx.wl #xxx BRA — — — — 2(0/1) — — — BSR — — — — 3(0/1) — — — JMP — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) — JSR — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — RTE — — 10(2/0) — — — — — RTS — — 5(1/0) — — — — — Table 3-19.
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ColdFire Core MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 4 Multiply-Accumulate Unit (MAC) 4.1 Introduction This chapter describes the functionality, microarchitecture, and performance of the multiply-accumulate (MAC) unit in the ColdFire family of processors. 4.1.1 Overview The MAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of baseline ColdFire architecture. The MAC provides functionality in three related areas: 1.
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Multiply-Accumulate Unit (MAC) cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond scope of any processor architecture and may require full DSP implementation.
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Multiply-Accumulate Unit (MAC) BDM: 0x804 (MACSR) Access: Supervisor read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 7 6 OMC S/U Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 F/I R/T N Z V C 0 0 0 0 0 0 Figure 4-2. MAC Status Register (MACSR) Table 4-2. MACSR Field Descriptions Field Description 31–8 Reserved, must be cleared.
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Multiply-Accumulate Unit (MAC) Table 4-2. MACSR Field Descriptions (continued) Field Description 1 V Overflow. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand size. After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly loaded. MULS and MULU instructions do not change this value. 0 Carry. This field is always zero. Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits. Table 4-3.
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Multiply-Accumulate Unit (MAC) if extension word, bit [5] = 1, the MASK bit, then if = (An) oa = An & {0xFFFF, MASK} if = (An)+ oa = An An = (An + 4) & {0xFFFF, MASK} if =-(An) oa = (An - 4) & {0xFFFF, MASK} An = (An - 4) & {0xFFFF, MASK} if = (d16,An) oa = (An + se_d16) & {0xFFFF0x, MASK} Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement.
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Multiply-Accumulate Unit (MAC) Table 4-5. ACC Field Descriptions Field 31–0 Accumulator 4.3 Description Store 32-bits of the result of the MAC operation. Functional Description The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations.
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Multiply-Accumulate Unit (MAC) 4.3.1 Fractional Operation Mode This section describes behavior when the fractional mode is used (MACSR[F/I] is set). 4.3.1.1 Rounding When the processor is in fractional mode, there are two operations during which rounding can occur: 1. The 32-bit accumulator is moved into a general purpose register.
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Multiply-Accumulate Unit (MAC) int macsr; } macState; The following assembly language routine shows the proper sequence for a correct MAC state save. This code assumes all Dn and An registers are available for use, and the memory location of the state save is defined by A7. MAC_state_save: move.l clr.l move.l move.l move.l movem.l macsr,d7 ; save the macsr d0 ; zero the register to ...
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Multiply-Accumulate Unit (MAC) Table 4-6. MAC Instruction Summary (continued) Command Mnemonic Description Load MACSR move.l {Ry,#imm},MACSR Writes a value to MACSR Store MACSR move.l MACSR,Rx Write the contents of MACSR to a CPU register Store MACSR to CCR move.l MACSR,CCR Write the contents of MACSR to the CCR Load MAC Mask Reg move.l {Ry,#imm},MASK Writes a value to the MASK register Store MAC Mask Reg move.l MASK,Rx Writes the contents of the MASK to a CPU register 4.3.
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Multiply-Accumulate Unit (MAC) • treated as a sticky flag, meaning after set, it remains set until the accumulator or the MACSR is directly loaded. See Section 4.2.1, “MAC Status Register (MACSR)”. The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. Without this operator, the product is not shifted.
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Multiply-Accumulate Unit (MAC) else result[31:0] = 0x7fff_ffff } /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ if (product[31] ^ product[30]) then {MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then if (product[63] == 1) then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000 else if (MACSR.
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Multiply-Accumulate Unit (MAC) break; case 1: case 3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.V == 0) then { MACSR.
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Multiply-Accumulate Unit (MAC) if (MACSR.OMC == 0 || MACSR.V == 0) then { MACSR.
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Multiply-Accumulate Unit (MAC) then {if (inst == MSAC) then result[31:0] = acc[31:0] - product[31:0] else result[31:0] = acc[31:0] + product[31:0] } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[31:0] = 0x0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[31:0] = 0xffff_ffff } /* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.
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Chapter 5 Static RAM (SRAM) 5.1 Introduction This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. 5.1.1 Overview The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-16K address.
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Static RAM (SRAM) Table 5-1. SRAM Programming Model Rc[11:0]1 Width Access (bits) Register Written Section/Page w/ MOVEC Reset Value Supervisor Access Only Registers 0xC05 1 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 5.2.1/5-2 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 28, “Debug Module.” 5.2.
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Static RAM (SRAM) Table 5-2. RAMBAR Field Descriptions (continued) Field Description 11–10 PRIU PRIL Priority Bit. PRIU determines if DMA or CPU has priority in the upper 16K bank of memory. PRIL determines if DMA or CPU has priority in the lower 16K bank of memory. If a bit is set, the CPU has priority. If a bit is cleared, DMA has priority.
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Static RAM (SRAM) 2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance. 3. After the data loads into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes.
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Chapter 6 Clock Module 6.1 Introduction The clock module allows the device to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly.
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Clock Module next POR. If the relaxation oscillator was already selected as the system clock’s source and is subsequently selected as the timer’s input source, the system and the timer can use the oscillator as the source. 6.3.2 RTC Mode A dedicated RTC oscillator can be selected to run the RTC circuitry. In normal operation, this oscillator is powered by the VDDPLL and VSSPLL pins. When the part is shut down, this oscillator is powered by the VSTBY pin.
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Clock Module In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator can also be disabled during stop mode, but requires a wakeup period to restart.
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Clock Module ADC auto-standby clock EXTERNAL OSCILLATOR 0 ON-CHIP 8 MHz OSCILLATOR 1 Reference Clock 0 0 XTAL Low Power Divider PreDivider 1 EXTAL PLL 1 STOP MODE OSCILLATOR LPD[3:0] XTAL CLKMOD0 CLKMOD1 CCHR CLKSRC System Clock (fsys) ÷2 ColdFire V2 Core PPRMH[11] PPRML[1] BDM CFM Interrupt Controller PPRML[17] PWM PPRMH[9] CLKOUT DMA Timers DISCLK PPRML[16:13] See note below GPT PPRMH[8] QSPI PPRML[10] ADC PPRMH[7] I2C USB_ALT_CLK PPRML[9] PITs PPRMH[4:3] USB_CTRL U
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Clock Module 6.6 Signal Descriptions The clock module signals are summarized in Table 6-2 and a brief description follows. For more detailed information, refer to Chapter 2, “Signal Descriptions.” Table 6-2. Signal Properties Name 6.6.
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Clock Module 6.6.5 RSTO The RSTO pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset control status register (RCR); see Section 10.5.1, “Reset Control Register (RCR).” 6.7 Memory Map and Registers The clock module programming model shown in Table 6-4 consists of registers that define clock operation and status as well as additional peripheral power management registers. Table 6-4.
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Clock Module 6.7.1.1 Synthesizer Control Register (SYNCR) IPSBAR Offset: 0x12_0000 (SYNCR) R W 15 14 13 12 11 10 9 8 LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 0 0 0 1 0 0 0 0 7 6 5 4 3 2 1 0 LOCEN DISCLK FWKUP — — 0 0 0 0 0 Reset R W Access: Supervisor read/write Reset CLKSRC1 PLLMODE 0 1 PLLEN1 0 Figure 6-2.
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Clock Module Table 6-5. SYNCR Field Descriptions (continued) Field Description 14–12 MFD Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one. Note: In external clock mode, the MFD[2:0] bits have no effect.
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Clock Module Table 6-5. SYNCR Field Descriptions (continued) Field Description 5 FWKUP Fast wakeup. Determines when the system clocks are enabled during wakeup from stop mode. 0 System clocks enabled only when PLL is locked or operating normally 1 System clocks enabled on wakeup regardless of PLL lock status Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in stop mode, the PLL wakes up in self-clocked mode or reference clock mode depending on the clock that was lost.
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Clock Module Table 6-6. SYNSR Field Descriptions Field Description 7 EXTOSC Indicates if an external oscillator is providing the reference clock source 0) Reference clock is not external oscillator 1 Reference clock is external oscillator 6 OCOSC Indicates if the on-chip oscillator is providing the reference clock source.
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Clock Module 6.7.1.3 Relaxation Oscillator Control Register (ROCR) The ROCR is used to trim the frequency of the on-chip oscillator. Setting one of the TRIM bits engages its associated bypass capacitance, which increases or decreases the period of the output frequency. The largest capacitance, and thus the biggest frequency step (40%), is associated with TRIM9. The lowest capacitance, and thus the smallest frequency step (0.8%), is associated with TRIM0.
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Clock Module Table 6-8. LPDR Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 LPD Low-Power Divider. This field is used to divide down the system clock by a factor of 2LPD. 6.7.1.5 Clock Control High Register (CCHR) The CCHR sets the pre-division factor, which divides down the PLL input clock by 1 (CCHR[2:0] = 000) to 8 (CCHR[2:0] =111). This allows an external oscillator or crystal of more than 10 MHz to be used with the PLL.
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Clock Module IPSBAR Offset: 0x12_0009 (CCLR) R Access: Supervisor read/write 7 6 5 4 3 2 1 0 — — — — — — OSCSEL1 OSCSEL0 0 0 0 0 0 0 0 See note1 W Reset: Figure 6-7. Clock Control Low Register (CCLR) 1 The OSCSEL reset state is determined during reset configuration. Table 6-10. CCLR Field Descriptions Field 7–1 Description Reserved, should be cleared. 1 OSCSEL1 Oscillator Select 1 bit.
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Clock Module IPSBAR Offset: 0x12_000A (OCHR) 7 6 OCOEN STBY See note1 0 R Access: Supervisor read/write 5 4 3 2 1 0 — — — — — — 0 0 0 0 0 0 W Reset: Figure 6-8. Oscillator Control High Register (OCHR) 1 The OCOEN reset state is determined during reset configuration. Table 6-12. OCHR Field Descriptions Field Description 7 OCOEN 6 STBY 5–0 On-chip Oscillator Enable bit. This bit enables the relaxation oscillator. 0 Relaxation oscillator is disabled.
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Clock Module Table 6-13. OCLR Field Descriptions Field Description 7 OSCEN External Oscillator Enable bit. This bit enables the crystal oscillator in external crystal or external oscillator mode. 0 External oscillator is disabled. 1 External oscillator is enabled. Note: When switching the clock source to the external oscillator, this bit should be set before CCLR[OSCSEL] is cleared. 6 REFS Reference Source bit.
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Clock Module Table 6-14. RTCCR Field Descriptions (continued) Field Description 2 REFS Reference Source bit. This bit configures the RTC oscillator for operation with an external crystal or external oscillator. 0 RTC oscillator is running in external oscillator mode. 1 RTC oscillator is running in external crystal mode. 1 LPEN Low-Power Enable bit. This bit configures the RTC oscillator to run in low-power mode when using an external crystal. 0 RTC oscillator runs in normal-power mode.
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Clock Module Table 6-15. BWCR Field Descriptions (continued) Field Description 1 BWDSTOP This bit determines whether the relaxation oscillator input to the BWT is stopped during Stop mode operation. 0 The relaxation oscillator input to the BWT is stopped when the device enters Stop mode. When the device leaves Stop mode, the relaxation oscillator input to the BWT is restored. 1 The relaxation oscillator input continues to be provided to the BWT when the device enters Stop mode.
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Clock Module In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the electrical specifications. If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes static. Alternately, if SYNCR[LOCEN] is cleared when the PLL fails, the system becomes static.
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Clock Module C2 C1 48 MHz CRYSTAL CONFIGURATION C1 = C2 = 18 pF RF = 1 MΩ R1 = 1 MΩ R1 VSSPLL EXTAL XTAL VSSPLL ON-CHIP RF Figure 6-12. Crystal Oscillator Example 6.8.4.1 Phase and Frequency Detector (PFD) The PFD is a dual-latch phase-frequency detector. It compares the phase and frequency of the reference and feedback clocks. The reference clock comes from the crystal oscillator or an external clock source.
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Clock Module 6.8.4.3 Voltage Control Output (VCO) The voltage across the loop filter controls the frequency of the VCO output. The frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four times the target system frequency. 6.8.4.4 Multiplication Factor Divider (MFD) When the PLL is not in 1:1 PLL mode, the MFD divides the output of the VCO and feeds it back to the PFD.
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Clock Module Start with Tight Lock Criteria Loss of Lock Detected Set Tight Lock Criteria and Notify System of Loss of Lock Condition Reference Count Reference Count ≠ Feedback Count ≠ Feedback Count Count N Reference Cycles and Compare Number of Feedback Cycles Elapsed Count N + K Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = N In Same Count/Compare Sequence Lock Detected.
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Clock Module 6.8.4.8 Loss of Clock Detection The LOCEN bit in the SYNCR enables the loss of clock detection circuit to monitor the input clocks to the phase and frequency detector (PFD). When the reference or feedback clock frequency falls below the minimum frequency, the loss of clock circuit sets the sticky LOCS flag in the SYNSR. NOTE In external clock mode, the loss of clock circuit is disabled. 6.8.4.
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Clock Module 6.8.4.11 Loss of Clock in Stop Mode Table 6-19 shows the resulting actions for a loss of clock in stop mode when the device is being clocked by the various clocking methods. EXT NRM NRM NRM X 0 X 0 X 0 0 0 X 0 0 0 X X X Off Off 0 Off Off 1 Off On 0 — — MODE Out EXT 0 0 Comments 0 Lose reference clock Stuck Lose lock, f.b. clock, reference clock Regain NRM No regain Stuck Lose lock, f.b.
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Clock Module NRM NRM 0 0 0 0 0 0 Off On 1 On On 0 Lose lock MODE Out No lock regain Unstable NRM Lose reference clock or no f.b.
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Clock Module NRM NRM NRM NRM NRM NRM 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 X Off On 0 Off On 1 On On 0 On On 1 On On X Off X X Lose lock, f.b. clock Lose lock, f.b. clock NRM No f.b. clock or lock regain Stuck Lose reference clock SCM 0 Regain f.b. clock Unstable NRM 0–>‘LK 0–>1 ‘LC No f.b. clock regain Stuck Lose reference clock SCM 0 0 1 NRM ‘LK 1 ‘LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f.b.
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Clock Module NRM NRM NRM 1 1 1 1 1 1 0 0 1 On On 0 On On 1 On On X — — — — MODE Out NRM 1 0 0 X X X — 1 RESET — — — Lose lock Stuck — — — Lose lock, regain NRM 0 1 ‘LC — NRM ‘LK 1 ‘LC Lose clock RESET Lose lock Unstable NRM 0 0–>1 ‘LC Lose lock, regain NRM 0 1 ‘LC — NRM ‘LK 1 ‘LC — — — 0 X 1 — REF Lose reference clock Stuck — — — — — 1 0 0 Off X 0 PLL disabled Regain SCM SCM 0 0 1 SCM 1 0 0 Off X 1 PLL disabled
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Clock Module SCM 1 0 0 On On 1 — — Lose reference clock MODE Out SCM 0 0 LOCS PLL Action During Stop LOCK Expected PLL Action at Stop LOCKSS FWKUP OSC PLL LOLRE LOCRE MODE In LOCEN Table 6-19. Stop Mode Operation (continued) Comments 1 SCM Note: PLL = PLL enabled during STOP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = oscillator enabled during STOP mode.
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Clock Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 7 Backup Watchdog Timer (BWT) Module 7.1 Introduction The Backup Watchdog Timer (BWT) module is used to help software recover from runaway code. This section presents the modes of operation, register information, and functional description of the BWT. A block diagram of the BWT is shown in Figure 7-1. IPBUS 16-bit WCNTR BWT Clock Source Divide by 4096 16-bit WSR Count = 0 16-bit Watchdog Counter EN Reset Load Counter WAIT DOZE 16-bit WMR HALTED IPBUS Figure 7-1.
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Backup Watchdog Timer (BWT) Module 7.1.2.1 Wait Mode The functionality of the BWT in Wait mode depends on the value of WCR[WAIT]. When WCR[WAIT]=1, the BWT stops when the device enters Wait mode. When the device leaves Wait mode, the BWT resumes from the state it was in when it stopped. When WCR[WAIT]=0, the BWT continues to operate normally when the device enters Wait mode. 7.1.2.2 Doze Mode The functionality of the BWT in Doze mode depends on the value of WCR[DOZE].
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Backup Watchdog Timer (BWT) Module 7.2.2 Register Descriptions 7.2.2.1 Backup Watchdog Timer Control Register (WCR) The WCR, shown in Figure 7-2, configures the operation of the BWT. It is a read-always/write-once register; after the register is written, the contents cannot be changed until the next Power-On Reset event occurs. This register must be written as a whole. NOTE To ensure that the BWT is properly enabled, the software must write a value to the WMR (see Section 7.2.2.
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Backup Watchdog Timer (BWT) Module 7.2.2.2 Backup Watchdog Timer Modulus Register (WMR) The WMR, shown in Figure 7-3, contains the value (modulus) that is loaded into the BWT count register (WCNTR) when the BWT is serviced. This value effectively corresponds to the BWT’s timeout period. The software must service the timer within this period to avoid a reset.
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Backup Watchdog Timer (BWT) Module IPSBAR Offset: 0x14_0004 (WCNTR) 15 14 13 Access: Supervisor read/write 12 11 10 9 8 R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 WC W Reset 1 1 1 1 1 1 1 1 Figure 7-4. Backup Watchdog Timer Count Register (WCNTR) Table 7-4. WCNTR Field Descriptions Field 15–0 WC Description BWT counter. This field reflects the current value in the BWT counter. 7.2.2.
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Backup Watchdog Timer (BWT) Module 7.3 Functional Description When the BWT is properly enabled, it loads the value in WMR[WM] into WCNTR[WC] and begins to decrement WCNTR[WC]. If WCNTR[WC] reaches zero, the BWT asserts a system reset. To prevent this reset, the BWT requires the software to write 0x5555 and 0xAAAA, in that order, to the WSR. This procedure, referred to as servicing the BWT, reinitializes the value of WCNTR[WC] to the value in WMR[WM]. This logic helps guard against runaway code.
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Chapter 8 Power Management 8.1 Introduction This chapter explains the low-power operation of the MCF52211. 8.1.1 Features The following features support low-power operation. • Four modes of operation: run, wait, doze, and stop • Ability to shut down most peripherals independently • Ability to shut down the external CLKOUT pin 8.2 Memory Map/Register Definition The power management programming model consists of registers from the SCM and CCM memory space, as shown in Table 8-1. Table 8-1.
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Power Management 8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) The PPMRH and PPMRL registers provide a bit map for controlling the generation of the module clocks for each decoded address space associated with the IPS controller. The PPMRx provides a unique control bit for each of these address spaces that defines whether the module clock for the given space is enabled or disabled.
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Power Management Table 8-2. PPMRH Field Descriptions Field 31–12 11 CDCFM 10 Description Reserved, should be cleared. Disable clock to the CFM (Common Flash Module) 0 CFM module clock is enabled 1 CFM module clock is disabled Reserved, should be cleared. 9 CDPWM Disable clock to the PWM module. 0 PWM module clock is enabled 1 PWM module clock is disabled 8 CDGPT Disable clock to the 16 bit general purpose timer module (GPT).
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Power Management 8.2.1.
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Power Management Table 8-3. PPMRL Field Descriptions (continued) Field Description 10 CDQSPI 9 CDI2C Disable clock to the QSPI module. 0 QSPI module clock is enabled 1 QSPI module clock is disabled Disable clock to the I2C module. 0 I2C module clock is enabled 1 I2C module clock is disabled 8 — Reserved, should be cleared. 7 CDUART2 Disable clock to the UART2 module. 0 UART1 module clock is enabled 1 UART2 module clock is disabled 6 CDUART1 Disable clock to the UART1 module.
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Power Management The following is the sequence of operations needed to enable this functionality: 1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropriate interrupt priority level. 2. At the appropriate time, the processor executes the privileged STOP instruction. After the processor has stopped execution, it asserts a specific Processor Status (PST) encoding.
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Power Management Table 8-4. LPICR Field Description (continued) 3–0 — Reserved, should be cleared. Table 8-5. XLPM_IPL Settings 8.2.
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Power Management 8.2.4 Peripheral Power Management Clear Register (PPMRC) The PPMRC register provides a simple memory-mapped mechanism to clear a given bit in the PPMRx registers to enable the clock for a given IPS module without the need to perform a read-modify-write on the PPMRx. The data value on a register write causes the corresponding bit in the PPMRx register to be cleared.
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Power Management Table 8-8. LPCR Field Descriptions Field Description 7–6 LPMD Low-power mode select. Used to select the low-power mode the chip enters after the ColdFire CPU executes the STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable in all modes. Below illustrates the four different power modes that can be configured with the LPMD bit field.
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Power Management the cycle with an error termination. At reset, the IPSBMT is enabled with a maximum timeout value. See Figure 8-7 and Table 8-9 for the IPSBMT definition.
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Power Management A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions: • Any type of reset • Any valid, enabled interrupt request Exiting from low-power mode via an interrupt request requires: • An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR.
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Power Management further details). A peripheral may be disabled at any time and remains disabled during any low-power mode of operation. 8.4.2 8.4.2.1 Peripheral Behavior in Low-Power Modes ColdFire Core The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 8.4.2.2 Static Random-Access Memory (SRAM) SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 8.4.2.
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Power Management 8.4.2.6 I2C Module When the I2C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop mode, the I2C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller.
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Power Management 8.4.2.10 I/O Ports The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is exited by a reset, the state of the I/O pins reverts to their default direction settings. 8.4.2.11 Reset Controller A power-on reset (POR) always causes a chip reset and exit from any low-power mode.
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Power Management 8.4.2.15 Programmable Interrupt Timers (PIT0–PIT1) In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation. When not stopped, the PIT may generate an interrupt to exit the low-power modes. 8.4.2.
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Power Management Table 8-10.
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Chapter 9 Chip Configuration Module (CCM) 9.1 Introduction This chapter describes the various operating configurations of the device. It also provides a description of signals used by the CCM and a programming model. 9.1.1 Features The chip configuration for the MCF52211 is determined by the chip configuration module (CCM).
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Chip Configuration Module (CCM) 9.2.1 RCON The serial flash programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. While the device is in this mode, the EzPort has access to the flash memory, which allows it to be programmed from an external device. 9.2.2 CLKMOD[1:0] The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. Refer to Chapter 6, “Clock Module” for more information. 9.2.
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Chip Configuration Module (CCM) 9.3.2 Memory Map Table 9-3. Chip Configuration Module Memory Map IPSBAR Offset1 Width (bits) Register Access Reset Value Section/Page Supervisor Mode Access Only 0x11_0004 Chip Configuration Register (CCR) 2 0x11_0007 Low-Power Control Register (LPCR) 0x11_0008 Reset Configuration Register (RCON) 0x11_000A Chip Identification Register (CIR) 16 R 0x0001 9.3.3.1/9-3 8 R/W 0x00 8.2.5/8-8 16 R 0x0000 9.3.3.2/9-4 16 R See note3 9.3.3.
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Chip Configuration Module (CCM) 9.3.3.2 Reset Configuration Register (RCON) At reset, RCON determines the default operation of certain chip functions. All default functions defined by the RCON values can only be overridden during reset configuration if the external RCON pin is asserted. RCON is a read-only register.
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Chip Configuration Module (CCM) Table 9-6. CIR Field Description Field Description 15–6 PIN Part identification number. Contains a unique identification number for the device. 5–0 PRN Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order, beginning with zero. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chip Configuration Module (CCM) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 10 Reset Controller Module 10.1 Introduction The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep a history of what caused the reset. The low voltage detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module. 10.
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Reset Controller Module RSTI Pin Power-On Reset RSTO Pin PLL Loss of Clock Reset Controller PLL Loss of Lock To Internal Resets Software Reset LVD Detect Figure 10-1. Reset Controller Block Diagram 10.4 Signals Table 10-1 provides a summary of the reset controller signal properties. The signals are described in the following sections. Table 10-1. Reset Controller Signal Properties 1 10.4.
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Reset Controller Module See Table 10-2 for the memory map and the following paragraphs for a description of the registers. Table 10-2. Reset Controller Memory Map IPSBAR Offset1 1 Width (bits) Register Access Reset Value 0x11_0000 Reset Control Register (RCR) 8 R/W 0x11_0001 Reset Status Register (RSR) 8 R 0x05 Section/Page 10.5.1/10-3 10.5.2/10-4 Addresses not assigned to a register and undefined register bits are reserved for expansion. 10.5.
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Reset Controller Module Table 10-3. RCR Field Descriptions (continued) Field Description 3 LVDIE LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. 1 LVD interrupt enabled 0 LVD interrupt disabled 2 LVDRE LVD reset enable. Controls the LVD reset if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVD reset has priority over LVD interrupt, if both are enabled.
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Reset Controller Module Table 10-4. RSR Field Descriptions (continued) Field 5 SOFT 4 Description Software reset flag. Indicates that the last reset was caused by software. 1 Last reset caused by software 0 Last reset not caused by software Reserved, should be cleared. 3 POR Power-on reset flag. Indicates that the last reset was caused by a power-on reset. 1 Last reset caused by power-on reset 0 Last reset not caused by power-on reset 2 EXT External reset flag.
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Reset Controller Module Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete. Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system. 10.6.1.
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Reset Controller Module 10.6.2 Reset Control Flow The reset logic control flow is shown in Figure 10-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Reset Controller Module 0 1 POR OR LVD Y LOSS OF CLOCK? N 2 LOSS OF LOCK? Y 5 ENABLE BUS MONITOR N 3 RSTI PIN OR WD TIMEOUT OR SW RESET? Y 6 N BUS CYCLE COMPLETE? N 4 ASSERT RSTO AND LATCH RESET STATUS Y 7 ASSERT RSTO AND LATCH RESET STATUS 8 N RSTI NEGATED? Y 9 PLL MODE? Y 9A N PLL LOCKED? Y N 10 12 NEGATE RSTO WAIT 512 CLKOUT CYCLES 11A 11 Y RCON ASSERTED? LATCH CONFIGURATION N Figure 10-4.
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Reset Controller Module 10.6.2.1 Synchronous Reset Requests In this discussion, the references in parentheses refer to the state numbers in Figure 10-4. All cycle counts given are approximate. If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges (3) and if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5). When the current bus cycle is completed (6), RSTO is asserted (7).
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Reset Controller Module If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A). 10.6.3.2 Reset Status Flags For a POR reset, the POR and LVD bits in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the POR.
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Chapter 11 Real-Time Clock 11.1 Introduction This section discusses how to operate and program the real-time clock (RTC) module that maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. 11.1.1 Overview Figure 11-1 is a block diagram of the Real-Time Clock (RTC) module.
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Real-Time Clock 11.1.3 Modes of Operation The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries.
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Memory Map/Register Definition 11.2.1.1 RTC Hours and Minutes Counter Register (HOURMIN) The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. A power-on reset (POR) sets the RTC to the reset values shown in Figure 11-2.
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Real-Time Clock 11.2.1.2 RTC Seconds Counter Register (SECONDS) The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. A power-on reset (POR) sets the RTC to the reset values shown in Figure 11-3.
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Memory Map/Register Definition 11.2.1.3 RTC Hours and Minutes Alarm Register (ALRM_HM) The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and minutes setting for the alarm. The alarm settings can be read or written at any time.
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Real-Time Clock 11.2.1.4 RTC Seconds Alarm Register (ALRM_SEC) The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the alarm. The alarm settings can be read or written at any time.
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Memory Map/Register Definition 11.2.1.5 RTC Control Register (RTCCTL) The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the reference frequency information for the prescaler.
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Real-Time Clock 11.2.1.6 RTC Interrupt Status Register (RTCISR) The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock interrupts. When an event of the types included in this register occurs, then the bit is set in this register regardless of its corresponding interrupt enable bit. These bits are cleared by writing a 1 to them; this also clears the interrupt. Interrupts may occur while the system clock is idle or in sleep mode.
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Memory Map/Register Definition 11.2.1.7 RTC Interrupt Enable Register (RTCIENR) The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit.
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Real-Time Clock 11.2.1.8 RTC Stopwatch Minutes Register (STPWCH) The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. When the minute counter of the TOD clock increments, the value in this register decrements.
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Memory Map/Register Definition 11.2.1.9 RTC Days Counter Register (DAYS) The real-time clock days counter register (DAYS) is used to program the day for the TOD clock. When the HOUR field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset because the real-time clock is always enabled at reset. Only 16-bit accesses to this register are allowed.
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Real-Time Clock 11.2.1.10 RTC Day Alarm Register (ALRM_DAY) The real-time clock day alarm (ALRM_DAY) register is used to configure the day for the alarm. The alarm settings can be read or written at any time.
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Functional Description IPSBAR Offset: 0x03F8 (RTCGOCL) 15 14 13 Access: User read/write 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RTCGOCNT[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 Figure 11-13. RTC General Oscillator Count Lower Register (RTCGOCL) Table 11-13. RTCGOCL Field Descriptions Field Description 15–0 RTC general oscillator count, bits 15:0. This field is used to control the 1 Hz clock and the sampling clock RTCGOCNT[15:0] as described in Section 11.
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Real-Time Clock Interrupts signal when each of the four counters increments, and can be used to indicate when a counter rolls over. For example, each tick of the seconds counter causes the 1HZ interrupt flag to be set. When the seconds counter rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal, and the hour counter with the DAY signal. 11.3.
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Initialization/Application Information Configure RTC Control Register Config RTC Days Counter Register Config RTC Seconds Counter Reg Config RTC Hr/Min Counter Register Config RTC Alarm Registers Config RTC Interrupt Enable Reg Check RTC Interrupt Status Register Figure 11-14. Flow Chart of RTC Operation 11.4.2 Code Example for Initializing the Real-Time Clock Figure 11-15 shows sample code for initializing the RTC.
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Chapter 12 System Control Module (SCM) 12.1 Introduction This section details the functionality of the system control module (SCM) that provides the programming model for the system access control unit (SACU), system bus arbiter, 32-bit core watchdog timer (CWT), and system control registers and logic.
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System Control Module (SCM) • 12.4 System access control unit (SACU) programming model — Master privilege register (MPR) — Peripheral access control registers (PACRs) — Grouped peripheral access control registers (GPACR0, GPACR1) Memory Map and Register Definition The memory map for the SCM registers is shown in Table 12-1.
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System Control Module (SCM) Table 12-1. SCM Register Map (continued) IPSBAR Offset1 Width (bits) Register Access Reset Value Section/Page 0x002C Peripheral Access Control Register (PACR8) 8 R/W 0x00 12.7.3.2/12-14 0x0030 GPACR0 Register 8 R/W 0x00 12.7.3.3/12-16 0x0031 GPACR1 Register 8 R/W 0x00 12.7.3.3/12-16 1 Addresses not assigned to a register and undefined register bits are reserved for expansion.
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System Control Module (SCM) NOTE Accessing reserved IPSBAR memory space could result in an unterminated bus cycle that causes the core to hang. Only a hard reset allows the core to recover from this state. Therefore, all bus accesses to IPSBAR space should fall within a module’s memory map space. If an address hits in overlapping memory regions, the following priority is used to determine what memory is accessed: 1. IPSBAR 2.
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System Control Module (SCM) known as a ping-pong scheme) may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM. After the processor completes the data calculations, it begins processing the recently-loaded buffer while the DMA moves out the recently-calculated data from the other buffer, and reloads the next data block into the recently-freed memory region.
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System Control Module (SCM) • The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the module access to the SRAM. NOTE The RAMBAR default value of 0x0000_0000 is invalid. The RAMBAR located in the processor’s CPU space must be initialized with the valid bit set before the CPU (or modules) can access the on-chip SRAM (see Chapter 5, “Static RAM (SRAM),” for more information. For details on the processor's view of the local SRAM memories, see Section 5.2.
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System Control Module (SCM) 12.5.4 Core Watchdog Control Register (CWCR) The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE]. It is disabled by default. If enabled, the watchdog timer requires the periodic execution of a core watchdog servicing sequence.
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System Control Module (SCM) Table 12-6. CWCR Field Description Field Description 7 CWE Core watchdog enable. 0 SWT disabled. 1 SWT enabled. 6 CWRI Core watchdog interrupt select. 0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 8 (ICR8) of INTC0. 1 Reserved. If a one is written undetermined behavior results.
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System Control Module (SCM) IPSBAR 0x0013 (CWSR) Offset: 7 Access: read/write 6 5 4 3 2 1 0 R CWSR[7:0] W Reset: Uninitialized Figure 12-5. Core Watchdog Service Register (CWSR) 12.6 Internal Bus Arbitration The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 12-6) has access to the external buses. The function of the arbitration logic is described in this section.
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System Control Module (SCM) • • • • There are two arbitration algorithms: fixed and round-robin. Fixed arbitration sets the next-state arbitration pointer to the highest priority requester. Round-robin arbitration sets the next-state arbitration pointer to the highest priority requester (calculated by adding a requester's fixed priority to the current bus master’s fixed priority and then taking this sum modulo the number of possible bus masters).
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System Control Module (SCM) • • Master 2 (M2): 4-channel DMA Master 0 (M0): V2 ColdFire Core IPSBAR Offset: 0x001C (MPARK) R Access: read/write 31 30 29 28 27 26 0 0 0 0 0 0 0 0 1 1 0 0 0 0 15 14 13 12 11 10 9 8 W Reset R 0 W Reset 0 TIME PRKL FIXED OUT AST 0 0 0 25 24 M2_P BCR2 _EN 4BIT LCKOUT_TIME 0 0 0 0 23 22 0 0 1 1 21 20 M2_PRTY 1 0 19 18 M0_PRTY 0 0 17 16 0 0 0 1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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System Control Module (SCM) Table 12-7. MPARK Field Description (continued) Field Description 12 PRKLAST Park on the last active master or highest priority master if no masters are active 0 park on last active master 1 park on highest priority master 11–8 Lock-out Time. Lock-out time for a master being denied the bus. LCKOUT_TIME The lock out time is defined as 2^ LCKOUT_TIME[3:0]. 7–0 Reserved, should be cleared. The initial state of the master priorities is M2 > M0.
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System Control Module (SCM) • User operand write Instruction fetch accesses are associated with the execute attribute. It should be noted that while the bus does not implement the concept of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus.
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System Control Module (SCM) Table 12-8. SACU Register Memory Map (continued) IPSBAR Offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x034 — — — — 0x038 — — — — 0x03C — — — — 12.7.3.1 Master Privilege Register (MPR) The MPR specifies the access privilege level associated with each bus master in the platform. The register provides one bit per bus master. Bit 3 is reserved and should be cleared.
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System Control Module (SCM) IPSBAR 0x0024 + Offset (PACRn) Offset: 7 Access: read/write 6 5 4 3 2 1 0 R LOCK1 ACCESS_CTRL1 LOCK0 ACCESS_CTRL0 W Reset: 0 0 0 0 0 0 0 0 Figure 12-9. Peripheral Access Control Register (PACRn) Table 12-10. PACR Field Descriptions Field Description 7 LOCK1 This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR generates an error termination and the contents of the register are not affected.
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System Control Module (SCM) Table 12-12. Peripheral Access Control Registers (PACRs) (continued) Modules Controlled1 IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 PACR3 UART2 — 0x028 PACR4 2 I C QSPI 0x029 PACR5 — — 0x02A PACR6 DTIM0 DTIM1 0x02B PACR7 DTIM2 DTIM3 0x02C PACR8 INTC0 — 0x027 1 A value of — in these columns indicates that the bits are not associated with any module and are reserved.
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System Control Module (SCM) Table 12-13. Grouped Peripheral Access Control Register (GPACR) Field Descriptions Field Description 7 LOCK This bit, after set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. 6–4 Reserved, should be cleared. 3–0 This 4-bit field defines the access control for the given memory region.
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System Control Module (SCM) Table 12-15. GPACR Address Space Register Space Protected (IPSBAR Offset) Modules Protected GPACR0 0x0000_0000– 0x03FF_FFFF Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, CFM (Control) GPACR1 0x0400_0000– 0x07FF_FFFF CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 13 General Purpose I/O Module 13.1 Introduction Many of the pins associated with the external interface may be used for several different functions. When not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. The digital I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits.
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General Purpose I/O Module 13.2 Overview The MCF52211 ports module controls the configuration for the following external pins: • External bus accesses • Chip selects • Debug data • Processor status • USB • I2C serial control • QSPI • UART transmit/receive • 32-bit DMA timers 13.
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General Purpose I/O Module Table 13-1.
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General Purpose I/O Module 13.6 Register Descriptions 13.6.1 Port Output Data Registers (PORTn) The PORTn registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. The PORTn registers with a full 8-bit implementation are shown in Figure 13-2. The remaining PORTn registers use fewer than 8 bits. Their bit definitions are shown in Figure 13-3, Figure 13-4, Figure 13-5, and Figure 13-6.
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General Purpose I/O Module IPSBAR Offset: 0x10_000C (PORTQS) 7 R Access: User read/write 6 5 4 3 2 1 0 PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 PORTn0 1 1 1 1 1 1 1 0 W Reset: 0 Figure 13-4. Port QS Output Data Register (PORTQS) IPSBAR Offset: 0x10_0008 (PORTNQ) Access: User read/write 7 6 5 4 3 2 1 PORTn7 PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 1 1 1 1 1 1 1 R 0 0 W Reset: 0 Figure 13-5.
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General Purpose I/O Module Setting any bit in a DDRn register configures the corresponding port n pin as an output. Clearing any bit in a DDRn register configures the corresponding pin as an input. IPSBAR 0x10_002C (DDRDD) Offsets: 0x10_0022 (DDRAN) Access: User read/write 7 6 5 4 3 2 1 0 DDRn7 DDRn6 DDRn5 DDRn4 DDRn3 DDRn2 DDRn1 DDRn0 0 0 0 0 0 0 0 0 R W Reset: Figure 13-7.
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General Purpose I/O Module IPSBAR Offset: 0x10_0023 (DDRAS) R Access: User read/write 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DDRn1 DDRn0 0 0 W Reset: 0 0 0 0 0 0 Figure 13-11. Port AS Data Direction Register (DDRAS) Table 13-3. DDRn Field Descriptions Field Description DDRnx 13.6.3 Sets data direction for port nx pin when the port is configured as a digital output.
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General Purpose I/O Module IPSBAR 0x10_003E (PORTTAP/SETTA) Offsets: 0x10_003F (PORTTCP/SETTC) 0x10_0040 (PORTTDP/SETTD) 0x10_0041 (PORTUAP/SETUA) 0x10_0042 (PORTUBP/SETUB) 0x10_0043 (PORTUCP/SETUC) R Access: User read/write 7 6 5 4 0 0 0 0 3 2 1 0 PORTnP3 PORTnP2 PORTnP1 PORTnP0 1 1 1 1 W Reset: 0 0 0 0 Figure 13-13.
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General Purpose I/O Module Table 13-4. PORTnP/SETn Field Descriptions Field Description PortnPx 13.6.4 Port nx pin data/set data bits. 1 PortnPx pin state is 1 (read); writing a 1 sets the corresponding port nx bit to 1 0 PortnPx pin state is 0 Port Clear Output Data Registers (CLRn) Writing 0s to a CLRn register clears the corresponding bits in the PORTn register. Writing 1s has no effect. Reading the CLRn register returns 0s.
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General Purpose I/O Module IPSBAR Offset: 0x10_0054 (CLRQS) 7 R Access: User read/write 6 5 4 3 2 1 0 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 0 0 0 0 0 0 0 0 W Reset: 0 Figure 13-19. Port QS Clear Output Data Register (CLRQS) IPSBAR Offset: 0x10_0050 (CLRNQ) Access: User read/write 7 6 5 4 3 2 1 CLRn7 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 0 0 0 0 0 0 0 R 0 0 W Reset: 0 Figure 13-20.
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General Purpose I/O Module 13.6.5.1 Dual-Function Pin Assignment Registers The dual function pin assignment registers allow each pin controlled by each register bit to be configured for the primary function or the GPIO function. The fields are described in Table 13-6, which applies to all dual-function registers.
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General Purpose I/O Module IPSBAR Offset: 0x10_006C (PQSPAR) R Access: User read/write 15 14 0 0 13 12 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PnPAR6 W Reset R PnPAR3 W Reset 0 11 0 9 PnPAR5 PnPAR2 0 10 PnPAR4 PnPAR1 0 8 PnPAR0 0 0 0 0 Figure 13-24. Port QS Pin Assignment Register (PQSPAR) IPSBAR Offset: 0x10_006B (PASPAR) R Access: User read/write 7 6 5 4 0 0 0 0 3 2 1 PnPAR1 0 PnPAR0 W Reset: 0 0 0 0 0 0 0 0 Figure 13-25.
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General Purpose I/O Module 13.6.5.3 Port NQ Pin Assignment Register (PNQPAR) The port NQ pin assignment register (PNQPAR) contains quad-function (for IRQ1) and dual-function pin assignment controls. Refer to Table 13-6 and Table 13-7 for the encodings for the different fields. The reset value of the PNQPAR register defaults to the primary function (IRQ) instead of GPIO.
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General Purpose I/O Module IPSBAR Offset: 0x10_0078 (PSRR) R W 31 30 29 28 27 26 25 24 PSRR31 PSRR30 PSRR29 PSRR28 PSRR27 PSRR26 PSRR25 PSRR24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 PSRR23 PSRR22 PSRR21 PSRR20 PSRR19 PSRR18 PSRR17 PSRR16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 PSRR15 PSRR14 PSRR13 PSRR12 PSRR11 PSRR10 PSRR9 PSRR8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PSRR7 PSRR6 PSRR5 PSRR4 PSRR3 PSRR2 PSRR1 PSRR0 0 0 0 0
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General Purpose I/O Module 13.6.6.2 Pin Drive Strength Register (PDSR) The pin drive strength register is read/write. Each bit resets to logic 0 in single chip mode (MCF52211 default) and logic 1 in EzPort and FAST mode. The fields are described in Table 13-9. Refer to Table 2-1 for details of which PDSR bit controls which pin.
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Chapter 14 Interrupt Controller Module This section details the functionality for the MCF52211 interrupt controller.
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Interrupt Controller Module fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing to the beginning of a specific exception service routine. In particular, vectors 64–255 of the exception vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the processor to manage reset, error conditions (access, address), arithmetic faults, system calls, etc.
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Interrupt Controller Module Table 14-1. Interrupt Priority Within a Level (continued) ICR[2:0] Priority Interrupt Sources 011 3 8–63 010 2 8–63 001 1 8–63 000 0 (Lowest) 8–63 The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source 1–7 (from the Edge Port module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level.
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Interrupt Controller Module if interrupt source 8 is active and acknowledged, then Vector number = 72 if interrupt source 9 is active and acknowledged, then Vector number = 73 ... if interrupt source 62 is active and acknowledged, then Vector number = 126 The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number. If there is no active interrupt source for the given level, a special spurious interrupt vector (vector number = 24) is returned.
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Interrupt Controller Module Table 14-2.
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Interrupt Controller Module 14.3.1 Interrupt Pending Registers (IPRHn, IPRLn) The IPRHn and IPRLn registers, Figure 14-1 and Figure 14-2, each 32 bits, provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of the interrupt mask register does not affect the IPRn. The IPRn is cleared by reset. The IPRn is a read-only register, so any attempted write to this register is ignored.
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Interrupt Controller Module Table 14-4. IPRLn Field Descriptions Field Description 31–1 INT Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRLn samples the signal generated by the interrupting source. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set.
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Interrupt Controller Module IPSBAR Offset: 0x0C0C (IMRLn) 31 30 Access: Read/write 29 28 27 26 25 R 22 21 20 19 18 17 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MASK ALL INT_MASK[15:1] W Reset 23 INT_MASK[31:16] W Reset 24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 14-4. Interrupt Mask Register Low (IMRLn) Table 14-6. IMRLn Field Descriptions Field Description 31–1 Interrupt mask.
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Interrupt Controller Module request, 0 = negate request) in the appropriate INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is cleared by reset.
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Interrupt Controller Module 14.3.4 Interrupt Request Level Register (IRLRn) This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. IPSBAR Offset: 0x0C18 (IRLRn) 7 Access: Read-only 6 5 R 4 3 2 1 IRQ[7:1] 0 0 W Reset: 0 0 0 0 0 0 0 0 Figure 14-7. Interrupt Request Level Register (IRLRn) Table 14-9.
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Interrupt Controller Module Table 14-10. IACKLPRn Field Descriptions Field 7 Description Reserved 6–4 Interrupt level. Represents the interrupt level currently being acknowledged. LEVEL 3–0 PRI Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged. 0 Priority 0 1 Priority 1 2 Priority 2 3 Priority 3 4 Priority 4 5 Priority 5 6 Priority 6 7 Priority 7 8 Mid-Point Priority associated with the fixed level interrupts only 14.3.
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Interrupt Controller Module IPSBAR Offsets: See Table 14-2 for register offsets (ICRnx) R 7 6 0 0 5 Access: R/W (Read only for ICRn1-ICRn7) 4 3 2 1 IL 0 IP W Reset: 0 0 0 0 0 0 0 0 Note: It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior.
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Interrupt Controller Module 14.3.6.1 Interrupt Sources Table 14-13 lists the interrupt sources for each interrupt request line. Table 14-13.
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Interrupt Controller Module Table 14-13.
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Interrupt Controller Module Table 14-13. Interrupt Source Assignments (continued) Source Module Flag 59 CFM CCIF SGFM command complete Cleared automatically 60 CFM PVIF Protection violation Cleared automatically 61 CFM AEIF Access error Cleared automatically 62 I2C1 IIF I2C interrupt Write IIF = 0 63 RTC RTC RTC Interrupt See Section 11.2.1.6, “RTC Interrupt Status Register (RTCISR)” 14.3.
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Interrupt Controller Module Table 14-14. SWIACKn and LmIACKn Field Descriptions Field Description 7–0 Vector number. A read from the SWIACK register returns the vector number associated with the highest level, VECTOR highest priority unmasked interrupt source. A read from one of the LmIACK registers returns the highest priority unmasked interrupt source within the level. 14.3.8 Global Level m IACK Registers (GLmIACK) In addition to the software IACK registers (Section 14.3.
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Interrupt Controller Module 2. The processor executes a STOP instruction which places it in stop mode. After the processor is stopped, each interrupt controller enables a special logic path that evaluates the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked storage elements.
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Interrupt Controller Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 15 Universal Serial Bus, OTG Capable Controller NOTE Portions of Chapter 15, “Universal Serial Bus, OTG Capable Controller,” relating to the EHCI specification are Copyright © Intel Corporation 1999-2001. The EHCI specification is provided “As Is” with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample.
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Universal Serial Bus, OTG Capable Controller USB software provides a uniform view of the system for all application software, hiding implementation details making application software more portable. It manages the dynamic attach and detach of peripherals. There is only one host in any USB system. The USB interface to the host computer system is referred to as the Host Controller. There may be multiple USB devices in any system such as joysticks, speakers, printers, etc.
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Universal Serial Bus, OTG Capable Controller 15.1.2 USB On-The-Go USB (Universal Serial Bus) is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and hand-held computers to host PCs. The On-The-Go (OTG) Supplement to the USB Specification extends USB to peer-to-peer application.
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Universal Serial Bus, OTG Capable Controller 15.1.3 • • • • • USB-FS Features USB 1.1 and 2.0 compliant full-speed device controller 16-Bidirectional end points DMA or FIFO data stream interfaces Low-power consumption On-The-Go protocol logic 15.2 Functional Description The USB-FS 2.0 full-speed/low-speed module communicates with the ColdFire processor core through status and control registers, and data structures in memory. 15.2.
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Universal Serial Bus, OTG Capable Controller System Memory BDT_PAGE Registers END_POINT IN ODD 000 BDT Page Current Endpoint BDT • • • Buffer in Memory Start of Buffer • • • End of Buffer Figure 15-3. Buffer Descriptor Table 15.3.2 Rx vs. Tx as a USB Target Device or USB Host The USB-FS core can function as a USB target device (function), or as a USB hosts, and may switch modes of operation between host and target device under software control.
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Universal Serial Bus, OTG Capable Controller BDT. The BDT must be located on a 512-byte boundary in system memory. All enabled TX and RX endpoint BD entries are indexed into the BDT to allow easy access via the USB-FS or ColdFire Core. When the USB-FS receives a USB token on an enabled endpoint it uses its integrated DMA controller to interrogate the BDT. The USB-FS must read the corresponding endpoint BD entry and determine if it owns the BD and corresponding buffer in system memory.
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Universal Serial Bus, OTG Capable Controller 31:26 25:16 15:8 7 6 5 4 3 2 1 0 RSVD BC (10-Bits) RSVD OWN DATA0/1 KEEP/ TOK_PID[3] NINC/ TOK_PID[2] DTS/ 5 TOK_PID[1] BDT_STALL/ TOK_PID[0] 0 0 Buffer Address (32-Bits) Figure 15-5. Buffer Descriptor Byte Format Table 15-3. Buffer Descriptor Byte Fields Field Description 31 – 26 RSVD Reserved 25 – 16 BC[9:0] The Byte Count bits represent the 10-bit Byte Count.
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Universal Serial Bus, OTG Capable Controller Table 15-3. Buffer Descriptor Byte Fields (continued) 1–0 Reserved ADDR[31:0] 15.3.5 Reserved, should read as zeroes The Address bits represent the 32 -bit buffer address in system memory. These bits are unchanged by the USB-FS. USB Transaction When the USB-FS transmits or receives data, it computes the BDT address using the address generation shown in Table 2.
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Universal Serial Bus, OTG Capable Controller because it is assumed that a second attempt will be queued and succeed in the future. For host mode, the TOK_DNE interrupt fires and the TOK_PID field of the BDT is 1111 to indicate the DMA latency error. Host mode software can decide to retry or move to another item in its schedule. In the second case of oversized data packets the USB specification is very ambiguous. It assumes correct software drivers on both sides.
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Universal Serial Bus, OTG Capable Controller Table 15-4.
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Universal Serial Bus, OTG Capable Controller IPSBAR Offset: 0x1C_0000 (PER_ID) R Access: User read-only 7 6 5 4 3 2 1 0 0 0 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 0 0 1 0 0 W Reset: Figure 15-7. Peripheral ID Register (PER_ID) Table 15-11. PER_ID Field Descriptions Field Description 7–6 These bits always read zeros 5–0 IDx Peripheral identification bits. These bits always read 0x04 (00_0100). 15.4.1.
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Universal Serial Bus, OTG Capable Controller 15.4.1.3 Peripheral Revision Register (REV) This register contains the revision number of the USB Module. Figure 15-9 shows the REV register. IPSBAR Offset: 0x1C_0008 (REV) R Access: User read-only 7 6 5 4 3 2 1 0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0 0 1 1 0 0 1 1 W Reset: Figure 15-9. Peripheral Revision Register Table 15-13. REV Field Descriptions Field 7–0 REVx 15.4.1.
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Universal Serial Bus, OTG Capable Controller 15.4.1.5 OTG Interrupt Status Register (OTG_INT_STAT) The OTG Interrupt Status Register records changes of the ID sense and VBUS signals. Software can read this register to determine which event has caused an interrupt. Only bits that have changed since the last software read are set. Writing a one to a bit clears the associated interrupt. Figure 15-11 shows the OTG_INT_STAT register.
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Universal Serial Bus, OTG Capable Controller 15.4.1.6 OTG Interrupt Control Register (OTG_INT_EN) The OTG Interrupt Control Register enables the corresponding interrupt status bits defined in the OTG Interrupt Status Register. Figure 15-12 shows the OTG_INT_EN register. IPSBAR Offset: 0x1C_0014 (OTG_INT_EN) 7 6 5 4 3 2 1 0 1_MSEC _EN LINE_STATE_ EN Reserved – SESS_VLD _EN B_SESS _EN Reserved ID_EN – A_VBUS _EN 0 0 X 0 0 X 0 R W Reset: Access: User read/write 0 Figure 15-12.
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Universal Serial Bus, OTG Capable Controller 15.4.1.7 Interrupt Status Register (OTG_STAT) The Interrupt Status Register displays the actual value from the external comparator outputs of the ID pin and VBUS. Figure 15-13 shows the OTG_STAT register. IPSBAR Offset: 0x1C_0018 (OTG_STAT) Access: User read/write 7 6 5 4 1_MSEC_EN LINE_STATE _STABLE Reserved ID 0 X R W Reset: 0 0 3 2 1 0 B_SESS _END Reserved SESS_VLD – A_VBUS _VLD 0 X 0 – 0 Figure 15-13.
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Universal Serial Bus, OTG Capable Controller 15.4.1.8 OTG Control Register (OTG_CTRL) The OTG Control Register controls the operation of VBUS and Data Line termination resistors. Figure 15-14 shows the OTG_CTRL register. IPSBAR Offset: 0x1C_001C (OTG_CTRL) 7 R Access: User read/write 6 5 4 3 2 1 0 DP_LOW DM_LOW VBUS_ON OTG_EN VBUS_ CHG VBUS_ DSCHG 0 0 0 0 0 0 RSVD DP_HIGH W Reset: 0 0 Figure 15-14. OTG Control Register Table 15-18.
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Universal Serial Bus, OTG Capable Controller 15.4.1.9 Interrupt Status Register (INT_STAT) The Interrupt Status Register contains bits for each of the interrupt sources within the USB Module. Each of these bits are qualified with their respective interrupt enable bits (see Section 15.4.1.10, “Interrupt Enable Register (INT_ENB)”). All bits of this register are logically OR’d together along with the OTG Interrupt Status Register (OTG_STAT) to form a single interrupt source for the ColdFire core.
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Universal Serial Bus, OTG Capable Controller 15.4.1.10 Interrupt Enable Register (INT_ENB) The Interrupt Enable Register contains enable bits for each of the interrupt sources within the USB Module. Setting any of these bits enables the respective interrupt source in the INT_STAT register. This register contains the value of 0x00 after a reset. Figure 15-16 shows the INT_ENB register.
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Universal Serial Bus, OTG Capable Controller 15.4.1.11 Error Interrupt Status Register (ERR_STAT) The Error Interrupt Status Register contains enable bits for each of the error sources within the USB Module. Each of these bits are qualified with their respective error enable bits (see Section 15.4.1.12, “Error Interrupt Enable Register (ERR_ENB)”). All bits of this Register are logically OR’d together and the result placed in the ERROR bit of the INT_STAT register.
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Universal Serial Bus, OTG Capable Controller 15.4.1.12 Error Interrupt Enable Register (ERR_ENB) The Error Interrupt Enable Register contains enable bits for each of the error interrupt sources within the USB Module. Setting any of these bits enables the respective interrupt source in the ERR_STAT register. Each bit is set as soon as the error conditions is detected. Therefore, the interrupt does not typically correspond with the end of a token being processed.
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Universal Serial Bus, OTG Capable Controller 15.4.1.13 Status Register (STAT) The Status Register reports the transaction status within the USB Module. When the ColdFire core has received a TOK_DNE interrupt the Status Register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted. The STAT register is actually a read window into a status FIFO maintained by the USB Module.
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Universal Serial Bus, OTG Capable Controller 15.4.1.14 Control Register (CTL) The Control Register provides various control and configuration information for the USB Module. Figure 15-20 shows the CTL register. IPSBAR Offset: 0x1C_0094 (CTL) 7 6 5 4 3 2 1 0 JSTATE SE0 TXSUSPEND/ TOKENBUSY RESET HOST_ MODE_EN RESUME ODD_RST USB_EN/ SOF_EN 0 0 0 0 0 0 0 0 R W Reset: Access: User read/write Figure 15-20. Control Register Table 15-24.
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Universal Serial Bus, OTG Capable Controller 15.4.1.15 Address Register (ADDR) The Address Register holds the unique USB address that the USB Module decodes when in Peripheral mode (HOST_MODE_EN=0). When operating in Host mode (HOST_MODE_EN=1) the USB Module transmits this address with a TOKEN packet. This enables the USB Module to uniquely address an USB peripheral. In either mode, the USB_EN bit within the control register must be set.
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Universal Serial Bus, OTG Capable Controller 15.4.1.16 BDT Page Register 1 (BDT_PAGE_01) The Buffer Descriptor Table Page Register 1 contains an 8-bit value that is used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. Figure 15-22 shows the BDT Page Register 1.
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Universal Serial Bus, OTG Capable Controller 15.4.1.17 Frame Number Register Low/High (FRM_NUML, FRM_NUMH) The Frame Number Register Low contains an 8-bit value that is used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. Figure 15-23 shows the FRM_NUML Register. IPSBAR Offset: 0x1C_00A0 (FRM_NUML) R Access: User read-only 7 6 5 4 3 2 1 0 FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 0 0 0 0 0 0 0 0 W Reset: Figure 15-23.
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Universal Serial Bus, OTG Capable Controller 15.4.1.18 Token Register (TOKEN) The Token Register is used to perform USB transactions when in host mode (HOST_MODE_EN=1). When the ColdFire core processor wishes to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this register. After this register has been written, the USB module begins the specified USB transaction to the address contained in the address register.
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Universal Serial Bus, OTG Capable Controller 15.4.1.19 SOF Threshold Register (SOF_THLD) The SOF Threshold Register is used only in Hosts mode (HOST_MODE_EN=1). When in Host mode, the 14-bit SOF counter counts the interval between SOF frames. The SOF must be transmitted every 1msec so the SOF counter is loaded with a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF) token is transmitted.
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Universal Serial Bus, OTG Capable Controller 15.4.1.20 BDT Page Register 2 (BDT_PAGE_02) The Buffer Descriptor Table Page Register 2 contains an 8-bit value that is used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. See Section 15.4.1.16, “BDT Page Register 1 (BDT_PAGE_01)” for more information on the format of the Buffer Descriptor Table. Figure 15-27 shows the BDT Page Register 2.
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Universal Serial Bus, OTG Capable Controller 15.4.1.22 Endpoint Control Registers 0 – 15 (ENDPT0–15) The Endpoint Control Registers contain the endpoint control bits for each of the 16 endpoints available within the USB Module for a decoded address. The format for these registers is shown in the following figure. Endpoint 0 (ENDPT0) is associated with control pipe 0 which is required for all USB functions.
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Universal Serial Bus, OTG Capable Controller Table 15-33. BDT_PAGE_03 Field Descriptions (continued) Field 5 Description Reserved 4 This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This EP_CTL_DIS applies if and only if the EP_RX_EN and EP_TX_EN bits are also set. SeeTable 15-34 3 EP_RX_EN This bit, when set, enables the endpoint for RX transfers. SeeTable 15-34 2 EP_TX_EN This bit, when set, enables the endpoint for TX transfers.
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Universal Serial Bus, OTG Capable Controller 15.4.1.23 USB Control Register (USB_CTRL) IPSBAR Offset: 0x1C_0100 (USB_CTRL) 7 6 SUSP PDE 0 1 R Access: User read/write 5 4 3 2 — — — — 1 0 CLK_SRC W Reset: 0 0 0 0 1 1 Figure 15-30. USB Control Register Table 15-35. USB_CTRL Field Descriptions Field 7 SUSP Description Places the USB transceiver into the suspend state. 0 USB transceiver is not in suspend state. 1 USB transceiver is in suspend state.
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Universal Serial Bus, OTG Capable Controller 15.4.1.24 USB OTG Observe Register (USB_OTG_OBSERVE) IPSBAR Offset: 0x1C_0104 (USB_OTG_OBSERVE) 7 6 DP_PU DP_PD 1 1 R 5 Access: User read/write 4 3 2 1 DM_PD VBUSE VBUSCHG VBUSDIS 0 0 0 1 0 0 1 W Reset: 0 1 Figure 15-31. USB OTG Observe Register Table 15-36. USB_OTG_OBSERVE Field Descriptions Field Description 7 DP_PU Provides observability of the D+ Pull Up signal output from the USB OTG module.
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Universal Serial Bus, OTG Capable Controller 15.4.1.25 USB OTG Control Register (USB_OTG_CONTROL) IPSBAR Offset: 0x1C_0108 (USB_OTG_CONTROL) R 7 6 5 — — — Access: User read/write 4 3 2 1 0 VBUSD ID VBUSVLD SESSVLD SESSEND 0 0 0 0 0 W Reset: 0 0 0 Figure 15-32. USB OTG Control Register Table 15-37.
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Universal Serial Bus, OTG Capable Controller Host mode is intended for use in handheld-portable devices to allow easy connection to simple HID class devices such as printers and keyboards. It is NOT intended to perform the functions of a full OHCI or UHCI compatible host controller found on PC motherboards. The USB-FS is not supported by Windows 98 as a USB host controller. Host mode allows bulk, Isochronous, interrupt and control transfers.
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Universal Serial Bus, OTG Capable Controller To complete a control transaction to a connected device: 1. Complete all steps discover a connected device 2. Set up the endpoint control register for bidirectional control transfers EP_CTL0[4:0] = 0x0d. 3. Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the USB 2.0 specification [2] for information on the device framework command set. 4.
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Universal Serial Bus, OTG Capable Controller To send a Full speed bulk data transfer to a target device: 1. Complete all steps discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant. 2. Write the ENDPT0 to 0x1D register to enable transmit and receive transfers with handshaking enabled. 3.
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Universal Serial Bus, OTG Capable Controller A_IDLE B_IDLE A_WAIT_VFALL A_WAIT_VRISE A_PERIPHERAL A_WAIT_BCON A_SUSPEND A_HOST Figure 15-33. Dual Role A Device Flow Diagram Table 15-38. State Descriptions for Figure 15-33 State Action A_IDLE A_WAIT_VRISE A_WAIT_BCON A_HOST Response If ID Interrupt. The cable has been un-plugged or a Type B cable has been attached. The device now acts as a Type B device.
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Universal Serial Bus, OTG Capable Controller Table 15-38. State Descriptions for Figure 15-33 (continued) State A_SUSPEND A_PERIPHERAL A_WAIT_VFALL 15.7.2 Action Response If ID Interrupt, or if 150 msec B disconnect timeout (This timeout value could be longer) or if A_VBUS_VLD\ Interrupt Go to A_WAIT_VFALL Turn off DRV_VBUS If HNP enabled, and B disconnects in 150 msec then B device is becoming the host.
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Universal Serial Bus, OTG Capable Controller Table 15-39. State Descriptions for Figure 15-34 (continued) State Action Response B_SRP_INIT If ID\ Interrupt or SRP Done (SRP must be done in less than 100 msecs.) Go to B_IDLE B_PERIPHERAL If HNP enabled and the bus is suspended and B wants the bus, the B device can become the host.
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Universal Serial Bus, OTG Capable Controller 15.7.4 USB Suspend State USB bus powered devices are required to respond to a 3ms lack of activity on the USB bus by going into a suspend state. Software is notified of the suspend condition via the transition in the port status and control register or, optionally, an interrupt can be generated which is controlled by the interrupt enable register. In the suspend state, a USB device has a maximum USB bus power budget of 500uA.
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Chapter 16 Edge Port Module (EPORT) 16.1 Introduction The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. NOTE Not all EPORT signals may be output from the device. See Chapter 2, “Signal Descriptions,” to determine which signals are available.
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Edge Port Module (EPORT) 16.2 Low-Power Mode Operation This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 8, “Power Management”. Table 16-1 shows EPORT-module operation in low-power modes and describes how this module may exit each mode. NOTE The control register (CR) in the system control module specifies the interrupt level at or above what is needed to bring the device out of a low-power mode. Table 16-1.
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Edge Port Module (EPORT) Table 16-2. Edge Port Module Memory Map IPSBAR Offset Width Access Reset Value (bits) Register Section/Page Supervisor Access Only Registers1 0x13_0000 EPORT Pin Assignment Register (EPPAR) 16 R/W 0x0000 16.4.1/16-3 0x13_0002 EPORT Data Direction Register (EPDDR) 8 R/W 0x00 16.4.2/16-4 0x13_0003 EPORT Interrupt Enable Register (EPIER) 8 R/W 0x00 16.4.3/16-4 Supervisor/User Access Registers 1 0x13_0004 EPORT Data Register (EPDR) 8 R/W 0xFF 16.4.
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Edge Port Module (EPORT) 16.4.2 EPORT Data Direction Register (EPDDR) The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually. : 0x002 (EPDDR) R W Reset Access: Supervisor read/write 7 6 5 4 3 2 1 EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 0 0 0 0 0 0 0 0 0 0 Figure 16-3. EPORT Data Direction Register (EPDDR) Table 16-4.
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Edge Port Module (EPORT) 16.4.4 Edge Port Data Register (EPDR) The EPORT data register (EPDR) holds the data to be driven to the pins. IPSBAR 0x13_0004 (EPDR) Offset: Access: User read/write 7 6 5 4 3 2 1 EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 1 1 1 1 1 1 1 R 0 0 W Reset: 1 Figure 16-5. EPORT Port Data Register (EPDR) Table 16-6. EPDR Field Descriptions Field Description 7–1 EPDn Edge Port Data Bits.
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Edge Port Module (EPORT) 16.4.6 Edge Port Flag Register (EPFR) The EPORT flag register (EPFR) individually latches EPORT edge events. IPSBAR 0x13_0006 (EPFR) Offset: Access: User read/write 7 6 5 4 3 2 1 EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 0 0 0 0 0 0 0 R 0 0 W Reset: 0 Figure 16-7. EPORT Port Flag Register (EPFR) Table 16-8. EPFR Field Descriptions Field Description 7–1 EPFn Edge port flag bits.
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Chapter 17 DMA Controller Module 17.1 Introduction This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. NOTE The designation n is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0, DMA1, DMA2, or DMA3. 17.1.
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DMA Controller Module DREQ0 DREQ1 DREQ2 DREQ3 Channel 0 Channel 1 Channel 2 Channel 3 Internal Bus SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 DSR0 DSR1 DSR2 DSR3 Channel Requests Interrupts Channel Attributes Channel Enables System Bus Address MUX MUX Control System Bus Size Current Master Attributes Arbitration/ Control Data Path Read Data Bus Bus Interface Data Path Control Write Data Bus Registered Bus Signals Figure 17-1.
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DMA Controller Module 17.2 DMA Transfer Overview The DMA module can data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four channels at once.
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DMA Controller Module Table 17-1.
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DMA Controller Module Table 17-2. DMAREQC Field Description Field Description 15–0 DMACn DMA channel n. Each four bit field defines the logical connection between the DMA requesters and that DMA channel.There are ten possible requesters (4 DMA Timers and 6 UARTs). Any request can be routed to any of the DMA channels. Effectively, the DMAREQC provides a software-controlled routing matrix of the 10 DMA request signals to the 4 channels of the DMA module.
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DMA Controller Module IPSBAR 0x00_0104 (DAR0) Offsets: 0x00_0114 (DAR1) 0x00_0124 (DAR2) 0x00_0134 (DAR3) 31 30 Access: read/write 29 28 27 26 25 24 R 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R DAR W Reset 22 DAR W Reset 23 0 0 0 0 0 0 0 0 Figure 17-5. Destination Address Registers (DARn) 17.3.
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DMA Controller Module IPSBAR Offsets: See Figure 17-6 (DSRn) 7 R Access: read/write 6 5 4 3 CE BES BED 0 0 0 0 2 1 0 REQ BSY DONE 0 0 0 0 W Reset: 0 0 Figure 17-7. DMA Status Registers (DSRn) Table 17-3. DSRn Field Descriptions Field 7 6 CE Description Reserved, should be cleared. Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR equals 0 when the DMA receives a start condition.
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DMA Controller Module 17.3.5 DMA Control Registers (DCRn) The DMA control registers (DCRn) are described in Figure 17-8 and Table 17-4.
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DMA Controller Module Table 17-4. DCRn Field Descriptions (continued) Field Description 27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus. BWC Number of kilobytes per block 000 DMA has priority and does not negate its request until transfer completes.
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DMA Controller Module Table 17-4. DCRn Field Descriptions (continued) Field Description 15–12 SMOD Source address modulo. Defines the size of the source data circular buffer used by the DMA Controller. If enabled (SMOD is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulocircular buffer size boundary. Misaligned buffers are not possible.
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DMA Controller Module Table 17-4. DCRn Field Descriptions (continued) Field Description 5–4 LINKCC Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. 00 No channel-to-channel linking 01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero.
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DMA Controller Module Source and destination address registers (SARn and DARn) can be programmed in the DCRn to increment at the completion of a successful transfer. 17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports internal and external requests. A request is issued by setting DCRn[START] or when a UART or DMA timer asserts a DMA request. Setting DCRn[EEXT] enables recognition of external DMA requests.
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DMA Controller Module 17.4.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block. 17.4.3.1 Channel Prioritization The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or in an order determined by DCRn[BWC].
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DMA Controller Module As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or a peripheral DMA request, depending on the status of DCRn[EEXT]. Programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, a peripheral DMA request must be asserted before the channel requests the bus. Changes to DCRn are effective immediately while the channel is active.
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DMA Controller Module If BWC equals 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the core. In this scheme, the arbiter can always force the DMA to relinquish the bus. See Section 13.6.3, “Bus Master Park Register (MPARK).” 17.4.
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Chapter 18 ColdFire Flash Module (CFM) 18.1 18.1.1 Introduction Overview The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module for integration with a CPU. The CFM provides 128 Kbytes of 32-bit Flash memory serving as electrically erasable and programmable, non-volatile memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring external programming voltage sources.
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ColdFire Flash Module (CFM) COMMON FLASH BUS EVEN ODD COMMON FLASH BUS INTERFACE EVEN BLOCK ARRAY 0 ARRAY 1 ODD BLOCK ARRAY 2 ARRAY 3 FLASH MEMORY CONTROLLER FLASH COMMAND CONTROLLER INTERNAL FLASH BUS INTERFACE INTERNAL FLASH BUS Figure 18-1. CFM Block Diagram 18.1.
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ColdFire Flash Module (CFM) • • • Protection scheme to prevent accidental program or erase of flash memory Access restriction control for supervisor/user and data/instruction operations Security feature to prevent unauthorized access to the flash memory 18.2 External Signal Description The CFM contains no signals that connect off-chip for the end customer. 18.3 Memory Map and Register Definition This section describes the CFM memory map and registers. 18.3.
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ColdFire Flash Module (CFM) Table 18-1. CFM Configuration Field Address Offset (from PROGRAM_ARRAY_BASE) Size (bytes) Description 0x0400 - 0x0407 8 Backdoor Comparison Key 0xFFFF_FFFF_FFFF_FFF F 0x0408 - 0x040B 4 Flash Protection Bytes (see Section 18.3.3.4, “CFMPROT — CFM Protection Register”) 0xFFFF_FFFF 0x040C - 0x040F 4 Flash SUPV Access Bytes (see Section 18.3.3.5, “CFMSACC — CFM Supervisor Access Register”) 0xFFFF_FFFF 0x0410 - 0x0413 4 Flash DATA Access Bytes (see Section 18.3.3.
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ColdFire Flash Module (CFM) NOTE Flash accesses (reads/writes) by a bus master other than the core, DMA controller, or writes to flash by the core during programming must use the backdoor flash address of IPSBAR plus an offset of 0x0400_0000. For example, for a DMA transfer from the first location of flash when IPSBAR is at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000.
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ColdFire Flash Module (CFM) Table 18-2. FLASHBAR Field Descriptions Bits Name 31–19 BA[31:18] 18–9 — 8 WP 7–6 — 5–1 Description Base Address Field. Defines the 0-modulo-512K base address of the flash module. By programming this field, the flash may be located on any 512-Kbyte boundary within the processor’s four gigabyte address space. Reserved, should be cleared. Write Protect. Write only. Allows only read accesses to the flash.
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ColdFire Flash Module (CFM) Table 18-3. CFM Register Address Map Register Bits IPSBAR Offset 31 - 24 23 - 16 0x1D_001C CFMUSTAT RESERVED1 0x1D_0024 CFMCMD RESERVED1 0x1D_0028 RESERVED1 0x1D_002C RESERVED1 0x1D_0030 RESERVED1 0x1D_0034 RESERVED1 0x1D_0038 RESERVED1 0x1D_003C RESERVED1 0x1D_0040 RESERVED1 RESERVED1 RESERVED1 0x1D_0048 18.3.3 7-0 0x1D_0020 0x1D_0044 1 15 - 8 RESERVED1 CFMCLKSEL Access to reserved address locations generate a cycle termination transfer error.
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ColdFire Flash Module (CFM) Table 18-4. CFMMCR Field Descriptions (continued) Field Description 8 AEIE Access Error Interrupt Enable The AEIE bit is always readable and writable. The AEIE bit enables an interrupt in case the access error flag, ACCERR in the CFMUSTAT register, is set. 1 = An interrupt is requested when the ACCERR flag is set. 0 = ACCERR interrupt disabled. 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit is always readable and writable.
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ColdFire Flash Module (CFM) All CFMCLKD register bits are readable, while bits [6:0] write once and bit 7 is not writable. Table 18-5. CFMCLKD Field Descriptions Field Description 7 DIVLD Clock Divider Loaded 1 = CFMCLKD register has been written to since the last reset. 0 = CFMCLKD register has not been written. 6 PRDIV8 Enable Prescaler by 8 1 = Enables a prescaler to divide the internal flash bus clock by 8 before feeding into the clock divider.
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ColdFire Flash Module (CFM) Table 18-6. CFMSEC Field Descriptions Field Description 29-16 Reserved, should read 0 15 - 0 SEC Flash memory security bits The SEC bits define the security state of the MCU as shown in Table 18-7, which defines the single code that enables the security feature in the CFM The CFMSEC register is loaded from the flash configuration field in the flash block at offset 0x0414 during the reset sequence, indicated by F in Figure 18-6. Table 18-7.
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ColdFire Flash Module (CFM) To change the flash memory protection on a temporary basis, the CFMPROT register should be written after the LOCK bit in the CFMMCR register has been cleared. To change the flash memory protection loaded during the reset sequence, the flash logical sector containing the flash configuration field must first be unprotected, and then the flash protection bytes must be programmed with the desired value. Table 18-8.
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ColdFire Flash Module (CFM) 18.3.3.5 CFMSACC — CFM Supervisor Access Register The CFMSACC register is used to control supervisor/user access to the flash memory.
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ColdFire Flash Module (CFM) 18.3.3.6 CFMDACC — CFM Data Access Register The CFMDACC register is used to control data/instruction access to the flash memory.
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ColdFire Flash Module (CFM) CFMUSTAT register bits CBEIF, PVIOL, ACCERR, and BLANK are readable and writable while CCIF is readable but not writable, and remaining bits read 0 and are not writable. The CFMUSTAT register bits CBEIF, CCIF, PVIOL, ACCERR, and BLANK are available as external signals CFM_STATUS_BITS[7:4,2] on the module boundary. NOTE Only one CFMUSTAT register bit can be cleared at a time. Table 18-11.
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ColdFire Flash Module (CFM) Table 18-11. CFMUSTAT Field Descriptions Field Description 2 BLANK All flash memory locations or the selected flash logical page have been verified as erased. The BLANK flag, set by the flash command controller, indicates that a blank check or page erase verify operation has checked all flash memory locations or the selected flash logical page and found them to be erased. The BLANK flag is cleared by writing a 1 to BLANK. Writing a 0 to the BLANK flag has no effect on BLANK.
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ColdFire Flash Module (CFM) 18.3.3.9 CFMCLKSEL — CFM Clock Select Register The CFMCLKSEL register reflects the factory setting for read access latency from the system bus to the flash block. IPSBAR Offset: 0x1D_004A(CFMCLKSEL) R Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1 W Reset 1 F1 Reset state set by factory. Figure 18-13.
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ColdFire Flash Module (CFM) 18.4.2 Flash Normal Mode In flash normal mode, the user can access the CFM registers and the CFM flash memory (see Section 18.3.1, “Memory Map”). 18.4.2.1 Read Operation A valid read operation occurs when a transfer request is initiated, the address is equal to an address within the valid range of the CFM flash memory space, and the read/write control indicates a read cycle. 18.4.2.
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ColdFire Flash Module (CFM) Therefore, the clock to the flash block timing control, FCLK, is: FCLK = (input clock) / (DIV + 1) 150KHz < FCLK <= 200KHz For example, if the input clock frequency is 33 MHz, the CFMCLKD DIV field should be set to 0x14 and bit PRDIV8 set to 1. The resulting FCLK is 196.4 KHz. As a result, the flash memory program and erase algorithm timings are increased over the optimum target by: (200 - 196.4) / 200 x 100% = 1.
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ColdFire Flash Module (CFM) buffered command waits for the active command to be completed before being launched. The CCIF flag in the CFMUSTAT register set upon completion of all active and buffered commands. A command write sequence can be aborted at anytime prior to clearing the CBEIF flag in the CFMUSTAT register by writing a 0 to the CBEIF flag.
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ColdFire Flash Module (CFM) check operation (CCIF=1), the BLANK flag sets in the CFMUSTAT register if the entire flash memory is erased. If any flash memory location is not erased, the blank check operation terminates and the BLANK flag remains clear.
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ColdFire Flash Module (CFM) Page Erase Verify The page erase verify operation verifies all memory addresses in a flash logical page are erased. An example flow to execute the page erase verify operation is shown in Figure 18-15. The page erase verify command write sequence is as follows: 1. Write to any word address in a flash logical page to start the command write sequence for the page erase verify command.
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ColdFire Flash Module (CFM) START Read: Register CFMCLKD Bit DIVLD Set? Clock Register Written Check no yes Write: Register CFMCLKD Read: Register CFMUSTAT Address, Data, Command Buffer Empty Check Bit CBEIF Set? no yes Bit ACCERR/PVIOL yes Write: Register CFMUSTAT Clear bit ACCERR/PVIOL 0x30 Set? Access Error and Protection Violation Check no 1. Write: Logical Page Address and Dummy Data 2.
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ColdFire Flash Module (CFM) An example flow to execute the program operation is shown in Figure 18-16. The program command write sequence is as follows: 1. Write to a word address in a flash physical block to start the command write sequence for the program command. The word address written determines the flash physical block address to program while the data written during the program command write sequence determines the data stored at that address.
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ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written Check Bit DIVLD Set? yes no Write: Register CFMCLKD Read: Register CFMUSTAT Bit CBEIF Set? no yes Bit ACCERR/PVIOL yes Write: Register CFMUSTAT Clear bit ACCERR/PVIOL 0x30 Set? Access Error and Protection Violation Check no 1. Write: Array Address and Data 2. Write: Register CFMCMD Program Command 0x20 NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. 3.
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ColdFire Flash Module (CFM) An example flow to execute the page erase operation is shown in Figure 18-17. The page erase command write sequence is as follows: 1. Write to any word address in a flash logical page to start the command write sequence for the page erase command. The word address written determines the flash logical page to erase while the data written during the page erase command write sequence is ignored. 2. Write the page erase command, $40, to the CFMCMD register. 3.
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ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written Check Bit DIVLD Set? yes no Write: Register CFMCLKD Read: Register CFMUSTAT Bit CBEIF Set? no yes Access Error and Protection Violation Check Bit ACCERR/PVIOL yes Write: Register CFMUSTAT Clear bit ACCERR/PVIOL 0x30 Set? no 1. Write: Logical Page Address and Dummy Data 2. Write: Register CFMCMD Page Erase Command 0x40 NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. 3.
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ColdFire Flash Module (CFM) An example flow to execute the mass erase command is shown in Figure 18-18. The mass erase command write sequence is as follows: 1. Write to any flash memory address to start the command write sequence for the mass erase command. The specific address and data written during the mass erase command write sequence is ignored. 2. Write the mass erase command, $41, to the CFMCMD register. 3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the mass erase command.
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ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written Check Bit DIVLD Set? yes no Write: Register CFMCLKD Read: Register CFMUSTAT Bit CBEIF Set? no yes Access Error and Protection Violation Check Bit ACCERR/PVIOL yes Write: Register CFMUSTAT Clear bit ACCERR/PVIOL 0x30 Set? no 1. Write: Array Address and Dummy Data 2. Write: Register CFMCMD Mass Erase Command 0x41 NOTE: command write sequence aborted by writing 0x00 to CFMUSTAT register. 3.
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ColdFire Flash Module (CFM) 18.4.2.3.5 Flash Normal Mode Illegal Operations The ACCERR flag is set during the command write sequence if any of the following illegal operations are performed, causing the command write sequence to immediately abort: • Writing to the flash memory before initializing CFMCLKD. • Writing to the flash memory while CBEIF is not set. • Writing to a flash block with a data size other than 32 bits.
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ColdFire Flash Module (CFM) If a command is not active (CCIF=1) when the MCU enters stop mode, the ACCERR flag does not set. 18.4.3 Flash Security Operation The CFM provides security information to the integration module and the rest of the MCU. This security information is stored within a word in the flash configuration field. This security word is read automatically after each reset and stored in the CFMSEC register.
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ColdFire Flash Module (CFM) 18.4.3.2 Blank Check A secured CFM can be unsecured by verifying that the entire flash memory is erased. If required, the mass erase command can be executed on the flash memory. The blank check command must then be executed on the flash memory. The CFM is unsecured if the blank check operation determines that the entire flash memory is erased. After the next reset sequence, the security state of the CFM is determined by the flash security word at address offset 0x0414.
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ColdFire Flash Module (CFM) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 19 EzPort EzPort is a serial flash programming interface that allows the flash memory contents on a 32-bit general purpose microcontroller to be read, erased, and programmed from off-chip in a compatible format to many standalone flash memory chips. 19.
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EzPort Figure 19-1 is a block diagram of the EzPort. EzPort Enabled G EZPCS EZPCK Flash Controller EzPort EZPD EZPQ Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 19-1. EzPort Block Diagram 19.3 External Signal Description 19.3.1 Overview Table 19-1 contains a list of EzPort external signals. Table 19-1. Signal Descriptions 19.3.2 19.3.2.
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EzPort EZPCK.The maximum frequency of the EzPort clock is half the system clock frequency for all commands except when executing the read data command. When executing the Read Data command, the EzPort clock has a maximum frequency of one eighth the system clock frequency. 19.3.2.2 EZPCS — EzPort Chip Select EzPort chip select (EZPCS) is the chip select for signalling the start and end of serial transfers.
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EzPort 19.4.1 Command Descriptions 19.4.1.1 Write Enable The Write Enable command sets the write enable register bit in the status register. The write enable bit must be set for a Write Configuration Register (WRCR), Page Program (PP), Sector Erase (SE), or Bulk Erase (BE) command to be accepted. The write enable register bit clears on reset, on a Write Disable command, and at the completion of a write, program, or erase command. This command should not be used if a write is already in progress. 19.4.
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EzPort Table 19-3. EzPort Status Register Field Description (continued) Field Descriptions 5 CRL Configuration Register Loaded. Status flag that indicates if the configuration register has been loaded. The configuration register initializes the flash controllers clock configuration register to generate a divided down clock from the system clock that runs at a frequency of 150 kHz to 200 kHz. This register must be initialized before any erase or program commands are accepted.
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EzPort Table 19-4. EzPort Configuration Register Field Description Field 7 — Descriptions Reserved, should be cleared. 6 PRDIV Enables prescaler divide by 8. 0 The system clock is fed directly into the divider. 1 Enables a prescaler that divides the system clock by 8 before it enters the divider. 5–0 DIV[5:0] Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the system clock down to a frequency between 150 kHz and 200 kHz. 19.4.1.
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EzPort 19.4.1.8 Sector Erase The Sector Erase command erases the contents of a 2-Kbyte space of flash memory. The 3-byte address sent after the command byte can be any address within the space to erase. This command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set, or the configuration register has not been written. This command is not accepted if flash security is enabled.
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EzPort 19.6 Initialization/Application Information Prior to issuing any program or erase commands, the clock configuration register must be written to set the flash state machine clock (FCLK). The flash controller module runs at the system clock frequency divide by 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0] bits in the clock configuration register. 1. If fSYS is greater than 25.
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Chapter 20 Programmable Interrupt Timers (PIT0–PIT1) 20.1 Introduction This chapter describes the operation of the two programmable interrupt timer modules: PIT0–PIT1. 20.1.1 Overview Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can count down from the value written in the modulus register or it can be a free-running down-counter. 20.1.
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Programmable Interrupt Timers (PIT0–PIT1) NOTE The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. Table 20-1. PIT Module Operation in Low-power Modes Low-power Mode PIT Operation Wait Normal Doze Mode Exit N/A Normal if PCSRn[DOZE] cleared, Any interrupt at or above level in LPICR, exit doze stopped otherwise mode if PCSRn[DOZE] is set.
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Programmable Interrupt Timers (PIT0–PIT1) 2 User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 20.2.1 PIT Control and Status Register (PCSRn) The PCSRn registers configure the corresponding timer’s operation.
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Programmable Interrupt Timers (PIT0–PIT1) Table 20-3. PCSRn Field Descriptions (continued) Field Description 5 DBG Debug mode bit. Controls the function of PIT in halted/debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.
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Programmable Interrupt Timers (PIT0–PIT1) Table 20-4. PMRn Field Descriptions Field Description 15–0 PM Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the counter. Reading this field returns the value written. 20.2.3 PIT Count Register (PCNTRn) The 16-bit, read-only PCNTRn contains the counter value.
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Programmable Interrupt Timers (PIT0–PIT1) PIT CLOCK COUNTER 0x0002 0x0001 MODULUS 0x0000 0x0005 0x0005 PIF Figure 20-5. Counter Reloading from the Modulus Latch 20.3.2 Free-Running Timer Operation This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement. When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set.
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Programmable Interrupt Timers (PIT0–PIT1) The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 21 General Purpose Timer Module (GPT) 21.1 Introduction This device has one 4-channel general purpose timer module (GPT). It consists of a 16-bit counter driven by a 7-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
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General Purpose Timer Module (GPT) 21.3 Block Diagram CLK[1:0] System Clock SYNCx Pin PR[2:0] PACLK PACLK/256 PACLK/65536 Divide by 2 MUX Channel 3 Output Compare X Prescaler TCRE CxI GPTCNTH:GPTCNTL CxF Clear Counter 16-Bit Counter TOF Interrupt Logic TOI TE Interrupt Request Channel 0 16-Bit Comparator Edge Detect C0F IOS0 CH. 0 Capture PT0 LOGIC GPTC0H:GPTC0L 16-Bit Latch EDG0A OM:OL0 EDG0B TOV0 CH. 0 Compare GPTx0 Pin CHANNEL 1 16-Bit Comparator Edge Detect C1F IOS1 CH.
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General Purpose Timer Module (GPT) 21.4 Low-Power Mode Operation This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in Chapter 8, “Power Management.” Table 21-1 shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode. Table 21-1.
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General Purpose Timer Module (GPT) 21.5.3 SYNCn The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter. 21.6 Memory Map and Registers Table 21-3 shows the memory map of the GPT module. The base address for GPT is IPSBAR + 0x1A_0000. NOTE Reading reserved or unimplemented locations returns zeros. Writing to reserved or unimplemented locations has no effect. Table 21-3.
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General Purpose Timer Module (GPT) Table 21-3. GPT Memory Map (continued) IPSBAR Offset1 1 2 Width (bits) Register Access Reset Value Section/Page 0x1A_0017 GPT Channel 3 Register Low (GPTC3L)2 8 0x1A_0018 Pulse Accumulator Control Register (GPTPACTL) 8 R/W 0x00 21.6.15/21-13 0x1A_0019 Pulse Accumulator Flag Register (GPTPAFLG) 8 R/W 0x00 21.6.16/21-14 0x1A_001A Pulse Accumulator Counter Register High (GPTPACNTH)2 8 R/W 21.6.
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General Purpose Timer Module (GPT) 21.6.2 GPT Compare Force Register (GPCFORC) IPSBAR Offset: 0x1A_0001 (GPCFORC) R Access: Supervisor read/write 7 6 5 4 0 0 0 0 3 2 1 0 0 0 FOC W Reset: 0 0 0 0 0 0 Figure 21-3. GPT Input Compare Force Register (GPCFORC) Table 21-5. GPTCFORC Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 FOC Force output compare.Setting an FOC bit causes an immediate output compare on the corresponding channel.
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General Purpose Timer Module (GPT) Table 21-6. GPTOC3M Field Descriptions Field 7–4 Description Reserved, should be cleared. 3–0 OC3M Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write anytime.
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General Purpose Timer Module (GPT) Table 21-8. GPTCNT Field Descriptions Field Description 15–0 CNTR Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the prescaler clock.
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General Purpose Timer Module (GPT) Write GPTFLG1 Register Data Bit n CnF Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 21-8. Fast Clear Flag Logic 21.6.7 GPT Toggle-On-Overflow Register (GPTTOV) IPSBAR Offset: 0x1A_0008 (GPTTOV) R Access: Supervisor read/write 7 6 5 4 0 0 0 0 3 2 1 0 0 0 TOV W Reset: 0 0 0 0 0 0 Figure 21-9. GPT Toggle-On-Overflow Register (GPTTOV) Table 21-10.
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General Purpose Timer Module (GPT) Table 21-11. GPTCL1 Field Descriptions Field Description 7–0 Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each OMx/OLx channel. When OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. These bits are read anytime, write anytime.
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General Purpose Timer Module (GPT) Table 21-13. GPTIE Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 Cnl Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled 21.6.
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General Purpose Timer Module (GPT) Table 21-14. GPTSCR2 Field Descriptions (continued) Field Description 2–0 PR Prescaler bits. Select the prescaler divisor for the GPT counter.
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General Purpose Timer Module (GPT) Table 21-16. GPTFLG2 Field Descriptions Field Description 7 TOF Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect).
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General Purpose Timer Module (GPT) Table 21-18. GPTPACTL Field Descriptions Field 7 Description Reserved, should be cleared. 6 PAE Enables the pulse accumulator. 1 Pulse accumulator enabled 0 Pulse accumulator disabled Note: The pulse accumulator can operate in event mode even when the GPT enable bit, GPTEN, is clear. 5 Pulse accumulator mode. Selects event counter mode or gated time accumulation mode. PAMOD 1 Gated time accumulation mode 0 Event counter mode 4 Pulse accumulator edge.
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General Purpose Timer Module (GPT) Table 21-19. GPTPAFLG Field Descriptions Field 7–2 Description Reserved, should be cleared. 1 PAOVF Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the GPTPACTL[PAOVI] bit is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write anytime. (Writing 1 clears the flag; writing 0 has no effect.
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General Purpose Timer Module (GPT) 21.6.18 GPT Port Data Register (GPTPORT) IPSBAR Offset: 0x1A_001D (GPTPORT) R Access: Supervisor read/write 7 6 5 4 0 0 0 0 3 2 1 0 0 0 PORTT W Reset: 0 0 0 0 0 0 Figure 21-20. GPT Port Data Register (GPTPORT) Table 21-21. GPTPORT Field Descriptions Field 7–4 Description Reserved, should be cleared. 3–0 GPT port input capture/output compare data.
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General Purpose Timer Module (GPT) 21.7.1 Prescaler The prescaler divides the module clock by 1 or 16. The PR[2:0] bits in GPTSCR2 select the prescaler divisor. 21.7.2 Input Capture Clearing an I/O select bit (IOSn) configures channel n as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the GPT counter into the GPT channel registers (GPTCn).
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General Purpose Timer Module (GPT) 21.7.4 Pulse Accumulator The pulse accumulator (PA) is a 16-bit counter that can operate in two modes: 1. Event counter mode: counts edges of selected polarity on the pulse accumulator input pin, PAI 2. Gated time accumulation mode: counts pulses from a divide-by-64 clock The PA mode bit (PAMOD) selects the mode of operation. The minimum pulse width for the PAI input is greater than two module clocks. 21.7.
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General Purpose Timer Module (GPT) The PA counter register (GPTPACNT) reflects the number of pulses from the divide-by-64 clock since the last reset. NOTE The GPT prescaler generates the divide-by-64 clock. If the timer is not active, there is no divide-by-64 clock. PULSE ACCUMULATOR PAD CHANNEL 3 OUTPUT COMPARE OM3 OL3 OC3M3 Figure 21-22. Channel 3 Output Compare/Pulse Accumulator Logic 21.7.
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General Purpose Timer Module (GPT) Table 21-23. GPT Settings and Pin Functions GPTEN DDR1 GPTIOS 1 2 3 4 5 EDGx [B:A] Pin OMx/ 3 Data 2 OC3Mx OLx Dir. Pin Driven by Pin Function Digital input Comments 0 0 X4 X X X In Ext. 0 1 X X X X Out Data reg. 1 0 0 (IC) 0 (IC disabled) X 0 In Ext. 1 1 0 0 X 0 Out Data reg. 1 0 0 <> 0 X 0 In Ext. 1 1 0 <> 0 X 0 Out Data reg. 1 0 0 <> 0 X 1 In Ext. 1 1 0 <> 0 X 1 Out Data reg.
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General Purpose Timer Module (GPT) 6 A successful output compare on channel 3 causes an output value determined by OC3Dn value to temporarily override the output compare pin state of any other output compare channel.The next OC action for the specific channel continues to be output to the pin. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, depending on the output compare 3 mask register. 21.
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General Purpose Timer Module (GPT) 21.9.3 Pulse Accumulator Input (PAIF) PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to this flag.
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Chapter 22 DMA Timers (DTIM0–DTIM3) 22.1 Introduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included.
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DMA Timers (DTIM0–DTIM3) Figure 22-1 is a block diagram of one of the four identical timer modules.
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DMA Timers (DTIM0–DTIM3) Table 22-1. DMA Timer Module Memory Map IPSBAR Offset DMA Timer 0 DMA Timer 1 DMA Timer 2 DMA Timer 3 Width Access (bits) Register Reset Value Section/Page 0x00_0400 0x00_0440 0x00_0480 0x00_04C0 DMA Timer n Mode Register (DTMRn) 16 R/W 0x0000 22.2.1/22-3 0x00_0402 0x00_0442 0x00_0482 0x00_04C2 DMA Timer n Extended Mode Register (DTXMRn) 8 R/W 0x00 22.2.2/22-4 0x00_0403 0x00_0443 0x00_0483 0x00_04C3 DMA Timer n Event Register (DTERn) 8 R/W 0x00 22.2.
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DMA Timers (DTIM0–DTIM3) Table 22-2. DTMRn Field Descriptions Field Description 15–8 PS Prescaler value. The prescaler is programmed to divide the clock input (internal bus clock/(16 or 1) or clock on DTINn) by values from 1 (PS equals 0x00) to 256 (PS equals 0xFF). 7–6 CE Capture edge. 00 Disable capture event output 01 Capture on rising edge only 10 Capture on falling edge only 11 Capture on any edge 5 OM Output mode. 0 Active-low pulse for one internal bus clock cycle (-ns resolution at MHz).
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DMA Timers (DTIM0–DTIM3) Table 22-3. DTXMRn Field Descriptions Field Description 7 DMA request. Enables DMA request output on counter reference match or capture edge event. DMAEN 0 DMA request disabled 1 DMA request enabled 6 Controls the counter when the core is halted. This allows debug mode to be entered without timer interrupts affecting HALTED the debug flow. 0 Timer function is not affected by core halt. 1 Timer stops counting while the core is halted.
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DMA Timers (DTIM0–DTIM3) Table 22-4. DTERn Field Descriptions Field Description 7–2 Reserved, must be cleared. 1 REF Output reference event. The counter value, DTCNn, equals the reference value, DTRRn. Writing a 1 to REF clears the event condition. Writing a 0 has no effect. 0 CAP 22.2.4 REF DTMRn[ORRI] DTXMRn[DMAEN] 0 X X No event 1 0 0 No request asserted 1 0 1 No request asserted 1 1 0 Interrupt request asserted 1 1 1 DMA request asserted Capture event.
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DMA Timers (DTIM0–DTIM3) IPSBAR 0x00_0404 (DTRR0) Offset: 0x00_0444 (DTRR1) 0x00_0484 (DTRR2) 0x00_04C4 (DTRR3) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 REF (32-bit reference value) W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 22-5. DTRRn Registers Table 22-5.
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DMA Timers (DTIM0–DTIM3) IPSBAR 0x00_040C (DTCN0) Offset: 0x00_044C (DTCN1) 0x00_048C (DTCN2) 0x00_04CC (DTCN3) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 CNT (32-bit timer counter value count) W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-7. DMA Timer Counters (DTCNn) Table 22-7. DTCNn Field Descriptions Field 31–0 CNT 22.3 22.3.1 Description Timer counter.
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DMA Timers (DTIM0–DTIM3) 22.4 Initialization/Application Information The general-purpose timer modules typically, but not necessarily, follow this program order: • The DTMRn and DTXMRn registers are configured for the desired function and behavior.
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DMA Timers (DTIM0–DTIM3) move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 reference to be move.l #D0,TRR0 ;defined as 0xAFAF The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 move.b #0x03,D0 move.b D0,TER0 move.w TMR0,D0 bset #0,D0 move.
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Chapter 23 Queued Serial Peripheral Interface (QSPI) 23.1 Introduction This chapter describes the queued serial peripheral interface (QSPI) module. After the feature set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram. 23.1.1 Block Diagram Figure 23-1 illustrates the QSPI module.
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Queued Serial Peripheral Interface (QSPI) 23.1.2 Overview The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.
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Queued Serial Peripheral Interface (QSPI) Table 23-1. QSPI Input and Output Signals and Functions Signal Name 23.3 Hi-Z or Actively Driven Function QSPI Data Output (QSPI_DOUT) Configurable Serial data output from QSPI QSPI Data Input (QSPI_DIN) N/A Serial data input to QSPI Serial Clock (QSPI_CLK) Actively driven Clock output from QSPI Peripheral Chip Selects (QSPI_CSn) Actively driven Peripheral selects Memory Map/Register Definition Table 23-2 is the QSPI register memory map.
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Queued Serial Peripheral Interface (QSPI) Table 23-3. QMR Field Descriptions Field Description 15 MSTR Master mode enable. 0 Reserved, do not use. 1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly. 14 DOHIE Data output high impedance enable. Selects QSPI_DOUT mode of operation. 0 Default value after reset. QSPI_DOUT is actively driven between transfers. 1 QSPI_DOUT is high impedance between transfers. 13–10 BITS Transfer size.
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Queued Serial Peripheral Interface (QSPI) Figure 23-3 shows an example of a QSPI clocking and data transfer. QSPI_CLK QSPI_DOUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb QSPI_DIN 15 A B QSPI_CS QMR[CPOL] = 0 QMR[CPHA] = 1 QCR[CONT] = 0 Chip selects are active low A = QDLYR[QCD] B = QDLYR[DTL] Figure 23-3. QSPI Clocking and Data Transfer Example 23.3.
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Queued Serial Peripheral Interface (QSPI) 23.3.3 QSPI Wrap Register (QWR) The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations. IPSBAR 0x00_0348 (QWR) Offset: 15 R W Reset 14 Access: User read/write 13 12 11 10 HALT WREN WRTO CSIV 0 0 0 0 9 8 7 6 ENDQP 0 0 5 4 3 CPTQP 0 0 0 0 2 1 0 NEWQP 0 0 0 0 0 0 Figure 23-5. QSPI Wrap Register (QWR) Table 23-5. QWR Field Descriptions Field Description 15 HALT Halt transfers.
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Queued Serial Peripheral Interface (QSPI) Table 23-6. QIR Field Descriptions Field Description 15 Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing WCEFB the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error. 14 ABRTB 13 12 ABRTL Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer.
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Queued Serial Peripheral Interface (QSPI) IPSBAR 0x00_0350 (QAR) Offset: R Access: User read/write 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 1 0 0 0 ADDR W Reset 2 0 0 0 0 Figure 23-7. QSPI Address Register (QAR) Table 23-7. QAR Field Descriptions Field Description 15–6 Reserved, should be cleared. 5–0 ADDR 23.3.6 Address used to read/write the QSPI RAM.
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Queued Serial Peripheral Interface (QSPI) NOTE The command RAM is accessed only using the most significant byte of QDR and indirect addressing based on QAR[ADDR]. Address: QAR[ADDR] 15 14 Access: CPU write-only 13 12 DT DSCK — — 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 — — — — — — — — R W CONT BITSE Reset — — QSPI_CS — — — — Figure 23-9. Command RAM Registers (QCR0–QCR15) Table 23-9. QCR0–QCR15 Field Descriptions Field Description 15 CONT Continuous.
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Queued Serial Peripheral Interface (QSPI) The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF). NOTE Throughout ColdFire documentation, the term word is used to designate a 16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units.
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Queued Serial Peripheral Interface (QSPI) 23.4.1 QSPI RAM The QSPI contains an 80-byte block of static RAM that can be accessed by the user and the QSPI. This RAM does not appear in the device memory map, because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
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Queued Serial Peripheral Interface (QSPI) stored in the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry. QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. 23.4.1.2 Transmit RAM Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.
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Queued Serial Peripheral Interface (QSPI) The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: f sys QMR[BAUD] = ----------------------------------------------------------------------------------2 × [desired QSPI_CLK baud rate] Eqn. 23-1 Table 23-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate Internal Bus Clock = MHz 23.4.3 QMR [BAUD] QSPI_CLK 2 16.5 MHz 4 8.25 MHz 8 4.1 MHz 16 2.06 MHz 32 1.0 MHz 255 12.
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Queued Serial Peripheral Interface (QSPI) where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of 8192/fsys. Standard delay period (DT = 0) is calculated by the following: 17 Standard delay after transfer = ------f sys Eqn. 23-4 (DT = 0) Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer.
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Queued Serial Peripheral Interface (QSPI) QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE]. There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting QWR[HALT].
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Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 24 UART Modules 24.1 Introduction This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples. NOTE The designation n appears throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0, UART1, or UART2. 24.1.1 Overview The internal bus clock can clock each of the three independent UARTs, eliminating the need for an external UART clock.
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UART Modules NOTE The DTINn pin can clock UARTn. However, if the timers are used, input capture mode is not available for that timer. The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits.
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UART Modules 24.2 External Signal Description Table 24-1 briefly describes the UART module signals. Table 24-1. UART Module Signals Signal Description UTXDn Transmitter Serial Data Output. UTXDn is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on UTXDn on the falling edge of the clock source, with the least significant bit (lsb) sent first. URXDn Receiver Serial Data Input.
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UART Modules Table 24-2. UART Module Memory Map IPSBAR Offset UART0 UART1 UART2 Register Width Access Reset Value Section/Page (bit) 0x00_0200 0x00_0240 0x00_0280 UART Mode Registers1 (UMR1n), (UMR2n) 8 R/W 0x00 24.3.1/24-5 24.3.2/24-6 0x00_0204 0x00_0244 0x00_0284 UART Status Register (USRn) 8 R 0x00 24.3.3/24-7 UART Clock Select Register (UCSRn) 8 W See Section 24.3.4/24-9 0x00_0208 0x00_0248 0x00_0288 UART Command Registers (UCRn) 8 W 0x00 24.3.
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UART Modules 24.3.1 UART Mode Registers 1 (UMR1n) The UMR1n registers control configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
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UART Modules Table 24-3. UMR1n Field Descriptions (continued) Field 2 PT Description Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11). 1–0 B/C PM Parity Mode Parity Type (PT= 0) Parity Type (PT= 1) 00 With parity Even parity Odd parity 01 Force parity Low parity High parity 10 No parity 11 Multidrop mode N/A Data character Address character Bits per character.
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UART Modules Table 24-4. UMR2n Field Descriptions Field 7–6 CM Description Channel mode. Selects a channel mode. Section 24.4.3, “Looping Modes,” describes individual modes. 00 Normal 01 Automatic echo 10 Local loopback 11 Remote loopback 5 TXRTS Transmitter ready-to-send. Controls negation of URTSn to automatically terminate a message transmission. Attempting to program a receiver and transmitter in the same UART for URTSn control is not permitted and disables URTSn control for both.
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UART Modules IPSBAR 0x00_0204 (USR0) Offset: 0x00_0244 (USR1) 0x00_0284 (USR2) R Access: User read-only 7 6 5 4 3 2 1 0 RB FE PE OE TXEMP TXRDY FFULL RXRDY 0 0 0 0 0 0 0 0 W Reset: Figure 24-5. UART Status Registers (USRn) Table 24-5. USRn Field Descriptions Field Description 7 RB Received break. The received break circuit detects breaks originating in the middle of a received character.
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UART Modules Table 24-5. USRn Field Descriptions (continued) Field Description 1 FFULL FIFO full. 0 The FIFO is not full but may hold up to two unread characters. 1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost. 0 RXRDY Receiver ready. 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read. 1 One or more characters were received and are waiting in the receive buffer FIFO. 24.3.
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UART Modules IPSBAR 0x00_0208 (UCR0) Offset: 0x00_0248 (UCR1) 0x00_0288 (UCR2) 7 Access: User write-only 6 5 4 3 2 1 0 R W 0 Reset: 0 MISC 0 0 TC 0 0 RC 0 0 0 Figure 24-7. UART Command Registers (UCRn) Table 24-7 describes UCRn fields and commands. Examples in Section 24.4.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. Table 24-7. UCRn Field Descriptions Field 7 6–4 MISC Description Reserved, must be cleared.
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UART Modules Table 24-7. UCRn Field Descriptions (continued) Field 3–2 TC Description TC Field (This field selects a single command) Command 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 TRANSMITTER Enables operation of the UART’s transmitter. USRn[TXEMP,TXRDY] are set. If the transmitter is already enabled, this command has no effect.
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UART Modules IPSBAR 0x00_020C (URB0) Offset: 0x00_024C (URB1) 0x00_028C (URB2) 7 6 Access: User read-only 5 4 R 3 2 1 0 1 1 1 1 RB W Reset: 1 1 1 1 Figure 24-8. UART Receive Buffer (URBn) 24.3.7 UART Transmit Buffers (UTBn) The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USRn[TXRDY] is set.
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UART Modules Table 24-8. UIPCRn Field Descriptions Field Description 7–5 Reserved 4 COS Change of state (high-to-low or low-to-high transition). 0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS]. 1 A change-of-state longer than 25–50 μs occurred on the UCTSn input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected. 3–1 Reserved 0 CTS Current state of clear-to-send.
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UART Modules NOTE True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. IPSBAR 0x00_0214 (UISR0) Offset: 0x00_0254 (UISR1) 0x00_0294 (UISR2) Access: User read/write 7 6 5 4 3 2 1 0 R (UISRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY W (UIMRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY 0 0 0 0 0 0 0 0 Reset: Figure 24-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn) Table 24-10.
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UART Modules 24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation, as described in Section 24.4.1.2.1, “Internal Bus Clock Baud Rates.
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UART Modules Table 24-11. UIPn Field Descriptions Field Description 7–1 Reserved 0 CTS Current state of clear-to-send. The UCTSn value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as UIPCRn[RTS]. 0 The current state of the UCTSn input is logic 0. 1 The current state of the UCTSn input is logic 1. 24.3.
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UART Modules 24.4.1.1 Programmable Divider As Figure 24-17 shows, the UARTn transmitter and receiver can use the following clock sources: • An external clock signal on the DTINn pin. When not divided, DTINn provides a synchronous clock; when divided by 16, it is asynchronous. • The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by the 16-bit value programmed in UBG1n and UBG2n. See Section 24.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).
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UART Modules Using a 66-MHz internal bus clock and letting baud rate equal 9600, then 66MHz Divider = ------------------------------- = 215 ( decimal ) = 0x00D6 ( hexadecimal ) [ 32 x 9600 ] Eqn. 24-2 Therefore, UBG1n equals 0x00 and UBG2n equals 0xD6. 24.4.1.2.2 External Clock An external source clock (DTINn) passes through a divide-by-1 or 16 prescaler. If fextc is the external clock frequency, baud rate can be described with this equation: f extc Baudrate = -------------------(16 or 1) 24.4.2 Eqn.
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UART Modules optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer (UTBn).
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UART Modules C1 in transmission C11 UTXDn C2 C3 C4 Break C6 Transmitter Enabled USRn[TXRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 UCTSn3 URTSn4 Manually asserted Manually asserted by BIT-SET command 1 Cn = transmit characters 2 W = write 3 UMR2n[TXCTS] = 1 4 UMR2n[TXRTS] = 1 Figure 24-19. Transmitter Timing Diagram 24.4.2.2 Receiver The receiver is enabled through its UCRn, as described in Section 24.3.
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UART Modules framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USRn at the received character boundary. They are valid only if USRn[RXRDY] is set. If a break condition is detected (URXDn is low for the entire character including the stop bit), a character of all 0s loads into the receiver holding register and USRn[RB,RXRDY] are set.
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UART Modules programming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block modes. USRn[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO.
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UART Modules 24.4.3.1 Automatic Echo Mode In automatic echo mode, shown in Figure 24-21, the UART automatically resends received data bit by bit. The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on UTXDn. The receiver must be enabled, but the transmitter need not be. URXDn Input Rx CPU Disabled Tx Disabled UTXDn Output Figure 24-21.
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UART Modules Disabled Rx Disabled URXDn Input Disabled UTXDn Output CPU Disabled Tx Figure 24-23. Remote Loopback 24.4.4 Multidrop Mode Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations. Although slave stations have their receivers disabled, they continuously monitor the master’s data stream.
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UART Modules Master Station A/D UTXDn ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled USRn[TXRDY] internal module select UMR1n[PM] = 11 ADD 1 C0 UMR1n[PT] = 1 UMR1n[PT] = 0 ADD 2 UMR1n[PT] = 1 Peripheral Station URXDn A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled USRn[RXRDY] internal module select UMR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 24-24.
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UART Modules 24.4.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 24.4.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 24.4.5.2 Write Cycles The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers complete normally without an error termination, but data is ignored. 24.
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UART Modules 3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts. 4. If TXRDY or RXRDY generates interrupt requests, verify that DMAREQC (in the SCM) does not also assign the UART’s TXRDY and RXRDY into DMA channels. 5. Initialize interrupts in the UART, see Table 24-13. Table 24-13. UART Interrupts 24.5.1.
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UART Modules To configure the UART for DMA requests: 1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA channels. For example, setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to DMA channel 1, setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA channel 2, and so on. It is possible to independently map transmit based and receive based UART DMA requests in the DMAREQC. 2. Disable interrupts using the UIMR register.
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UART Modules b) If preferred, program operation of transmitter ready-to-send (TXRTS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCRn: Enable transmitter and/or receiver. Enable Serial Module Any Errors? Y SINIT N Initiate: Channel Interrupts Enable Receiver CHK1 Assert Request To Send Call CHCHK SINITR Save Channel Status Return Figure 24-25.
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UART Modules CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK N Is Transmitter Ready? N Waited Too Long? Y Set TransmitterNever-ready Flag Y Set ReceiverNever-ready Flag Y SNDCHR Send Character To Transmitter RxCHK N Has Character Been Received? N Waited Too Long? Y B A Figure 24-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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UART Modules A B FRCHK RSTCHN Have Framing Error? N Disable Transmitter Restore To Original Mode Set Framing Error Flag PRCHK Have Parity Error? N Return Y Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Y N Set Incorrect Character Flag B Figure 24-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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UART Modules SIRQ INCH ABRKI Was IRQ Caused By Beginning Of A Break? N Y Does Channel A Receiver Have A Character? N Y Clear Change-inBreak Status Bit Place Character In D0 ABRKI1 Has End-of-break IRQ Arrived Yet? N Return Y Clear Change-inBreak Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR RTE Figure 24-25.
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UART Modules OUTCH Is Transmitter Ready? N Y Send Character To Transmitter Return Figure 24-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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UART Modules MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 25 I2C Interface 25.1 Introduction This chapter describes the I2C module, clock synchronization, and I2C programming model registers. It also provides extensive programming examples. NOTE The MCF52211 contains two I C modules, I2C0 and I2C1. The designation ‘n’, with n = 0 or 1, is used throughout this chapter to refer to registers associated with one of the two identical I2C modules. 2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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I2C Interface 25.1.1 Block Diagram Figure 25-1 is a block diagram of the I2C module. Internal Bus IRQ Address Data Address Decode Data MUX I2C Data I/O Register (I2DR) I2C Address Register (IADR) Registers and Slave Interface I2C Frequency Divider Register (IFDR) I2C Control Register (I2CR) I2C Status Register (I2SR) Clock Control Start, Stop, and Arbitration Control Input Sync In/Out Data Shift Register Address Compare SCL SDA Figure 25-1.
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I2C Interface The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus loading. The maximum communication length and the number of devices connected are limited by a maximum bus capacitance of 400 pF.
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I2C Interface Table 25-1. I2C Module Memory Map IPSBAR Offset Register I2C0 I2C1 Access Reset Value Section/Page 0x0300 0x0380 I2C Address Registers (I2ADRn) R/W 0x00 25.2.1/25-4 0x0304 0x0384 I2C Frequency Divider Registers (I2FDRn) R/W 0x00 25.2.2/25-4 0x0308 0x0388 I2C Control Registers (I2CRn) R/W 0x00 25.2.3/25-5 0x030C 0x038C I2C Status Registers (I2SRn) R/W 0x81 25.2.4/25-7 0x0310 0x0390 I2C Data I/O Registers (I2DRn) R/W 0x00 25.2.
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I2C Interface IPSBAR 0x0304 (I2FDR0) Offset: 0x0384 (I2FDR1) R Access: User read/write 7 6 0 0 5 4 3 2 1 0 0 0 0 IC W Reset: 0 0 0 0 0 Figure 25-3. I2FDRn Registers Table 25-3. I2FDRn Field Descriptions Field Description 7–6 Reserved, must be cleared. 5–0 IC I2C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below.
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I2C Interface IPSBAR 0x0308 (I2CR0) Offset: 0x0388 (I2CR1) Access: User read/write 7 6 5 4 3 2 IEN IIEN MSTA MTX TXAK RSTA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset: Figure 25-4. I2CRn Registers Table 25-4. I2CRn Field Descriptions Field Description 7 IEN I2C enable. Controls the software reset of the entire I2C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.
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I2C Interface I2C Status Registers (I2SRn) 25.2.4 The I2SRn contain bits that indicate transaction direction and status. IPSBAR 0x030C (I2SR0) Offset: 0x038C (I2SR1) R Access: User read/write 7 6 5 ICF IAAS IBB 4 3 2 0 SRW IAL 1 0 RXAK IIF W Reset: 1 0 0 0 0 0 0 1 Figure 25-5. I2SRn Registers Table 25-5. I2SRn Field Descriptions Field 7 ICF 6 IAAS Description I2C Data transferring bit. While one byte of data is transferred, ICF is cleared.
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I2C Interface I2C Data I/O Registers (I2DRn) 25.2.5 In master-receive mode, reading the I2DRns allows a read to occur and for the next data byte to be received. In slave mode, the same function is available after the I2C has received its slave address. IPSBAR 0x0310 (I2DR0) Offset: 0x0390 (I2DR1) 7 Access: User read/write 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset: 0 0 0 0 Figure 25-6. I2DRn Registers Table 25-6. I2DRn Field Description Field Description 7–0 DATA I2C data.
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I2C Interface Interrupt bit set (Byte complete) msb SCL lsb 1 SDA 2 3 4 5 6 7 msb 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W A SCL held low while Interrupt is serviced Calling Address START Signal XXX B C 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte ACK Bit R/W lsb 1 No ACK Bit E D STOP Signal F 2 Figure 25-7. I C Standard Communication Protocol 25.3.2 Slave Address Transmission The master sends the slave address in the first byte after the START signal (B).
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I2C Interface 25.3.4 Acknowledge The transmitter releases the SDA line high during the acknowledge clock pulse as shown in Figure 25-9. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of the clock pulse. If it does not acknowledge the master, the slave receiver must leave SDA high.
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I2C Interface msb SCL lsb 1 SDA 2 3 4 5 6 7 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Calling Address START Signal lsb msb 8 R/W ACK Bit 1 XX 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W New Calling Address Repeated START Signal A R/W No ACK Bit STOP Signal Figure 25-10. Repeated START Various combinations of read/write formats are then possible: • The first example in Figure 25-11 is the case of master-transmitter transmitting to slave-receiver.
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I2C Interface 25.3.7 Clock Synchronization and Arbitration I2C is a true multi-master bus that allows more than one master connected to it. If two or more master devices simultaneously request control of the bus, a clock synchronization procedure determines the bus clock. Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus.
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I2C Interface 25.3.8 Handshaking and Clock Stretching The clock synchronization mechanism can acts as a handshake in data transfers. Slave devices can hold SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases SCL. Slaves may also slow down the transfer bit rate. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it.
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I2C Interface may need to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions. The following example signals START and transmits the first byte of data (slave address): 1. Check I2SR[IBB]. If it is set, wait until it is clear. 2. After cleared, set to transmit mode by setting I2CR[MTX]. 3. Set master mode by setting I2CR[MSTA]. This generates a START condition. 4. Transmit the calling address via the I2DR. 5. Check I2SR[IBB].
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I2C Interface For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example. 1. Decrement RXCNT. 2. If last byte (RXCNT = 0) go to step #4. 3. If next to last byte (RXCNT = 1), set I2CR[TXAK] to disable ACK and go to step #5. 4.
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I2C Interface Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? N Last Byte Transmitted ? N RXAK= 0 ? Clear IAL Y Last Byte to be Read ? N Y Y N End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR N Y Y (Read)Y N Data Cycle SRW=1 ? Generate STOP Signal Switch to Rx Mode Generate STOP Signal Tx/Rx ? N (WRITE) N Y Set TX Mode Write Data to I2DR Dummy Read from I2DR IAAS=1 ? Address Y Cycle 2nd Last Byte to be Read? Set TXAK =1 Y IAAS=1 ? Read Data from
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Chapter 26 Analog-to-Digital Converter (ADC) 26.1 Introduction The analog-to-digital converter (ADC) consists of two separate and complete ADCs, each with their own sample and hold circuits. The converters share a common voltage reference and common digital control module. 26.2 Features The ADC’s characteristics include the following: • 12-bit resolution • Maximum ADC clock frequency of 5.0 MHz, 200 ns period • Sampling rate up to 1.66 million samples per second1 • Single conversion time of 8.
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Analog-to-Digital Converter (ADC) 26.3 Block Diagram The ADC function, shown in Figure 26-1, consists of two four-channel input select functions, interfacing with two independent Sample and Hold (S/H) circuits, which feed two 12-bit ADCs. The two converters store their results in a buffer, awaiting further processing.
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Analog-to-Digital Converter (ADC) Table 26-1. ADC Register Summary (continued) IPSBAR Offset1 1 Width (bits) Register Access Reset Value Section/Page 0x19_0032–40 High Limit Registers 0-7 (ADHLMT0-7) 16 R/W 0x0000 26.4.10/26-15 0x19_0042–50 Offset Registers 0-7 (ADOFS0-7) 16 R/W 0x0000 26.4.11/26-17 0x19_0052 Power Control Register (POWER) 16 R/W 0x00D7 26.4.12/26-17 0x19_0054 Voltage Reference Register (CAL) 16 R/W 0x0000 26.4.
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Analog-to-Digital Converter (ADC) Table 26-2. CTRL1 Field Descriptions (continued) Field Description 12 SYNC0 Synchronization 0 Enable bit. When this bit is set, a conversion may be initiated by asserting a positive edge on the SYNC0 input. Any subsequent SYNC0 input pulses that occur during the scan are ignored. In once sequential and once parallel scan modes, only the first SYNC0 input pulse is honored. Subsequent SYNC0 input pulses are ignored until SYNC0 input is re-armed by setting SYNC0.
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Analog-to-Digital Converter (ADC) Table 26-2. CTRL1 Field Descriptions (continued) Field Description 7–4 CHNCFG Channel Configure. This field configures the inputs for single-ended or differential conversions: CHNCFG Inputs Description xxx1 AN0–AN1 Configured as differential pair (AN0 is + and AN1 is –) xxx0 Both configured as single ended inputs xx1x AN2–AN3 xx0x Both configured as single ended inputs x1xx AN4–AN5 x0xx AN6–AN7 0xxx 26.4.
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Analog-to-Digital Converter (ADC) Table 26-3. CTRL2 Field Descriptions Under Sequential Scan Modes Field Description 15–5 Reserved, should be cleared. 4–0 DIV Clock Divisor Select. This field controls the divider circuit, which generates the ADC clock by dividing the system clock by 2×DIV+1. DIV must be chosen so the ADC clock does not exceed 5.0 MHz. See Table 26-5 for a listing of ADC clock frequency based on the value of DIV for several configurations. 26.4.2.
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Analog-to-Digital Converter (ADC) Table 26-4. CTRL2 Field Descriptions Under Parallel Scan Modes (continued) Field Description 12 SYNC1 Synchronization 1 Enable bit. In parallel-scan modes when SIMULT equaling 0, setting SYNC1 allows a conversion to be initiated by asserting a positive edge on the SYNC1 input. Any subsequent SYNC1 input pulses that occur during the scan are ignored. In once sequential and once parallel scan modes, only the first SYNC1 input pulse is honored.
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Analog-to-Digital Converter (ADC) Table 26-5. ADC Clock Frequency for Various Conversion Clock Sources (continued) — — — — — — 11111 64 100 kHz 62.5 kHz 500 kHz CLK/128 26.4.3 Zero Crossing Control Register (ADZCC) The ADC zero crossing control (ADZCC) register provides the ability to monitor the selected channels and determine the direction of zero crossing triggering the optional interrupt. Zero crossing logic monitors only the sign change between current and previous sample.
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Analog-to-Digital Converter (ADC) SAMPLE4-7 should only contain binary values between 100 and 111. No damage occurs if this constraint is violated, but results are undefined. When inputs are configured as differential pairs, a reference to either analog input in a differential pair by a sample slot implies a differential measurement on the pair. The details of single ended and differential measurement are described in Section 26.5.2.1, “Single-Ended Samples” and Section 26.5.2.2, “Differential Samples”.
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Analog-to-Digital Converter (ADC) Table 26-8. ADLST2 Field Descriptions Field 15 Description Reserved, should be cleared. 14–12 SAMPLE7 11 Sample input channel select 7. The settings for this field are given in Table 26-9. Reserved, should be cleared. 10–8 SAMPLE6 7 Sample input channel select 6. The settings for this field are given in Table 26-9. Reserved, should be cleared. 6–4 SAMPLE5 3 Sample input channel select 5. The settings for this field are given in Table 26-9.
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Analog-to-Digital Converter (ADC) IPSBAR Offset: 0x19_000A (ADSDIS) R Access: read/write 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 7 6 5 4 3 2 1 0 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 0 0 0 0 0 0 0 0 Figure 26-8. Sample Disable Register (ADSDIS) Table 26-10. ADSDIS Field Descriptions Field Description 15–8 Reserved, should be cleared. 7–0 DSn Disable Sample bits.
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Analog-to-Digital Converter (ADC) Table 26-11. ADSTAT Field Descriptions Field Description 15 CIP0 Conversion in Progress 0 bit. This bit indicates when a scan is in progress. This bit supports any sequential scan or parallel scan with SIMULT equaling 1. When executing a parallel scan with SIMULT equaling 0, this bit services the scan of converter A, and the CIP1 bit services the scan of converter B.
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Analog-to-Digital Converter (ADC) Table 26-11. ADSTAT Field Descriptions (continued) Field Description 8 HLMTI High Limit Interrupt bit. If any high limit register (ADHLMTn) is enabled by having a value other than 0x7FF8, high limit checking is enabled. This bit is set at the completion of an individual conversion which may or may not be the end of a scan. It is cleared by writing 1 to all active ADLSTAT[HLS] bits.
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Analog-to-Digital Converter (ADC) 26.4.8 Zero Crossing Status Register (ADZCSTAT) The ADC zero crossing status (ADZCSTAT) register latches in the result of a sign comparison between the current and previous sample. The type of comparison is controlled by the ADZCC register (see Section 26.4.3, “Zero Crossing Control Register (ADZCC)”).
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Analog-to-Digital Converter (ADC) Negative results (SEXT = 1) are always presented in twos-complement format. If an application requires that the result be always positive, the corresponding offset register (ADOFSn) must be set to 0x0. The interpretation of the numbers programmed into the ADC limit and offset registers (ADLLMTn, ADHLMTn, and ADOFSn) must match your interpretation of the result register.
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Analog-to-Digital Converter (ADC) IPSBAR 0x19_0022 (ADLLMT0) Offsets: ox19_0024 (ADLLMT1) 0x19_0026 (ADLLMT2) 0x19_0028 (ADLLMT3) 0x19_002A (ADLLMT4) 0x19_002C (ADLLMT5) 0x19_002E (ADLLMT6) 0x19_0030 (ADLLMT7) 15 R 14 13 Access: read/write 12 11 10 9 0 0 7 6 5 4 3 LLMT W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 Figure 26-13. Low Limit Registers (ADLLMTn) Table 26-15. ADLLMTn Field Descriptions Field Description 15 Reserved, should be cleared.
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Analog-to-Digital Converter (ADC) 26.4.11 Offset Registers (ADOFSn) The values in the offset registers (ADOFSn) are subtracted from the raw ADC values, and the results are stored in the ADRSLTn registers. To obtain unsigned results, the respective offset register must be programmed with a value of 0x0 to yield a resulting range of 0x0 to 0x7FF8.
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Analog-to-Digital Converter (ADC) 5. Current mode • Normal current mode is used to power the converters at clock rates above 100 kHz. • Standby current mode uses less power and is engaged only when the ADC clock is at 100 kHz. The current mode active does not affect the number of ADC clock cycles required to do a conversion or the accuracy of a conversion. The ADC module may change the current mode when idle as part of the power saving strategy. Both converters are in the same current mode at all times.
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Analog-to-Digital Converter (ADC) Table 26-18. POWER Field Descriptions (continued) Field Description 10 PSTS0 Converter A Power Status bit. This bit is asserted immediately after PD0 is set. It is deasserted PUDELAY ADC clock cycles after PD0 is cleared if APD is 0. This bit can be read as a status bit to determine when the ADC is ready for operation. During auto power-down mode, this bit indicates the current powered state of converter A.
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Analog-to-Digital Converter (ADC) Table 26-18. POWER Field Descriptions (continued) Field Description 1 PD1 Manual Power-Down for Converter B bit. This bit forces Converter B to power-down. Setting PD1 powers-down converter B immediately. The results of a scan using converter B is invalid when PD1 is set. When PD1 is cleared, converter B is continuously powered-up (APD = 0) or automatically powered-up when needed (APD = 1).
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Analog-to-Digital Converter (ADC) 26.5 Functional Description The ADC’s conversion process is initiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a STARTn bit. Starting a single conversion actually begins a sequence of conversions, or a scan of up to 8 single-ended or differential samples one at a time in sequential scan mode. The operation of the module in sequential scan mode is shown in Figure 26-18.
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Analog-to-Digital Converter (ADC) Parallel scan can be simultaneous or non-simultaneous. During simultaneous scan, the scans in the two converters are done simultaneously and always result in simultaneous pairs of conversions, one by converter A and one by converter B. The two converters share the same start, stop, sync, end-of-scan interrupt enable control, and interrupt. Scanning in both converters is terminated when either converter encounters a disabled sample.
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Analog-to-Digital Converter (ADC) Optional interrupts can be generated at the end of a scan sequence. Interrupts are available simply to indicate the scan ended, that a sample was out of range, or at several different zero crossing conditions. Out-of-range is determined by the high and low limit registers. To understand the operation of the ADC, it is important to understand the features and limitations of each of the functional parts. 26.5.
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Analog-to-Digital Converter (ADC) Table 26-20. Analog MUX Controls for Each Conversion Mode (continued) Conversion Mode Channel Select Switches Single Ended Differential Switches Parallel, Single Ended The two 1-of-4 select muxes can be set for the appropriate input line. The lower switch selects VREFL for the V- input of the A/D. The upper switch is always closed so that any of the four inputs can get to the V+ A/D input.
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Analog-to-Digital Converter (ADC) 26.5.2 ADC Sample Conversion The ADC consists of a cyclic, algorithmic architecture using two recursive sub-ranging sections (RSD#1 and RSD#2), shown in Figure 26-21. Each sub-ranging section resolves a single bit for each conversion clock, resulting in an overall conversion rate of two bits per clock cycle. Each sub-ranging section is designed to run at a maximum clock speed of 5.0 MHz. Thus a complete 12-bit conversion takes 6 ADC clocks (1.
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Analog-to-Digital Converter (ADC) 26.5.2.1 Single-Ended Samples The ADC module performs a ratio metric conversion.
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Analog-to-Digital Converter (ADC) VREFH Potential AN+ + – AN– Differential buffer centers about mid-point AN+ NOTE: Normally, VREFL is set to VSSA = 0V AN– VREF/2 Center tap held at (VREFH + VREFL) /2 Figure 26-22. Typical Connections for Differential Measurements 26.5.3 ADC Data Processing As shown in Figure 26-23, the raw result of the ADC conversion process is sent to an adder for offset correction.
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Analog-to-Digital Converter (ADC) ADHLMT[0:3] > End of Scan A Interrupt ADLLMT[0:3] Test Data (From CPU) < Zero Crossing Logic 12 V+ ADCA 12 12 + + 13 ADRSLT[0:3] – IRQ Logic V– ADOFS[0:3] ADHLMT[4:7] > ADLLMT[4:7] < ADC0 ADC1 ADC2 Zero Crossing or Error Limit Interrupt End of Scan B Interrupt Zero Crossing Logic V+ V– ADCB 12 12 12 + + 13 ADRSLT[4:7] – ADOFS[4:7] Test Data (From CPU) Figure 26-23. Result Register Data Manipulation 26.5.4 Sequential vs.
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Analog-to-Digital Converter (ADC) bit is 1, when the SYNC0 input goes high. A scan ends when the first disabled sample slot is encountered in the SDIS register. Completion of the scan triggers the EOSI0 interrupt if the interrupt is enabled by the EOSIE0 bit. The START0 bit and SYNC0 input are ignored while a scan is in process. Scanning stops and cannot be initiated when the STOP0 bit is set.
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Analog-to-Digital Converter (ADC) completion of the previous scan. In loop parallel scan modes, both converters restart together if SIMULT equals 1 and restart independently if SIMULT equals 0. All subsequent start and sync pulses are ignored after the scan begins. Scanning can only be terminated by setting a STOPn bit. Use STOP0 in the CTRL1 register if operating in a sequential or simultaneous parallel mode.
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Analog-to-Digital Converter (ADC) Table 26-21. ADC Scan Modes Scan Mode Description Once sequential Upon START or an enabled sync signal, samples are taken one at a time starting with SAMPLE0 until a first disabled sample is encountered. If no disabled sample is encountered in the ADSDIS register, conversion concludes after SAMPLE7. If the scan is initiated by a sync signal, only one scan is completed until the converter is rearmed by writing to the CTRL1 register.
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Analog-to-Digital Converter (ADC) 26.5.7 Interrupt Sources Figure 26-24 illustrates how five interrupt sources are combined into three entries in the interrupt vector table. EOSI0 EOSIE0 ADCA Conversion Complete (ADC_CC0_INT) EOSI1 EOSIE1 ADCB Conversion Complete (ADC_CC1_INT) ZCI ZCIE LLMTI LLMTIE ADC Zero Crossing or Limit Error (ADC_ERR_INT) HLMTI HLTMIE Figure 26-24. ADC Interrupt Sources 26.5.8 Power Management The five supported power modes are described below.
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Analog-to-Digital Converter (ADC) PUDELAY ADC clock cycles execute at the start of all scans while the ADC engages the conversion clock and the ADC powers up, stabilizing in the standby current mode. This provides the lowest possible power configuration for ADC operation. 3.
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Analog-to-Digital Converter (ADC) When starting up in normal mode, first set PUDELAY to the large power-up value. Next, clear the PD0 and or PD1 bits to power-up the required converters. Poll the status bits (PSTSn in the POWER register) until all required converters are powered up. Following polling, start scan operations. The value in PUDELAY provides a power-up delay before scans begin. Because normal mode does not use PUDELAY at start of scans, no further delays are imposed.
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Analog-to-Digital Converter (ADC) Table 26-22. ADC Clock Summary Clock input Source Characteristics Peripheral Clock (=System Clock) 1/2 Core clock Maximum rate is PLL output divided by 2 if PLL enabled. When PLL disabled, max rate is oscillator clock divided by 2. ADC 8MHz Clock 26.5.9.2 Relaxation Provides 8MHz for auto standby power saving mode.
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Analog-to-Digital Converter (ADC) standby power mode requires an 8 MHz oscillator clock from the relaxation oscillator, crystal oscillator, or external oscillator. 26.5.9.3 ADC Clock Resynchronization at Start of Scan At the fastest ADC speed, each ADC clock period is 6 system clock periods long. When asserting the start of a scan, by writing to a STARTn bit or by a SYNCn signal, the ADC clock is re-synchronized to align it to the system clock.
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Analog-to-Digital Converter (ADC) ADC Conversion Clock Resynchronized ADCA Scan Start START1 Asserted ADCB Scan Should Start Here ADCB Scan Start START0 Asserted System Clock Wait for next rising edge of ADC Conversion Clock Old ADC Clock ADC Clock After Resynchronization ADCA Scan ADCB Scan Delay in start because ADC Clock cannot be resynchronized: 5 System Clocks Figure 26-27. ADC Clock Resynchronization for Non-Simultaneous Parallel Modes 26.5.
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Analog-to-Digital Converter (ADC) VREFH is as noise-free as possible. Any noise residing on the VREFH voltage is directly transferred to the digital result. Figure 26-28 illustrates the internal workings of the ADC voltage reference circuit. VREFH must be noise filtered; a minimum configuration is shown in the figure. 26.5.11 Supply Pins VDDA and VSSA Dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy.
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Chapter 27 Pulse-Width Modulation (PWM) Module 27.1 Introduction This chapter describes the configuration and operation of the pulse-width modulation (PWM) module. It includes a block diagram, programming model, and functional description. 27.1.1 Overview The PWM module, shown in Figure 27-1, generates a synchronous series of pulses having programmable period and duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter.
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Pulse-Width Modulation (PWM) Module Main features include the following: • Double-buffered period and duty cycle • Left- or center-aligned outputs • Eight independent PWM modules • Byte-wide registers provide programmable duty cycle and period control • Four programmable clock sources NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”) prior to configuring the PWM module. 27.
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Pulse-Width Modulation (PWM) Module 27.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEn) to start its waveform output. While in run mode, if all eight PWM output channels are disabled (PWME[7:0] = 0), the prescaler counter shuts off for power savings. See Section 27.3.2.1, “PWM Enable” for more information.
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Pulse-Width Modulation (PWM) Module Table 27-2. PWME Field Descriptions (continued) Field Description 1 PWM Channel 1 Output Enable. If enabled, the PWM signal becomes available at PWMOUT1 when its PWME1 corresponding clock source begins its next cycle. 0 PWM output disabled 1 PWM output enabled 0 PWM Channel 0 Output Enable. If enabled, the PWM signal becomes available at PWMOUT0 when its PWME0 corresponding clock source begins its next cycle.
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Pulse-Width Modulation (PWM) Module IPSBAR 0x1B_0002 (PWMCLK) Offset: Access: User Read/Write 7 6 5 4 3 2 1 0 PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0 0 0 0 0 0 0 0 R W Reset: Figure 27-4. PWM Clock Select Register (PWMCLK) Table 27-4. PWMCLK Field Descriptions Field Description 7–0 PCLKn PWM channel n clock select. Selects between one of two clock sources for each PWM channel. See Section 27.2.4, “PWM Prescale Clock Select Register (PWMPRCLK)” and Section 27.2.
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Pulse-Width Modulation (PWM) Module Table 27-5. PWMPRCLK Field Descriptions Field 7 Description Reserved, should be cleared. 6–4 PCKB 3 Clock B prescaler select. These three bits control the rate of Clock B which can be used for PWM channels2, 3, 6 and 7. PCKB Clock B Rate 000 Internal bus clock ÷ 20 001 Internal bus clock ÷ 21 ... ... 111 Internal bus clock ÷ 27 Reserved, should be cleared. 2–0 PCKA Clock A prescaler select.
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Pulse-Width Modulation (PWM) Module Table 27-6. PWMCAE Field Descriptions Field Description 7–0 CAEn Center align enable for channel n. The even-numbered channels’ center align enable has no effect when the corresponding PWMCTL[CONn(n+1)] bit is set. For example, if PWMCTL[CON01] equals 1, PWMCAE[CAE0] has no affect. 0 Channel n operates in left-aligned output mode 1 Channel n operates in center-aligned output mode 27.2.
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Pulse-Width Modulation (PWM) Module Table 27-7. PWMCTL Field Descriptions (continued) Field Description 3 PSWAI PWM stops in doze mode. Disables the input clock to the prescaler while in doze mode. 0 Allow the clock to the prescaler while in doze mode 1 Stop the input clock to the prescaler when the core is in doze mode 2 PFRZ PWM counters stop in debug mode (BKPT asserted). 0 Allow PWM counters to continue while in debug mode 1 Disable PWM input clock to the prescaler when the core is in debug mode.
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Pulse-Width Modulation (PWM) Module 27.2.8 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated according to the following equation: Clock B Clock SB = ---------------------------------------2 × PWMSCLB Eqn. 27-2 Any value written to this register causes the scale counter to load the new scale value (PWMSCLB).
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Pulse-Width Modulation (PWM) Module (PWMEn=0), the PWMCNTn register does not count. When a channel is enabled (PWMEn=1), the associated PWM counter starts at the count in the PWMCNTn register. For more detailed information on the operation of the counters, refer to Section 27.3.2.4, “PWM Timer Counters.
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Pulse-Width Modulation (PWM) Module IPSBAR 0x1B_0014 (PWMPER0) Offset: 0x1B_0015 (PWMPER1) 0x1B_0016 (PWMPER2) 0x1B_0017 (PWMPER3) 0x1B_0018 (PWMPER4) 0x1B_0019 (PWMPER5) 0x1B_001A (PWMPER6) 0x1B_001B (PWMPER7) 7 6 Access: User Read/Write 5 4 3 2 1 0 1 1 1 1 R PERIOD W Reset: 1 1 1 1 Figure 27-11. PWM Period Registers (PWMPERn) Table 27-11. PWMPERn Field Descriptions Field Description 7–0 Period counter for the output PWM signal.
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Pulse-Width Modulation (PWM) Module Table 27-12. PWMDTYn Field Descriptions Field Description 7–0 DUTY Contains the duty value used to determine when a transition occurs on the PWM output signal. When a match occurs with the corresponding PWMCNTn register, the PWM output toggles. If DUTY equals 0x00, the PWMn output is always low (PPOLn=1) or always high (PPOLn=0). See Section 27.3.2.8, “PWM Boundary Cases” for other special cases. 27.2.
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Pulse-Width Modulation (PWM) Module Table 27-13. PWMSDN Field Descriptions (continued) Field Description 1 PWM7IL PWM channel 7 input polarity. If PWMSDN[SDNEN] is set, this bit sets the active level of the PWM 7 channel 0 PWM 7 input is active low 1 PWN 7 input is active high 0 SDNEN PWM emergency shutdown enable. If set, the pin associated with PWM channel 7 is forced to input and the emergency shutdown feature is enabled. 0 Emergency shutdown is disabled 1 Emergency shutdown is enabled 27.3 27.3.
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Pulse-Width Modulation (PWM) Module PCLR0 1 Clock to PWM0 0 1 Clock to PWM1 0 PCLR1 Clock SA PWMSCLA PCLR4 1 ÷2 Clock to PWM4 0 PWMPRCLK [PCKA] 1 Clock to PWM5 0 Clock A PCLR5 PCLR2 Internal Bus Clock (fsys/) Clock SB 1 PWMSCLB ÷2 Clock to PWM2 0 PWMPRCLK [PCKB] 1 Clock to PWM3 0 Clock B PCLR3 PCLR6 1 Clock to PWM6 0 1 Clock to PWM7 0 PCLR7 Figure 27-14. PWM Clock Select Block Diagram 27.3.1.
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Pulse-Width Modulation (PWM) Module 27.3.1.2 Scaled Clock (SA or SB) The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with a user programmable value, then divide this by 2. The rates available for clock SA are programmable to run at clock A divided by 2, 4,..., or 512. Similar rates are available for clock SB.
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Pulse-Width Modulation (PWM) Module Clock Source From Figure 27-14 PWMCNTn PWMDTYn 0 Up/Down Reset 1 PWMOUTn PWMEn PPOLn PWMPERn PWMCAE = 1 PWMCAE = 0 Figure 27-15. PWM Timer Channel Block Diagram 27.3.2.1 PWM Enable Each PWM channel has an enable bit (PWMEn) to start its waveform output. When any of the PWMEn bits are set (PWMEn=1), the associated PWM output signal is enabled immediately.
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Pulse-Width Modulation (PWM) Module and/or period values to be latched. In addition, because the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used to make adjustments. When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers contain the count of the high time or the low time. 27.3.2.
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Pulse-Width Modulation (PWM) Module 27.3.2.5 Left-Aligned Outputs The PWM timer provides the choice of two types of outputs: left- or center-aligned. They are selected with the PWMCAE[CAEn] bits. If the CAEn bit is cleared, the corresponding PWM output is left-aligned. In left-aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register, as shown in the block diagram in Figure 27-15.
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Pulse-Width Modulation (PWM) Module E = 25ns DUTY CYCLE = 75% PERIOD = 100ns Figure 27-17. PWM Left-Aligned Output Example Waveform 27.3.2.6 Center-Aligned Outputs For center-aligned output mode selection, set the PWMCAE[CAEn] bit and the corresponding PWM output is center-aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up when the counter is equal to 0x00.
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Pulse-Width Modulation (PWM) Module PWMDTYn Duty Cycle = ⎛ 1 – PWMPOL [ PPOLn ] – -------------------------------⎞ × 100% ⎝ PWMPERn ⎠ 27.3.2.6.1 Eqn.
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Pulse-Width Modulation (PWM) Module Clock Source 7 High PWMCNT6 Low PWMCNT7 Period/Duty Compare Clock Source 5 High PWMCNT4 PWMOUT7 Low PWMCNT5 Period/Duty Compare Clock Source 3 High PWMCNT2 PWMOUT5 Low PWMCNT3 Period/Duty Compare Clock Source 1 High PWMCNT0 PWMOUT3 Low PWMCNT1 Period/Duty Compare PWMOUT1 Figure 27-20. PWM 16-Bit Mode Left- or center-aligned output mode can be used in concatenated mode and is controlled by the low order CAEn bit. The high order CAEn bit has no effect.
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Pulse-Width Modulation (PWM) Module Table 27-16. PWM Boundary Cases 1 PWMDTYn PWMPERn PPOLn PWMn Output 0x00 (indicates no duty) >0x00 1 Always Low 0x00 (indicates no duty) >0x00 0 Always High XX 0x001 (indicates no period) 1 Always High XX 0x001 (indicates no period) 0 Always Low ≥ PWMPERn XX 1 Always High ≥ PWMPERn XX 0 Always Low Counter = 0x00 and does not count. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 28 Debug Module 28.1 Introduction This chapter describes the revision B+ enhanced hardware debug module. 28.1.1 Block Diagram The debug module is shown in Figure 28-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PST[3:0], DDATA[3:0] PSTCLK Communication Port DSCLK, DSI, DSO Figure 28-1. Processor/Debug Module Interface 28.1.
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Debug Module The first version 2 ColdFire core devices implemented the original debug architecture, now called revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores. For revision A, CSR[HRL] is 0. See Section 28.4.2, “Configuration/Status Register (CSR)”.
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Debug Module Table 28-2. Debug Module Signals (continued) Signal Description Processor Status Clock (PSTCLK) Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values. The following figure shows PSTCLK timing with respect to PSTD and DATA.
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Debug Module Execution speed is affected only when both storage elements contain valid data to be dumped to the DDATA port. The core stalls until one FIFO entry is available. Table 28-3 shows the encoding of these signals. Table 28-3. Processor Status Encoding PST[3:0] Definition 0x0 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
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Debug Module 28.3.1 Begin Execution of Taken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output. Multiple byte DDATA values are displayed in least-to-most-significant order.
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Debug Module 28.4 Memory Map/Register Definition In addition to the existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contain a number of registers to support the required functionality. These registers are also accessible from the processor’s supervisor programming model by executing the WDEBUG instruction (write only).
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Debug Module NOTE Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. These control registers are write-only from the programming model and they can be written through the BDM port using the WDMREG command. In addition, the configuration/status register (CSR) can be read through the BDM port using the RDMREG command.
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Debug Module DRc[4:0]: 0x00 (CSR) 31 30 R Access: Supervisor write-only BDM read/write 29 28 BSTAT 27 FOF 26 25 24 23 22 TRG HALT BKPT 21 20 HRL 19 18 0 0 0 0 W Reset R W Reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 MAP TRC EMU 0 0 0 DDC 0 UHE 0 0 0 0 1 7 6 5 4 0 BTB 0 1 0 0 NPL IPI SSM 0 0 0 17 16 PCD IPW 0 0 3 2 1 0 0 0 0 0 0 0 0 0 Figure 28-3. Configuration/Status Register (CSR) Table 28-6.
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Debug Module Table 28-6. CSR Field Descriptions (continued) Field Description 15 MAP Force processor references in emulator mode. 0 All emulator-mode references are mapped into supervisor code and data spaces. 1 The processor maps all references while in emulator mode to a special address space, TT equals 10, TM equals 101 or 110. The internal SRAM and caches are disabled. 14 TRC Force emulation mode on trace exception.
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Debug Module Table 28-6. CSR Field Descriptions (continued) Field Description 4 SSM Single-Step Mode. Setting SSM puts the processor in single-step mode. 0 Normal mode. 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the GO command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. 3–0 Reserved, must be cleared. 28.4.
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Debug Module setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4:0]: 0x06 (AATR) 15 Access: Supervisor write-only BDM write-only 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset RM 0 SZM 0 TTM 0 0 TMM 0 0 0 R 0 0 SZ 0 TT 0 0 TM 0 1 0 1 Figure 28-5. Address Attribute Trigger Register (AATR) Table 28-8.
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Debug Module Table 28-8. AATR Field Descriptions (continued) Field Description 4–3 TT Transfer Type. Compared with the local bus transfer type signals. 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Acknowledge/CPU space access These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates an external or DMA access (for backward compatibility). These bits affect the TM bits. 2–0 TM Transfer Modifier.
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Debug Module DRc[4:0]: 0x07 (TDR) Access: Supervisor write-only BDM write-only Second Level Trigger 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W Reset TRC 0 L2EBL 0 0 L2ED 0 0 0 0 L2DI 0 0 0 L2EA L2EPC L2PCI 0 0 0 0 0 0 5 4 3 2 1 0 First Level Trigger 15 14 13 12 11 10 0 0 0 9 8 7 6 0 0 0 R W L2T Reset 0 L1T L1EBL 0 0 L1ED 0 L1DI 0 L1EA 0 0 L1EPC L1PCI 0 0 0 Figure 28-6. Trigger Definition Register (TDR) Table 28-9.
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Debug Module Table 28-9. TDR Field Descriptions (continued) Field Description 20–18 L2EA Enable Level 2 Address Breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all three bits disables the breakpoint. TDR Bit 17 L2EPC Description 20 Address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR. 19 Address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR. 18 Address breakpoint low.
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Debug Module Table 28-9. TDR Field Descriptions (continued) Field Description 12–6 L1ED Enable Level 1 Data Breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints. TDR Bit Description 12 Data longword. Entire processor’s local data bus. 11 Lower data word. 10 Upper data word. 9 Lower lower data byte. Low-order byte of the low-order word.
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Debug Module contents of the breakpoint registers are compared with the processor’s program counter register when TDR is configured appropriately. The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the WDMREG command using values shown in Section 28.5.3.3, “Command Set Descriptions”.
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Debug Module DRc[4:0]: 0x09 (PBMR) Access: Supervisor write-only BDM write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 28-9. PC Breakpoint Mask Register (PBMR) Table 28-12. PBMR Field Descriptions Field 31–0 Mask 28.4.7 Description PC Breakpoint Mask. 0 The corresponding PBR0 bit is compared to the appropriate PC bit. 1 The corresponding PBR0 bit is ignored.
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Debug Module 28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR) The data breakpoint register (DBR), specify data patterns used as part of the trigger into debug mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR. DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the WDMREG command.
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Debug Module Table 28-17. Address, Access Size, and Operand Data Location 28.5 Address[1:0] Access Size Operand Location 00 Byte D[31:24] 01 Byte D[23:16] 10 Byte D[15:8] 11 Byte D[7:0] 0x Word D[31:16] 1x Word D[15:0] xx Longword D[31:0] Background Debug Mode (BDM) The ColdFire family implements a low-level system debugger in the microprocessor in a dedicated hardware module.
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Debug Module 3. The execution of a HALT instruction immediately suspends execution. Attempting to execute HALT in user mode while CSR[UHE] is cleared generates a privilege violation exception. If CSR[UHE] is set, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a GO command into the debug module. Execution continues at the instruction after HALT. 4.
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Debug Module C0 C1 C2 C3 C4 PSTCLK DSCLK Current DSI BDM State Machine Next Next State Current State Past DSO Current Figure 28-13. Maximum BDM Serial Interface Timing DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along with DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge (registered after a BDM state machine state change).
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Debug Module Table 28-18. Receive BDM Packet Field Description Field 16 S Description Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
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Debug Module Table 28-20. BDM Command Summary Command Mnemonic Read A/D register RAREG/ Write A/D register WAREG/ Read memory location Description CPU State1 Section/Page Command (Hex) Read the selected address or data register and return the results through the serial interface. Halted 28.5.3.3.1/28-26 0x218 {A/D, Reg[2:0]} Write the data operand to the specified address or data register. Halted 28.5.3.3.
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Debug Module 28.5.3.1 ColdFire BDM Command Format All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words. 15 14 13 12 11 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 1 0 Register Extension Word(s) Figure 28-16. BDM Command Format Table 28-21. BDM Field Descriptions Field Description 15–10 Specifies the command. These values are listed in Table 28-20.
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Debug Module 28.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 28-17 shows serial bus traffic for commands. Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.
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Debug Module • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the final transfer. If a bus error terminates a memory or register access, error status (S = 1, DATA = 0x0001) returns instead of result data. 28.5.3.
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Debug Module 28.5.3.3.2 Write A/D Register (WAREG/WDREG) The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: 15 14 13 12 11 0x2 10 9 8 7 0x0 6 5 4 0x8 3 2 A/D 1 0 Register D[31:16] D[15:0] Figure 28-20.
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Debug Module Command/Result Formats: 15 14 Byte 13 12 11 10 0x1 9 8 7 0x9 6 5 4 3 0x0 Command 2 1 0 0x0 A[31:16] A[15:0] Result Word Command X X X X X X 0x1 X X 0x9 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] Result Longword Command D[15:0] 0x1 0x9 A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 28-22.
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Debug Module 28.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. BAAR[TT,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
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Debug Module Command Sequence: WRITE (B/W) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ WRITE (LONG) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 28-25. WRITE Command Sequence Operand Data: Result Data: 28.5.3.3.
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Debug Module NOTE DUMP does not check for a valid address; it is a valid command only when preceded by NOP, READ, or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is processed, allowing the operand size to be dynamically altered.
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Debug Module Result Data: 28.5.3.3.6 Requested data is returned as a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs. Fill Memory Block (FILL) A FILL command is used with the WRITE command to access large blocks of memory.
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Debug Module Command Sequence: FILL (LONG) ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR FILL (B/W) ??? DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ NEXT CMD ’NOT READY’ XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 28-29. FILL Command Sequence Operand Data: A single operand is data to be written to the memory location.
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Debug Module Operand Data: Result Data: 28.5.3.3.8 NOP None The command-complete response (0xFFFF) is returned during the next shift operation. No Operation (NOP) performs no operation and may be used as a null command where required. Command Formats: 15 14 13 12 0x0 11 10 9 0x0 8 7 6 5 4 3 2 0x0 1 0 0x0 Figure 28-32. NOP Command Format Command Sequence: NOP ??? NEXT CMD ’CMD COMPLETE’ Figure 28-33. NOP Command Sequence Operand Data: Result Data: 28.5.3.3.
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Debug Module 15 14 13 12 11 10 0x0 9 8 7 6 0x0 5 4 3 2 0x0 1 0 0x1 Figure 28-34. SYNC_PC Command Format Command Sequence: SYNC_PC NEXT CMD ??? CMD COMPLETE Figure 28-35. SYNC_PC Command Sequence Operand Data: Result Data: None Command complete status (0xFFFF) is returned when the register write is complete. 28.5.3.3.10 Read Control Register (RCREG) Read the selected control register and return the 32-bit result.
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Debug Module Command Sequence: RCREG ??? MS ADDR ’NOT READY’ READ CONTROL REGISTER MS ADDR ’NOT READY’ XXX ’NOT READY’ NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ Figure 28-37. RCREG Command Sequence Operand Data: Result Data: The only operand is the 32-bit Rc control register select field. Control register contents are returned as a longword, most-significant word first.
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Debug Module else A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Pointer The BDM programming model supports reads and writes to A7 and OTHER_A7 directly. It is the responsibility of the external development system to determine the mapping of A7 and OTHER_A7 to the two program-visible definitions (supervisor and user stack pointers), based on the SR[S] bit. 28.5.3.3.12 Write Control Register (WCREG) The operand (longword) data is written to the specified control register.
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Debug Module 28.5.3.3.13 Read Debug Module Register (RDMREG) Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). This read of the CSR clears CSR (FOF, TRG, HALT, and BKPT) as well as the trigger status bits (CSR[BSTAT]) if a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and no level-2 breakpoint has been enabled.
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Debug Module Command Format: Figure 28-42. WDMREG BDM Command Format 15 14 13 12 0x2 11 10 9 8 7 0xC 6 5 4 3 100 2 1 0 DRc D[31:16] D[15:0] Table 28-4 shows the definition of the DRc write encoding. Command Sequence: WDMREG ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ Figure 28-43. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register.
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Debug Module Table 28-24. DDATA[3:0]/CSR[BSTAT] Breakpoint Response 1 DDATA[3:0]1 CSR[BSTAT]1 0000 0000 No breakpoints enabled 0010 0001 Waiting for level-1 breakpoint 0100 0010 Level-1 breakpoint triggered 1010 0101 Waiting for level-2 breakpoint 1100 0110 Level-2 breakpoint triggered Breakpoint Status Encodings not shown are reserved for future use. The breakpoint status is also posted in the CSR.
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Debug Module When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator mode. After the debug interrupt handler completes execution, the external development system can use BDM commands to read the reserved memory locations. In revision B/B+, the hardware inhibits generation of another debug interrupt during the first instruction after the RTE exits emulator mode.
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Debug Module NOTE Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint triggers. Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU is writing the debug’s registers (DSCLK must be inactive).
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Debug Module Table 28-25. PST/DDATA Specification for User-Mode Instructions Instruction Operand Syntax PST/DDATA add.l y,Dx PST = 0x1, {PST = 0xB, DD = source operand} add.l Dy,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} adda.l y,Ax PST = 0x1, {PST = 0xB, DD = source operand} addi.l #,Dx PST = 0x1 addq.l #,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} addx.l Dy,Dx PST = 0x1 and.
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Debug Module Table 28-25. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA divu.w y,Dx PST = 0x1, {PST = 0x9, DD = source operand} eor.l Dy,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} eori.l #,Dx PST = 0x1 ext.l Dx PST = 0x1 ext.w Dx PST = 0x1 extb.
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Debug Module Table 28-25. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA or.l Dy,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} ori.l #,Dx PST = 0x1 pea.l y PST = 0x1, {PST = 0xB, DD = destination operand} pulse PST = 0x4 rems.l y,Dw:Dx PST = 0x1, {PST = 0xB, DD = source operand} remu.
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Debug Module 1 During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
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Debug Module Table 28-26. PST/DDATA Values for User-Mode Multiply-Accumulate Instructions (continued) Instruction 28.7.2 Operand Syntax PST/DDATA msac.w Ry,Rx PST = 0x1 msac.w Ry,Rx,y,Rw PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. The PST/DDATA specification for these opcodes is shown in Table 28-27. Table 28-27.
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Debug Module Developer reserved1 1 2 BKPT GND 3 4 DSCLK GND 5 6 Developer reserved1 RESET 7 8 DSI 2 EVDD 9 10 GND PST2 11 12 DSO PST3 13 14 PST1 PST0 15 16 DDATA2 DDATA0 17 18 DDATA3 DDATA1 19 20 GND Freescale reserved 21 22 Freescale reserved GND 23 24 PSTCLK IVDD 25 26 TA 1 Pins reserved for BDM 2 Supplied by target developer use. Figure 28-44. Recommended BDM Connector MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev.
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Chapter 29 IEEE 1149.1 Test Access Port (JTAG) 29.1 Introduction The Joint Test Action Group (JTAG) is a dedicated user-accessible test logic compliant with the IEEE 1149.1 standard for boundary-scan testability, which helps with system diagnostic and manufacturing testing. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. 29.1.
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IEEE 1149.1 Test Access Port (JTAG) 29.1.
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IEEE 1149.1 Test Access Port (JTAG) Table 29-2. Pin Function Selected JTAG_EN = 0 JTAG_EN = 1 Pin Name Module selected BDM JTAG — Pin Function — BKPT DSI DSO DSCLK TCLK TMS TDI TDO TRST TCLK BKPT DSI DSO DSCLK When one module is selected, the inputs into the other module are disabled or forced to a known logic level, as shown in Table 29-3, to disable the corresponding module. Table 29-3.
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IEEE 1149.1 Test Access Port (JTAG) 29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the TAP controller to the test-logic-reset state. The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, data input on DSI is sampled and DSO changes state. 29.2.
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IEEE 1149.1 Test Access Port (JTAG) IR[4:0]: 0_0001 (IDCODE) Access: User read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R PRN DC 9 8 PIN 7 6 5 4 3 2 1 JEDEC 0 ID W Reset 1 See note1 0 1 1 1 0 1 See note1 0 0 0 0 0 0 0 1 1 1 0 1 The reset values for PRN and PIN are device-dependent. Figure 29-3. IDCODE Register Table 29-4. IDCODE Field Descriptions Field Description 31–28 PRN Part revision number.
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IEEE 1149.1 Test Access Port (JTAG) The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG signals, analog signals, power supplies, compliance enable pins, and clock signals. 29.4 29.4.1 Functional Description JTAG Module The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers. 29.4.
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IEEE 1149.1 Test Access Port (JTAG) 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT DR-SCAN SELECT IR-SCAN 1 1 CAPTURE-DR 1 CAPTURE-IR 0 0 0 SHIFT-DR 1 EXIT1-DR 1 EXIT1-IR 1 1 0 0 0 PAUSE-DR 0 PAUSE-IR 1 1 EXIT2-DR EXIT2-IR 0 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 0 0 UPDATE-IR 0 1 0 Figure 29-4. TAP Controller State Machine Flow 29.4.3 JTAG Instructions Table 29-5 describes public and private instructions. Table 29-5.
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IEEE 1149.1 Test Access Port (JTAG) Table 29-5.
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IEEE 1149.1 Test Access Port (JTAG) and held in the boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state while performing external boundary scan operations. 29.4.3.4 TEST_LEAKAGE Instruction The TEST_LEAKAGE instruction forces the jtag_leakage output signal to high.
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IEEE 1149.1 Test Access Port (JTAG) to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. 29.4.3.9 BYPASS Instruction The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI pin to the TDO pin.
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Appendix A Register Memory Map Quick Reference Table A-1 summarizes the address, name, and byte assignment for registers within the MCF52211 CPU space. Table A-2 lists an overview of the memory map for the on-chip modules, and Table A-3 is a detailed memory map including all of the registers for on-chip modules. Table A-1.
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Register Memory Map Quick Reference Table A-2.
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Register Memory Map Quick Reference Table A-2. Module Memory Map Overview (continued) Address Module Size IPSBAR + 0x18_0000 Reserved 64K IPSBAR + 0x19_0000 ADC 64K IPSBAR + 0x1A_0000 General Purpose Timer 64K IPSBAR + 0x1B_0000 PWM 64K IPSBAR + 0x1C_0000 USB-OTG 64K IPSBAR + 0x1D_0000 CFM (Flash) Control Registers 64K IPSBAR + 0x1E_0000 Reserved 63M+128K IPSBAR + 0x400_0000 CFM (Flash) Memory for IPS Reads and Writes 128K Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Register Memory Map Quick Reference Table A-3.
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Appendix B Revision History This appendix describes corrections to the MCF52211 Reference Manual. For convenience, the corrections are grouped by revision. B.1 Changes between Rev. 1 and Rev. 2 Table 1. MCF52211RM Rev. 1 to Rev. 2 Changes Location Description Throughout Formatting, layout, spelling, and grammar corrections. Chapter 1 Added information about the MCF52212 and MCF52213 devices. Table 2-1 / Page 2-6 • Changed the GPTn pin assignments for the 64-pin package (were 40...
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Revision History B.2 Changes between Rev. 0 and Rev. 1 Table 2. MCF52211RM Rev. 0 to Rev. 1 Changes Location Description Throughout • Formatting, layout, spelling, and grammar corrections. • Removed the “Preliminary” label. Table 2-1 / Page 2-3 Synchronized the table in the reference manual and the device data sheet. Table 6-4 / Page 6-6 Corrected the CCHR reset value (was 0x04, is 0x05). Figure 6-12 / Page 6-19 Deleted the RS resistor.