Integrated Microcontroller Reference Manual

System Control Module (SCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-11
• Master 2 (M2): 4-channel DMA
• Master 0 (M0): V2 ColdFire Core
IPSBAR
Offset: 0x001C (MPARK)
Access: read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0
M2_P
_EN
BCR2
4BIT
00
M2_PRTY
M0_PRTY
00
W
Reset0 0 1100001 1 1000 01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
FIXED
TIME
OUT
PRKL
AST
LCKOUT_TIME
0
0 0000 00
W
Reset0 0 0000000 0 0000 00
Figure 12-7. Default Bus Master Park Register (MPARK)
Table 12-7. MPARK Field Description
Field Description
31–26 Reserved, should be cleared.
25
M2_P_EN
DMA bandwidth control enable
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
24
BCR24BIT
Enables the use of 24 bit byte count registers in the DMA module
0 DMA BCRs function as 16 bit counters.
1 DMA BCRs function as 24 bit counters.
23–22 Reserved, should be cleared.
21–20
M2_PRTY
Master priority level for master 2 (DMA Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
19–18
M0_PRTY
Master priority level for master 0 (ColdFire Core)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
17–16 Reserved, should be cleared.
15 Reserved, should be cleared.
14
FIXED
Fixed or round robin arbitration
0 round robin arbitration
1 fixed arbitration
13
TIMEOUT
Timeout Enable
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is
reached.