Integrated Microcontroller Reference Manual

Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
15-22 Freescale Semiconductor
15.4.1.14 Control Register (CTL)
The Control Register provides various control and configuration information for the USB Module.
Figure 15-20 shows the CTL register.
IPSBAR
Offset: 0x1C_0094 (CTL) Access: User read/write
76 5 43210
R
JSTATE SE0
TXSUSPEND/
TOKENBUSY
RESET
HOST_
MODE_EN
RESUME ODD_RST
USB_EN/
SOF_EN
W
Reset:00 0 00000
Figure 15-20. Control Register
Table 15-24. CTL Field Descriptions
Field Description
7
JSTATE
Live USB differential receiver JSTATE signal. The polarity of this signal is affected by the current state of
LS_EN (See)
6
SE0
Live USB Single Ended Zero signal
5
TXSUSPEND/
TOKENBUSY
When the USB Module is in Host mode TOKEN_BUSY is set when the USB Module is busy executing a USB
token and no more token commands should be written to the Token Register. Software should check this bit
before writing any tokens to the Token Register to ensure that token commands are not lost.
In Target mode TXD_SUSPEND is set when the SIE has disabled packet transmission and reception.
Clearing this bit allows the SIE to continue token processing. This bit is set by the SIE when a Setup Token
is received allowing software to dequeue any pending packet transactions in the BDT before resuming token
processing.
4
RESET
Setting this bit enables the USB Module to generate USB reset signaling. This allows the USB Module to
reset USB peripherals. This control signal is only valid in Host mode (HOST_MODE_EN=1). Software must
set RESET to 1 for the required amount of time and then clear it to 0 to end reset signaling. For more
information on RESET signaling see Section 7.1.4.3 of the USB specification version 1.0.
3
HOST_
MODE_EN
When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the USB module
performs USB transactions under the programmed control of the host processor.
2
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling. This allows the USB Module to
perform remote wake-up. Software must set RESUME to 1 for the required amount of time and then clear it
to 0. If the HOST_MODE_EN bit is set, the USB module appends a Low Speed End of Packet to the Resume
signaling when the RESUME bit is cleared. For more information on RESUME signaling see Section 7.1.4.5
of the USB specification version 1.0.
1
ODD_RST
Setting this bit to 1 resets all the BDT ODD ping/pong bits to 0, which then specifies the EVEN BDT bank.
0
USB_EN/
SOF_EN
USB Enable
0 The USB Module is disabled
1 The USB Module is enabled.
Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much
of the logic in the SIE. When host mode is enabled, clearing this bit causes the SIE to stop sending SOF
tokens.