Integrated Microcontroller Reference Manual

Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 28-17
28.4.7 Address Breakpoint Registers (ABLR, ABHR)
The ABLR and ABHR define regions in the processor’s data address space that can act as part of the
trigger. These register values are compared with the address for each transfer on the processor’s high-speed
local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:
• Identically the value in ABLR
• Inside the range bound by ABLR and ABHR inclusive
• Outside that same range
ABLR and ABHR are accessible in supervisor mode using the WDEBUG instruction and via the BDM
port using the WDMREG command.
DRc[4:0]: 0x09 (PBMR) Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WMask
Reset––––––––––––––––––––––––––––––––
Figure 28-9. PC Breakpoint Mask Register (PBMR)
Table 28-12. PBMR Field Descriptions
Field Description
31–0
Mask
PC Breakpoint Mask.
0 The corresponding PBR0 bit is compared to the appropriate PC bit.
1 The corresponding PBR0 bit is ignored.
DRc[4:0]: 0x0C (ABHR)
0x0D (ABLR)
Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WAddress
Reset––––––––––––––––––––––––––––––––
Figure 28-10. Address Breakpoint Registers (ABLR, ABHR,)
Table 28-13. ABLR Field Description
Field Description
31–0
Address
Low Address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
specific single addresses are programmed into ABLR.
Table 28-14. ABHR Field Description
Field Description
31–0
Address
High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range.