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MPC8260 PowerQUICC™ II

Family Reference Manual

Supports

MPC8250

MPC8255

MPC8260

MPC8264

MPC8265

MPC8266

MPC8260RM

Rev. 2, 12/2005

Summary of content (1360 pages)

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MPC8260 PowerQUICC™ II Family Reference Manual Supports MPC8250 MPC8255 MPC8260 MPC8264 MPC8265 MPC8266 MPC8260RM Rev.
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How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.
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Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
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I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
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Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports 35 36 37 38 39 40 Register Quick Reference Guide Reference Manual (Rev 1) Errata A B Glossary of Terms and Abbreviations Index GLO IND
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35 36 37 38 39 40 Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports A B Register Quick Reference Guide Reference Manual (Rev 1) Errata GLO IND Glossary of Terms and Abbreviations Index
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Contents Paragraph Number Title Page Number About This Book Reference Manual Revision History............................................................................ lxxvii Before Using this Manual—Important Note ................................................................ lxxix Audience ....................................................................................................................... lxxix Organization..........................................................................
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Contents Paragraph Number 1.7.2.5 1.7.2.6 Title Page Number PCI with 155-Mbps ATM ...................................................................................... 1-22 PowerQUICC II as PCI Agent............................................................................... 1-23 Chapter 2 G2 Core 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.5 2.2.6 2.2.6.1 2.2.6.2 2.3 2.3.1 2.3.1.1 2.3.1.2 2.3.1.2.1 2.3.1.2.2 2.3.1.2.3 2.3.1.2.4 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.4 2.4.1 2.4.
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Contents Paragraph Number 2.5.1 2.5.2 2.5.3 2.6 2.6.1 2.6.2 2.7 2.8 Title Page Number PowerPC Exception Model........................................................................................ 2-21 PowerQUICC II Implementation-Specific Exception Model.................................... 2-22 Exception Priorities.................................................................................................... 2-25 Memory Management....................................................................
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Contents Paragraph Number 4.3.1.7 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.2.9 4.3.2.10 4.3.2.11 4.3.2.12 4.3.2.13 4.3.2.14 4.3.2.15 4.3.2.16 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 4.3.4 4.3.4.1 4.3.4.2 4.4 Title Page Number SIU External Interrupt Control Register (SIEXR)................................................. 4-25 System Configuration and Protection Registers ........................................................ 4-26 Bus Configuration Register (BCR)..................
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Contents Paragraph Number 5.4.2.2 5.4.2.3 5.4.2.4 Title Page Number Single PowerQUICC II Configured from Boot EPROM ...................................... 5-10 Multiple PowerQUICC IIs Configured from Boot EPROM ................................. 5-11 Multiple PowerQUICC IIs in a System with No EPROM .................................... 5-13 Chapter 6 External Signals 6.1 6.2 Functional Pinout .............................................................................................................
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Contents Paragraph Number 7.2.4.4.2 7.2.4.5 7.2.4.6 7.2.5 7.2.5.1 7.2.5.1.1 7.2.5.1.2 7.2.5.2 7.2.5.2.1 7.2.5.2.2 7.2.6 7.2.6.1 7.2.6.1.1 7.2.6.1.2 7.2.6.2 7.2.6.2.1 7.2.6.2.2 7.2.7 7.2.7.1 7.2.7.1.1 7.2.7.1.2 7.2.7.2 7.2.7.2.1 7.2.7.2.2 7.2.8 7.2.8.1 7.2.8.1.1 7.2.8.1.2 7.2.8.2 7.2.8.2.1 7.2.8.2.2 7.2.8.3 7.2.8.3.1 7.2.8.3.2 Title Page Number Global (GBL)—Input .......................................................................................... 7-8 Caching-Inhibited (CI)—Output ...................
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Contents Paragraph Number 8.2.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.3.5 8.4.3.6 8.4.3.7 8.4.3.8 8.4.4 8.4.4.1 8.4.4.2 8.4.5 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.7 8.7.1 8.7.2 8.8 Title Page Number 60x-Compatible Bus Mode.......................................................................................... 8-3 60x Bus Protocol Overview ............................................................................................. 8-4 Arbitration Phase .....
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Contents Paragraph Number 9.6 9.7 9.8 9.9 9.9.1 9.9.1.1 9.9.1.2 9.9.1.2.1 9.9.1.2.2 9.9.1.2.3 9.9.1.2.4 9.9.1.3 9.9.1.3.1 9.9.1.3.2 9.9.1.4 9.9.1.4.1 9.9.1.4.2 9.9.1.4.3 9.9.1.4.4 9.9.1.4.5 9.9.1.4.6 9.9.1.4.7 9.9.1.5 9.9.1.5.1 9.9.1.5.2 9.9.2 9.9.2.1 9.9.2.2 9.9.2.3 9.10 9.10.1 9.10.2 9.10.2.1 9.10.2.2 9.10.3 9.11 9.11.1 9.11.1.1 9.11.1.2 9.11.1.3 9.11.1.4 Title Page Number 60x Bus Arbitration Priority ............................................................................................
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Contents Paragraph Number 9.11.1.5 9.11.1.6 9.11.1.7 9.11.1.8 9.11.1.9 9.11.1.10 9.11.1.11 9.11.1.12 9.11.1.13 9.11.1.14 9.11.1.15 9.11.1.16 9.11.1.17 9.11.2 9.11.2.1 9.11.2.2 9.11.2.3 9.11.2.4 9.11.2.5 9.11.2.6 9.11.2.7 9.11.2.8 9.11.2.9 9.11.2.10 9.11.2.11 9.11.2.12 9.11.2.13 9.11.2.14 9.11.2.15 9.11.2.16 9.11.2.17 9.11.2.18 9.11.2.19 9.11.2.20 9.11.2.21 9.11.2.22 9.11.2.23 9.11.2.24 9.11.2.25 9.11.2.26 Title Page Number PCI Outbound Comparison Mask Registers (POCMRx) ..................................
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Contents Paragraph Number 9.11.2.27 9.11.2.27.1 9.11.2.27.2 9.11.2.28 9.12 9.12.1 9.12.1.1 9.12.1.2 9.12.2 9.12.2.1 9.12.2.2 9.12.3 9.12.3.1 9.12.3.2 9.12.3.2.1 9.12.3.2.2 9.12.3.3 9.12.3.3.1 9.12.3.3.2 9.12.3.4 9.12.3.4.1 9.12.3.4.2 9.12.3.4.3 9.12.3.4.4 9.12.3.4.5 9.12.3.4.6 9.12.3.4.7 9.12.3.4.8 9.13 9.13.1 9.13.1.1 9.13.1.2 9.13.1.3 9.13.1.4 9.13.1.5 9.13.1.6 9.13.1.6.1 Title Page Number PCI Configuration Register Access in Big-Endian Mode ....................................
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Contents Paragraph Number 9.13.1.6.2 9.13.1.6.3 9.13.1.6.4 9.13.1.6.5 9.13.1.6.6 9.13.1.6.7 9.13.2 9.13.2.1 9.13.2.2 9.14 9.14.1 9.14.1.1 9.14.1.1.1 9.14.1.1.2 9.14.1.1.3 9.14.1.2 9.14.1.3 9.14.1.3.1 9.14.1.3.2 9.14.1.3.3 9.14.1.3.4 9.14.1.3.5 9.14.1.4 9.14.1.4.1 9.14.1.4.2 9.14.1.4.3 Title Page Number DMA Status Register [0–3] (DMASRx) .......................................................... 9-90 DMA Current Descriptor Address Register [0–3] (DMACDARx) ..................
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Contents Paragraph Number 10.6 10.6.1 10.7 10.8 10.9 10.10 Title Page Number PowerQUICC II Internal Clock Signals ........................................................................ 10-5 General System Clocks.............................................................................................. 10-5 PLL Pins ........................................................................................................................ 10-6 System Clock Control Register (SCCR).........................
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Contents Paragraph Number 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.5.1 11.4.5.2 11.4.6 11.4.6.1 11.4.6.2 11.4.6.3 11.4.6.4 11.4.6.5 11.4.6.6 11.4.6.7 11.4.6.8 11.4.7 11.4.8 11.4.9 11.4.10 11.4.11 11.4.12 11.4.12.1 11.4.13 11.5 11.5.1 11.5.1.1 11.5.1.2 11.5.1.3 11.5.1.4 11.5.1.5 11.5.1.6 11.5.2 11.5.3 11.5.4 11.6 11.6.1 11.6.1.1 11.6.1.2 11.6.1.3 Title Page Number SDRAM Machine ........................................................................................................
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Contents Paragraph Number 11.6.1.4 11.6.2 11.6.3 11.6.4 11.6.4.1 11.6.4.1.1 11.6.4.1.2 11.6.4.1.3 11.6.4.1.4 11.6.4.1.5 11.6.4.2 11.6.4.3 11.6.4.4 11.6.4.5 11.6.4.6 11.6.5 11.6.6 11.7 11.7.0.1 11.8 11.8.1 11.8.2 11.9 11.9.1 11.9.2 11.9.3 11.9.4 11.9.5 11.9.5.1 Title Page Number Exception Requests.............................................................................................. 11-67 Programming the UPMs ..........................................................................................
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Contents Paragraph Number Title Page Number Chapter 13 IEEE 1149.1 Test Access Port 13.1 13.2 13.3 13.4 13.5 13.6 Overview........................................................................................................................ 13-1 TAP Controller............................................................................................................... 13-2 Boundary Scan Register.................................................................................................
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Contents Paragraph Number 14.6.7 14.6.8 14.6.9 14.6.10 Title Page Number RISC Timer Initialization Example ......................................................................... 14-26 RISC Timer Interrupt Handling ............................................................................... 14-26 RISC Timer Table Scan Algorithm.......................................................................... 14-26 Using the RISC Timers to Track CP Loading ....................................................
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Contents Paragraph Number 16.4.3 16.4.4 16.4.5 16.4.6 Title Page Number CMX SI2 Clock Route Register (CMXSI2CR)....................................................... 16-12 CMX FCC Clock Route Register (CMXFCR) ........................................................ 16-13 CMX SCC Clock Route Register (CMXSCR) ........................................................ 16-16 CMX SMC Clock Route Register (CMXSMR) ......................................................
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Contents Paragraph Number 19.5.2 19.5.2.1 19.5.2.1.1 19.5.2.1.2 19.5.2.2 19.5.2.2.1 19.5.2.2.2 19.5.3 19.5.4 19.6 19.7 19.7.1 19.7.1.1 19.7.1.2 19.7.2 19.8 19.8.1 19.8.2 19.8.2.1 19.8.2.2 19.8.2.3 19.8.3 19.8.4 19.8.5 19.9 19.9.1 19.9.2 19.10 19.10.1 19.11 19.12 19.12.1 19.12.2 19.12.3 Title Page Number Memory to/from Peripheral Transfers ....................................................................... 19-9 Dual-Address Transfers ....................................................................
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Contents Paragraph Number 20.1.3 20.1.4 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.5.1 20.3.5.2 20.3.6 20.3.6.1 20.3.7 20.3.7.1 20.3.7.2 20.3.7.3 20.3.7.4 20.3.7.5 20.3.8 Title Page Number Data Synchronization Register (DSR)....................................................................... 20-9 Transmit-on-Demand Register (TODR) .................................................................. 20-10 SCC Buffer Descriptors (BDs) ................................................................
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Contents Paragraph Number 21.18 21.19 21.20 21.21 21.22 Title Page Number SCC UART Transmit Buffer Descriptor (TxBD) ........................................................ 21-18 SCC UART Event Register (SCCE) and Mask Register (SCCM) .............................. 21-19 SCC UART Status Register (SCCS)............................................................................ 21-21 SCC UART Programming Example ............................................................................
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Contents Paragraph Number 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 23.15 23.16 23.17 Title Page Number SCC BISYNC Commands ............................................................................................. 23-4 SCC BISYNC Control Character Recognition.............................................................. 23-5 BISYNC SYNC Register (BSYNC).............................................................................. 23-7 SCC BISYNC DLE Register (BDLE) ......................
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Contents Paragraph Number Title Page Number Chapter 25 SCC Ethernet Mode 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.10 25.11 25.12 25.13 25.14 25.15 25.16 25.17 25.18 25.19 25.20 25.21 Ethernet on the PowerQUICC II.................................................................................... 25-1 Features .......................................................................................................................... 25-2 Connecting the PowerQUICC II to Ethernet .....................
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Contents Paragraph Number Title Page Number Chapter 27 Serial Management Controllers (SMCs) 27.1 27.2 27.2.1 27.2.2 27.2.3 27.2.3.1 27.2.4 27.2.4.1 27.2.4.2 27.2.4.3 27.2.4.4 27.2.4.5 27.2.5 27.2.6 27.3 27.3.1 27.3.2 27.3.3 27.3.4 27.3.5 27.3.6 27.3.7 27.3.8 27.3.9 27.3.10 27.3.11 27.3.12 27.4 27.4.1 27.4.2 27.4.3 27.4.4 27.4.5 27.4.6 27.4.7 27.4.8 27.4.9 27.4.10 Features ..........................................................................................................................
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Contents Paragraph Number 27.4.11 27.5 27.5.1 27.5.2 27.5.2.1 27.5.2.2 27.5.3 27.5.3.1 27.5.3.2 27.5.4 27.5.5 27.5.6 27.5.7 27.5.8 27.5.9 Title Page Number SMC Transparent NMSI Programming Example.................................................... 27-29 The SMC in GCI Mode ............................................................................................... 27-30 SMC GCI Parameter RAM......................................................................................
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Contents Paragraph Number 28.3.4.3 28.3.4.3.1 28.3.4.3.2 28.3.4.3.3 28.3.4.4 28.3.4.4.1 28.3.4.4.2 28.3.4.4.3 28.3.4.4.4 28.3.4.5 28.4 28.5 28.5.1 28.5.2 28.5.3 28.5.4 28.6 28.7 28.8 28.8.1 28.8.1.1 28.8.1.2 28.8.1.2.1 28.8.1.2.2 28.8.1.2.3 28.8.1.2.4 28.8.1.2.5 28.8.1.2.6 28.8.1.2.7 28.8.1.3 28.8.1.4 28.9 28.9.1 28.9.2 28.10 28.10.1 28.10.2 28.11 Title Page Number SS7 Configuration Register—SS7 Mode ............................................................ 28-24 AERM Implementation ..................
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Contents Paragraph Number Title Page Number Chapter 29 Fast Communications Controllers (FCCs) 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.7.1 29.8 29.8.1 29.8.2 29.8.3 29.9 29.10 29.10.1 29.10.1.1 29.10.1.2 29.10.1.3 29.11 29.12 29.12.1 29.12.2 29.12.3 29.12.4 29.12.5 29.13 Overview........................................................................................................................ 29-1 General FCC Mode Registers (GFMRx) ......................................................................
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Contents Paragraph Number 30.2.1.4 30.2.1.5 30.2.2 30.2.2.1 30.2.2.2 30.2.2.2.1 30.2.2.3 30.2.2.4 30.2.3 30.2.4 30.3 30.3.1 30.3.2 30.3.3 30.3.3.1 30.3.3.2 30.3.4 30.3.5 30.3.5.1 30.3.5.2 30.3.5.3 30.3.5.3.1 30.3.5.3.2 30.3.5.4 30.3.6 30.4 30.4.1 30.4.2 30.4.2.1 30.4.2.2 30.4.3 30.4.4 30.5 30.5.1 30.5.1.1 30.5.1.2 30.5.1.3 30.5.2 30.5.2.1 30.5.3 30.6 Title Page Number AAL2 Transmitter Overview.................................................................................
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Contents Paragraph Number 30.6.1 30.6.2 30.6.3 30.6.4 30.6.5 30.6.6 30.6.6.1 30.6.6.2 30.6.6.3 30.6.6.4 30.7 30.7.1 30.8 30.9 30.9.1 30.9.2 30.9.3 30.9.4 30.9.5 30.9.6 30.9.7 30.9.8 30.10 30.10.1 30.10.1.1 30.10.1.2 30.10.1.3 30.10.2 30.10.2.1 30.10.2.2 30.10.2.2.1 30.10.2.2.2 30.10.2.2.3 30.10.2.2.4 30.10.2.2.5 30.10.2.2.6 30.10.2.3 30.10.2.3.1 30.10.2.3.2 30.10.2.3.3 30.10.2.3.4 Title Page Number ATM-Layer OAM Definitions .................................................................................
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Contents Paragraph Number 30.10.2.3.5 30.10.2.3.6 30.10.2.3.7 30.10.2.3.8 30.10.3 30.10.4 30.10.4.1 30.10.4.2 30.10.4.3 30.10.5 30.10.5.1 30.10.5.2 30.10.5.2.1 30.10.5.2.2 30.10.5.2.3 30.10.5.2.4 30.10.5.3 30.10.5.4 30.10.5.5 30.10.5.6 30.10.5.7 30.10.5.8 30.10.5.9 30.10.5.10 30.10.5.11 30.10.5.12 30.10.5.13 30.10.5.14 30.10.5.15 30.10.6 30.10.7 30.11 30.11.1 30.11.2 30.11.3 30.12 30.12.1 30.12.1.1 30.12.2 30.12.2.1 30.12.2.2 Title Page Number AAL2 Protocol-Specific TCT ..................................
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Contents Paragraph Number 30.12.2.3 30.13 30.13.1 30.13.2 30.13.3 30.13.4 30.14 30.15 30.16 30.16.1 30.16.2 30.16.3 Title Page Number UTOPIA Loop-Back Modes................................................................................ 30-87 ATM Registers ............................................................................................................. 30-87 General FCC Mode Register (GFMR).....................................................................
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Contents Paragraph Number 31.8 31.8.1 31.9 31.9.1 31.9.1.1 31.9.2 31.9.2.1 31.10 31.11 31.11.1 31.11.2 31.12 31.12.1 31.12.2 31.13 31.13.1 31.14 31.15 31.16 31.17 31.18 Title Page Number AAL-1 Memory Structure............................................................................................ 31-22 AAL1 CES Parameter RAM.................................................................................... 31-22 Receive and Transmit Connection Tables (RCT, TCT) ......................................
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Contents Paragraph Number 32.4.1 32.4.2 32.4.3 32.4.4 32.4.4.1 32.4.4.2 32.4.4.3 32.4.4.4 32.4.4.5 32.4.4.6 32.4.4.7 32.4.4.8 32.5 32.6 32.7 Title Page Number Receiver Overview .................................................................................................. 32-20 Mapping of PHY | VP | VC | CID............................................................................ 32-21 AAL2 Switching....................................................................................................
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Contents Paragraph Number 33.3.2.4 33.3.3 33.3.3.1 33.3.3.2 33.3.3.2.1 33.3.3.2.2 33.3.3.3 33.4 33.4.1 33.4.2 33.4.2.1 33.4.2.1.1 33.4.2.1.2 33.4.2.2 33.4.2.2.1 33.4.2.2.2 33.4.2.3 33.4.3 33.4.3.1 33.4.4 33.4.4.1 33.4.4.1.1 33.4.4.1.2 33.4.4.1.3 33.4.4.1.4 33.4.4.2 33.4.4.2.1 33.4.4.2.2 33.4.4.2.3 33.4.4.2.4 33.4.5 33.4.5.1 33.4.5.1.1 33.4.5.1.2 33.4.5.1.3 33.4.5.2 33.4.5.2.1 33.4.5.2.2 33.4.5.3 33.4.6 33.4.6.1 Title Page Number Differences in CTC Operation ...............................................
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Contents Paragraph Number 33.4.6.2 33.4.7 33.4.7.1 33.4.7.2 33.4.8 33.4.8.1 33.4.8.2 33.4.8.2.1 33.4.8.2.2 33.4.8.2.3 33.4.8.3 33.4.8.4 33.4.8.5 33.4.8.6 33.4.8.7 33.4.9 33.4.9.1 33.4.9.2 33.4.10 33.5 33.5.1 33.5.2 33.5.3 33.5.3.1 33.5.3.2 33.5.3.3 33.5.3.4 33.5.3.5 33.5.3.6 33.5.3.7 33.5.3.8 33.5.3.9 33.5.3.10 33.5.3.11 33.5.3.12 33.5.3.13 33.5.4 33.5.4.1 33.5.4.2 33.5.4.3 33.5.4.3.1 Title Page Number Delay Compensation Buffers (DCB)...................................................................
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Contents Paragraph Number 33.5.4.3.2 33.5.4.4 33.5.4.4.1 33.5.4.4.2 33.5.4.5 33.5.4.5.1 33.5.4.5.2 33.5.4.6 33.5.4.7 33.5.4.8 33.5.4.9 33.5.4.10 33.5.4.11 33.5.4.11.1 33.5.4.11.2 33.5.4.12 33.5.4.12.1 33.5.4.12.2 33.5.4.13 33.5.4.13.1 33.5.4.13.2 Title Page Number As Responder (RX) ......................................................................................... 33-65 Link Addition Procedure ..................................................................................... 33-65 Rx Steps .....
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Contents Paragraph Number 34.4.2.1 34.4.2.2 34.4.3 34.4.3.1 34.4.3.2 34.4.3.3 34.4.3.4 34.4.3.5 34.4.3.6 34.4.4 34.4.5 34.4.5.1 34.4.5.2 34.5 34.5.1 34.5.2 34.5.3 34.5.4 34.5.5 34.5.6 34.5.7 34.5.8 34.5.9 Title Page Number TC Layer General Event Register (TCGER)....................................................... 34-11 TC Layer General Status Register (TCGSR)....................................................... 34-11 TC Layer Cell Counters.............................................................
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Contents Paragraph Number 35.15 35.16 35.17 35.18 35.18.1 35.18.2 35.19 35.20 Title Page Number Handling Collisions ..................................................................................................... 35-17 Internal and External Loopback................................................................................... 35-17 Ethernet Error-Handling Procedure ............................................................................. 35-17 Fast Ethernet Registers .......................
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Contents Paragraph Number 38.3.1 38.3.2 38.3.3 38.4 38.4.1 38.4.1.1 38.4.2 38.4.3 38.5 38.5.1 38.6 38.7 38.7.1 38.7.1.1 38.7.1.2 38.8 38.9 38.10 Title Page Number The SPI as a Master Device....................................................................................... 38-3 The SPI as a Slave Device ......................................................................................... 38-4 The SPI in Multimaster Operation..........................................................................
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Contents Paragraph Number Title Page Number Chapter 40 Parallel I/O Ports 40.1 40.2 40.2.1 40.2.2 40.2.3 40.2.4 40.2.5 40.3 40.4 40.4.1 40.4.2 40.5 40.6 Features .......................................................................................................................... 40-1 Port Registers ................................................................................................................. 40-1 Port Open-Drain Registers (PODRA–PODRD) ............................................
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Contents Paragraph Number Title Page Number MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 2-1 2-2 2-3 2-4 2-5 2-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 Title Page Number PowerQUICC II Block Diagram............................................................................................. 1-7 PowerQUICC II External Signals ......................................................................................... 1-11 Remote Access Server Configuration .................
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Figures Figure Number 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 Title Page Number Interrupt Table Handling Example........................................................................................ 4-25 SIU External Interrupt Control Register (SIEXR) ................................................................ 4-26 Bus Configuration Register (BCR) ....
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Figures Figure Number 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 Title Page Number 28-Bit Extended Transfer to 32-Bit Port Size ....................................................................... 8-28 Burst Transfer to 32-Bit Port Size.........................................................................................
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Figures Figure Number 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 9-55 9-56 9-57 9-58 9-59 9-60 9-61 9-62 9-63 9-64 9-65 9-66 9-67 9-68 9-69 9-70 9-71 9-72 9-73 9-74 9-75 9-76 Title Page Number PCI Bus Status Register ........................................................................................................ 9-49 Revision ID Register .............................................................................................................
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Figures Figure Number 9-77 9-78 9-79 9-80 9-81 9-82 9-83 9-84 9-85 9-86 9-87 9-88 9-89 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 Title Page Number Inbound Message Interrupt Status Register (IMISR)............................................................ 9-81 Inbound Message Interrupt Mask Register (IMIMR) ...........................................................
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Figures Figure Number 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 11-43 11-44 11-45 11-46 11-47 11-48 11-49 11-50 11-51 11-52 11-53 11-54 11-55 11-56 11-57 11-58 11-59 11-60 11-61 11-62 Title Page Number CL = 2 (2 Clock Cycles) ..................................................................................................... 11-40 LDOTOPRE = 2 (-2 Clock Cycles) ............................................................
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Figures Figure Number 11-63 11-64 11-65 11-66 11-67 11-68 11-69 11-70 11-71 11-72 11-73 11-74 11-75 11-76 11-77 11-78 11-79 11-80 11-81 11-82 11-83 11-84 11-85 11-86 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 14-3 14-4 14-5 14-6 14-7 Title Page Number CS Signal Selection............................................................................................................. 11-75 BS Signal Selection......................................................................................
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Figures Figure Number 14-8 14-9 14-10 14-11 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 17-1 Title Page Number Dual-Port RAM Memory Map............................................................................................ 14-19 RISC Timer Table RAM Usage ..........................................................................................
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Figures Figure Number 17-2 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 21-1 21-2 21-3 21-4 Title Page Number Baud-Rate Generator Configuration Registers (BRGCx)..................................................... 17-2 Timer Block Diagram ...........................................................................................................
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Figures Figure Number 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 22-12 22-13 22-14 22-15 22-16 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 24-1 24-2 24-3 24-4 24-5 25-1 25-2 25-3 Title Page Number Asynchronous UART Transmitter ...................................................................................... 21-10 Protocol-Specific Mode Register for UART (PSMR) .......................................................
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Figures Figure Number 25-4 25-5 25-6 25-7 25-8 25-9 25-10 26-1 26-2 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 27-17 27-18 27-19 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 28-10 28-11 28-12 28-13 Title Page Number Ethernet Address Recognition Flowchart ........................................................................... 25-11 Ethernet Mode Register (PSMR) ........................................................................................
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Figures Figure Number 28-14 28-15 28-16 28-17 28-18 28-19 28-20 28-21 28-22 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 30-1 30-2 30-3 30-4 30-5 30-6 30-7 30-8 30-9 30-10 30-11 30-12 30-13 30-14 30-15 30-16 30-17 30-18 30-19 30-20 30-21 Title Page Number Transmitter Super Channel Example .................................................................................. 28-31 Receiver Super Channel with Slot Synchronization Example............................................
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Figures Figure Number 30-22 30-23 30-24 30-25 30-26 30-27 30-28 30-29 30-30 30-31 30-32 30-33 30-34 30-35 30-36 30-37 30-38 30-39 30-40 30-41 30-42 30-43 30-44 30-45 30-46 30-47 30-48 30-49 30-50 30-51 30-52 30-53 30-54 30-55 30-56 30-57 30-58 30-59 30-60 30-61 30-62 Title Page Number VCI Filtering Enable Bits ................................................................................................... 30-39 Global Mode Entry (GMODE) .................................................................
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Figures Figure Number 30-63 30-64 30-65 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 31-11 31-12 31-13 31-14 31-15 31-16 31-17 31-18 31-19 31-20 31-21 31-22 31-23 31-24 31-25 31-26 31-27 31-28 31-29 31-30 31-31 31-32 32-1 32-2 32-3 32-4 32-5 32-6 Title Page Number COMM_INFO Field ........................................................................................................... 30-93 AAL1 CES SRTS Generation Using External Logic..........................................................
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Figures Figure Number 32-7 32-8 32-9 32-10 32-11 32-12 32-13 32-14 32-15 32-16 32-17 32-18 32-19 32-20 32-21 32-22 32-23 32-24 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 33-13 33-14 33-15 33-16 33-17 33-18 33-19 33-20 33-21 33-22 Title Page Number CPS Tx Queue Descriptor (TxQD) ..................................................................................... 32-14 Buffer Structure Example for CPS Packets.........................................................................
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Figures Figure Number 33-23 33-24 33-25 33-26 33-27 33-28 33-29 33-30 33-31 33-32 33-33 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 34-11 34-12 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 35-9 35-10 36-1 36-2 36-3 36-4 36-5 36-6 36-7 36-8 Title Page Number IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 33-43 IMA Link Receive Control (ILRCNTL).............................................................................
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Figures Figure Number 36-9 37-1 37-2 38-1 38-2 38-3 38-4 38-5 38-6 38-7 38-8 38-9 38-10 38-11 38-12 39-1 39-2 39-3 39-4 39-5 39-6 39-7 39-8 39-9 39-10 39-11 39-12 39-13 39-14 40-1 40-2 40-3 40-4 40-5 40-6 40-7 Title Page Number FCC Status Register (FCCS)............................................................................................... 36-16 In-Line Synchronization Pattern ...........................................................................................
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Figures Figure Number Title Page Number MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Tables Table Number i ii iii iv v 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 Title Page Number Changes to MPC8260 Family Reference Manual, Rev. 1 ................................................. lxxviii Device- and Silicon-Specific Notations............................................................................. lxxviii Acronyms and Abbreviated Terms.................................................
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Tables Table Number 4-23 4-24 4-25 4-26 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 Title Page Number PITR Field Descriptions........................................................................................................ 4-48 PCIBRx Field Descriptions................................................................................................... 4-49 PCIMSKx Field Descriptions ....
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Tables Table Number 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 9-55 9-56 Title Page Number PITARx Field Descriptions ................................................................................................... 9-42 PIBARx Field Descriptions ..................................................................................................
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Tables Table Number 9-57 9-58 9-59 9-60 9-61 9-62 9-63 9-64 9-65 9-66 9-67 9-68 9-69 9-70 9-71 9-72 9-73 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 Title Page Number OPTPR Field Descriptions .................................................................................................... 9-77 IFQPR Field Descriptions ...................................................................................................
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Tables Table Number 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 11-43 11-44 13-1 13-2 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 Title Page Number SDRAM Address Multiplexing (A16–A31) ....................................................................... 11-38 60x Address Bus Partition...................................................................................................
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Tables Table Number 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 16-1 16-2 16-3 16-4 16-5 16-6 16-7 17-1 17-2 17-3 18-1 18-2 18-3 18-4 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 20-1 Title Page Number SIxGMR Field Descriptions................................................................................................ 15-17 SIxMR Field Descriptions ..................................................................................................
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Tables Table Number 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 Title Page Number GSMR_L Field Descriptions ................................................................................................ 20-5 TODR Field Descriptions ...................................................................................................
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Tables Table Number 23-10 23-11 23-12 23-13 23-14 23-15 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 Title Page Number PSMR Field Descriptions.................................................................................................... 23-11 SCC BISYNC RxBD Status and Control Field Descriptions .............................................
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Tables Table Number 27-17 27-18 27-19 27-20 27-21 27-22 27-23 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 28-10 28-11 28-12 28-13 28-14 28-15 28-16 28-17 28-18 28-19 28-20 28-21 28-22 28-23 29-1 29-2 29-3 29-4 29-5 30-1 30-2 30-3 30-4 30-5 30-6 Title Page Number SMC GCI Parameter RAM Memory Map ......................................................................... 27-31 SMC GCI Commands .........................................................................................................
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Tables Table Number 30-7 30-8 30-9 30-10 30-11 30-12 30-13 30-14 30-15 30-16 30-17 30-18 30-19 30-20 30-21 30-22 30-23 30-24 30-25 30-26 30-27 30-28 30-29 30-30 30-31 30-32 30-33 30-34 30-35 30-36 30-37 30-38 30-39 30-40 30-41 30-42 30-43 30-44 30-45 30-46 30-47 Title Page Number Fields and their Positions in RM Cells................................................................................ 30-26 Pre-Assigned Header Values at the UNI .................................................................
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Tables Table Number 30-48 30-49 30-50 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 31-11 31-12 31-13 31-14 31-15 32-1 32-2 32-3 32-4 32-5 32-6 32-7 32-8 32-9 32-10 32-11 32-12 32-13 32-14 32-15 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 Title Page Number FCCE/FCCM Field Descriptions ........................................................................................ 30-91 FTIRRx Field Descriptions.................................................................................................
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Tables Table Number 33-9 33-10 33-11 33-12 33-13 33-14 33-15 33-16 33-17 33-18 33-19 33-20 33-21 33-22 33-23 33-24 33-25 33-26 33-27 33-28 33-29 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 34-11 34-12 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 Title Page Number ICP Cell Template .............................................................................................................. 33-33 IMA Group Receive Table Entry ..............................................................................
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Tables Table Number 35-9 35-10 35-11 36-1 36-2 36-3 36-4 36-5 36-6 36-7 36-8 36-9 36-10 38-1 38-2 38-3 38-4 38-5 38-6 38-7 38-8 38-9 39-1 39-2 39-3 39-4 39-5 39-6 39-7 39-8 39-9 39-10 40-1 40-2 40-3 40-4 40-5 40-6 40-7 40-8 A-1 Title Page Number FCCE/FCCM Field Descriptions ........................................................................................ 35-21 RxBD Field Descriptions ....................................................................................................
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Tables Table Number A-2 A-3 A-4 A-5 Title Page Number User-Level PowerPC SPRs .................................................................................................... A-1 Supervisor-Level PowerPC Registers .................................................................................... A-2 Supervisor-Level PowerPC SPRs .......................................................................................... A-2 MPC8260-Specific Supervisor-Level SPRs ......................................
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About This Book The primary objective of this manual is to help communications system designers build systems using the PowerQUICC II™ and to help software designers provide operating systems and user-level applications to take fullest advantage of the PowerQUICC II. This manual supports the following devices: the MPC8250, the MPC8255, the MPC8260, the MPC8264, the MPC8265, and the MPC8266. Throughout this manual they are collectively referred to as the PowerQUICC II.
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Us Table i. Changes to MPC8260 Family Reference Manual, Rev. 1 Substantive Changes Additional New functionality chapter Description References Previous supplemental documents supported functionality not available on the original PowerQUICC II. They have been incorporated into this manual.
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Table ii. Device- and Silicon-Specific Notations (continued) Format Usage Example Footnotes • Figures—Attached to elements (such as functional blocks). • Figure 4-31 on page 4-39 Figure 4-8 on page 4-8 • Tables—Attached to rows, columns, or entries. Often used • Table 4-15 on page 4-39 to designate variation in bit definition. Text in-line Parenthetical comments placed within a paragraph or bullet item list. Indicates a portion of the text pertains only to specific devices. • Section 1.
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• • Part III, “The Hardware Interface,” describes external signals, clocking, memory control, and power management of the PowerQUICC II. — Chapter 6, “External Signals,” shows a functional pinout of the PowerQUICC II and describes the PowerQUICC II signals. — Chapter 7, “60x Signals,” describes signals on the 60x bus. — Chapter 8, “The 60x Bus,” describes the operation of the bus used by processors that implement the PowerPC architecture.
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— Chapter 22, “SCC HDLC Mode,” describes the PowerQUICC II implementation of HDLC protocol. — Chapter 23, “SCC BISYNC Mode,” describes the PowerQUICC II implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. — Chapter 24, “SCC Transparent Mode,” describes the PowerQUICC II implementation of transparent mode (also called totally transparent mode), which provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation.
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• • • MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. — Chapter 39, “I2C Controller,” describes the PowerQUICC II implementation of the inter-integrated circuit (I2C®) controller, which allows data to be exchanged with other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
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• Application notes—These short documents contain useful information about specific design issues useful to programmers and engineers working with Freescale’s processors. For a current list of documentation, refer to www.freescale.com. Conventions This document uses the following notational conventions: Table 1: Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user. B ld mnemonics Instruction mnemonics are shown in lowercase bold.
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Table iii. Acronyms and Abbreviated Terms (continued) Term Meaning BIST Built-in self test BPU Branch processing unit BRI Basic rate interface. BUID Bus unit ID CAM Content-addressable memory CEPT Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations).
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Table iii.
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Table iii.
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PowerPC Architecture Terminology Conventions Table iv lists certain terms used in this manual that differ from the architecture terminology conventions. Table iv.
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MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Part I Overview Intended Audience Part I is intended for readers who need a high-level understanding of the PowerQUICC II. Contents Part I provides a high-level description of the PowerQUICC II, describing general operation and listing basic features. • Chapter 1, “Overview,” provides a high-level description of PowerQUICC II functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.
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Acronyms and Abbreviations Table I-1 contains acronyms and abbreviations that are used in this document. Table I-1.
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Table I-1.
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MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 1 Overview The PowerQUICC II™ is a versatile communications processor that integrates on one chip a high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The G2 core is an embedded variant of the MPC603e™ microprocessor with 16 Kbytes of instruction cache and 16 Kbytes of data cache.
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Overview • • • • • • • • — Floating-point unit (FPU) supports floating-point arithmetic. — Support for cache locking. Low-power consumption Separate power supply for internal logic (2.5 V) and for I/O (3.3 V) Separate PLLs for G2 core and for the CPM — G2 core and CPM can run at different frequencies for power/performance optimization — Internal G2 core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.
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Overview • • — Three user programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine — Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local) — Dedicated interface logic for SDRAM Disable CPU mode Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals — Interfaces to G2 core through on-chip dual-port RAM and DMA controller.
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Overview • – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One I2C controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to eight TDM interfaces (four on the MPC8250 and the MPC8255) – Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8250 and the MPC8255) – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit
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Overview – Performing HEC error detection and single bit error correction (programmable by user) – Generating loss of cell delineation status/interrupt (LOC/LCD) — — — — Operates with FCC2 (UTOPIA 8) Provides serial loop back mode Cell echo mode is provided Supports both FCC transmit modes – External rate mode—Idle cells are generated by the FCC (microcode) to control data rate. – Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
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Overview — Supports the I2O standard — Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66 MHz, 3.3 V specification — 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port — Makes use of the local bus signals, so there is no need for additional pins 1.
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Overview 16 Kbytes I-Cache I-MMU System Interface Unit (SIU) G2 Core 16 Kbytes D-Cache Bus Interface Unit Communication Processor Module (CPM) PCI Bus2 32 bits, up to 66 MHz 60x-to-PCI Bridge 2 60x-to-Local Bridge D-MMU 60x Bus or Local Bus3 32 bits Memory Controller Timers Interrupt Controller Serial DMAs Dual-Port RAM1 Clock Counter Parallel I/O 32-bit RISC Microcontroller and Program ROM Baud Rate Generators System Functions 7 6,7 MCC1 Virtual IDMAs5 IMA 4 Microcode MCC2 FCC1 F
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Overview The G2 core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. The G2 core performance for the SPEC 95 benchmark for integer operations ranges between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the G2 core is 280 MIPS at 200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz). The G2 core can be disabled.
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Overview 1.2.3 Communications Processor Module (CPM) The CPM contains features that allow the PowerQUICC II to excel in a variety of applications targeted mainly for networking and telecommunication markets. The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP performance and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full-duplex).
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Overview PowerQUICC II initialization code requires changes from the MPC860 initialization code (Freescale provides reference code). 1.3.1 Signals Figure 1-2 shows PowerQUICC II signals grouped by function. Note that many of these signals are multiplexed and this figure does not indicate how these signals are multiplexed. NOTE A bar over a signal name indicates that the signal is active low—for example, BB (bus busy).
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Overview VCCSYN/GNDSYN/VCCSYN1//VDDH/ ⎯⎯⎯> 100 VDD/VSS <⎯⎯> 1 PCI_PAR1 /L_A14 SMI/PCI_FRAME1/L_A15 <⎯⎯> 1 PCI_TRDY1/L_A16 <⎯⎯> 1 CKSTOP_OUT/PCI_IRDY1/L_A17 <⎯⎯> 1 PCI_STOP1/L_A18 <⎯⎯> 1 PCI_DEVSEL1/L_A19 <⎯⎯> 1 PCI_IDSEL1/L_A20 <⎯⎯> 1 PCI_PERR1/L_A21 <⎯⎯> 1 PCI_SERR/1 L_A22 <⎯⎯> 1 PCI_REQ01/L_A23 <⎯⎯> 1 CPCI_HS_ES1/PCI_REQ11/L_A24 <⎯⎯> 1 PCI_GNT01/L_A25 <⎯⎯> 1 CPCI_HS_LED1 /PCI_GNT11/L_A26 <⎯⎯⎯ 1 CPCI_HS_ENUM1/PCI_CLK1/L_A27 <⎯⎯> 1 CORE_SRESET/PCI_RST1/L_A28 <⎯⎯> 1 PCI_INTA1/L_A29 <⎯⎯> 1 PCI_REQ21/L_A30 <⎯
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Overview 1.4 Differences between MPC860 and PowerQUICC II The following MPC860 features are not included in the PowerQUICC II.
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Overview 1.6 PowerQUICC II Configurations The PowerQUICC II offers flexibility in configuring the device for specific applications. The functions mentioned in the above sections are all available in the device, but not all of them can be used at the same time. This does not imply that the device is not fully activated in any given implementation: The CPM architecture has the advantage of using common hardware resources for many different protocols, and applications.
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Overview Table 1-3 shows serial performance for the MPC8250, which does not support ATM (155-Mbps). Table 1-3.
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Overview PowerQUICC II SDRAM/DRAM/SRAM Quad TDM0 60x Bus T1 Framer Channelized Data (up to 256 channels) TDM7 SDRAM/DRAM/SRAM 155 Mbps ATM PHY UTOPIA Multi PHY Local Bus or MII Transceiver ATM Connection Tables (optional) 10/100BaseT or Framer E3 clear channel (takes one TDM) DSP Bank Slow Comm SMC/I2C/SPI/SCC PHY Slaves on Local Bus Figure 1-3. Remote Access Server Configuration In this application, eight TDM ports are connected to external framers.
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Overview 1.7.1.2 Regional Office Router Figure 1-4 shows a regional office router configuration (refer to note at the beginning of Section 1.7, “Application Examples”). PowerQUICC II Quad TDM0 T1 Framer TDM3 SDRAM/DRAM/SRAM MII 10/100BaseT Transceiver 60x Bus Channelized Data (up to 128 channels) 10/100BaseT Slow Comm SMC/I2C/SPI/SCC PHY Figure 1-4.
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Overview PowerQUICC II MII Transceiver 10/100BaseT SDRAM/DRAM/SRAM 60x Bus 155 Mbps ATM PHY SDRAM/DRAM/SRAM 155 Mbps ATM PHY UTOPIA Multi PHY Local Bus or MII Transceiver Data UTOPIA Multi PHY ATM Connection Tables (optional) 10/100BaseT Slow Comm SMC/I2C/SPI/SCC PHY Figure 1-5. LAN-to-WAN Bridge Router Configuration 1.7.1.4 Cellular Base Station Figure 1-6 shows a cellular base station configuration (refer to note at the beginning of Section 1.7, “Application Examples”).
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Overview Here the PowerQUICC II channelizes two E1s (up to 256, 16-Kbps channels). The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred through the parallel bus to the host port of the DSPs with the internal virtual IDMA. The slow communication ports (SCCs, SMCs, I2C, SPI) can be used for management and debug functions. 1.7.1.
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Overview PowerQUICC II TDM0 576 Kbps SONET Transceivers TDM3 SDRAM/DRAM/SRAM 60x Bus Channelized Data (up to 16 channels) MII 10/100BaseT Transceiver SDRAM/DRAM/SRAM Local Bus Slow ATM Connection Tables SMC/I2C/SPI/SCC Comm (10BaseT) PHY Figure 1-8. SONET Transmission Controller Configuration In this application, the PowerQUICC II implements super channeling with the MCC. Nine 64-Kbps channels are combined to form a 576-Kbps channel.
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Overview core. The CP can store large data frames in the local memory without interfering with the operation of the system core. (Refer to note at the beginning of Section 1.7, “Application Examples.”) PowerQUICC II SDRAM/SRAM/DRAM/Flash 60x Bus PHY Communication Channels SDRAM/SRAM/DRAM 155 Mbps ATM PHY UTOPIA Local Bus ATM Connection Tables Figure 1-9. Basic System Configuration 1.7.2.2 High-Performance Communication Figure 1-10 shows a high-performance communication configuration.
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Overview Serial throughput is enhanced by connecting one PowerQUICC II in master or slave mode (with system core enabled or disabled) to another PowerQUICC II in master mode with the core enabled. The core in PowerQUICC II A can access the memory on the local bus of PowerQUICC II B. 1.7.2.3 High-Performance System Microprocessor Figure 1-11 shows a configuration with a high-performance system microprocessor (MPC750). (Refer to note at the beginning of Section 1.7, “Application Examples.
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Overview SDRAM/SRAM/DRAM/Flash PowerQUICC II 60x Bus PHY Communication Channels PCI Bus Host or Agent Figure 1-12. PCI Configuration In this system the local bus is configured as PCI (33-MHz 32-bit data bus version 2.1). The PowerQUICC II can be configured as a host or as an agent on the PCI bus. The 60x bus and PCI bus are asynchronous; there is no frequency dependency between the two. The PCI bus is a 3.3-V bus. 1.7.2.
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Overview to store ATM connection tables. Therefore, an external PCI bridge is necessary. In systems with fewer than 128 active connections or where the ATM average bit rate is lower that 155 Mbps, the local bus may not be necessary to store connection tables, and it may be possible to use it as PCI bus. 1.7.2.6 PowerQUICC II as PCI Agent Figure 1-14 shows the configuration when the PowerQUICC II acts as the PCI agent (refer to note at the beginning of Section 1.7, “Application Examples.”).
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Overview MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 2 G2 Core The PowerQUICC II contains an embedded version of the MPC603e™ microprocessor. This chapter provides an overview of the basic functionality of the processor core.
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G2 Core 64-Bit (Two Instructions) Branch Processing Unit 64-Bit Sequential Fetcher 64-Bit CTR CR LR Instruction Queue System Register Unit 64-Bit (Two Instructions) Dispatch Unit + Instruction Unit 64-Bit 32-Bit Integer Unit / * + GPR File GP Rename Registers 64-Bit Load/Store Unit + XER FloatingPoint Unit / * + FPR File FP Rename Registers FPSCR 32-Bit Completion Unit D MMU SRs DTLB Power Dissipation Control Time Base Counter/ Decrementer JTAG/COP Interface Clock Multiplier Tags D
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G2 Core The processor core is a superscalar processor that can issue and retire as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the processor core makes completion appear sequential. The processor core integrates four execution units—an integer unit (IU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU).
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G2 Core • • • • — LSU for data transfer between data cache and GPRs and FPRs — SRU that executes condition register (CR), special-purpose register (SPR), and integer add/compare instructions — Thirty-two GPRs for integer operands — Thirty-two FPRs for floating-point operands. They also can be used for general operands using floating-point load and store operations.
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G2 Core Figure 2-1 shows how the execution units—IU, BPU, LSU, and SRU—operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. The processor core provides address translation and protection facilities, including an ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. The MMUs translate addresses for cache or external memory accesses.
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G2 Core The BPU contains an adder to compute branch target addresses and three user-control registers—the link register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the branch target address for the Branch Conditional to Count Register (bcctrx) instruction.
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G2 Core Load and store instructions are issued and translated in program order; however, the actual memory accesses can occur out of order. Synchronizing instructions are provided to enforce strict ordering where needed. Cacheable loads, when free of data dependencies, execute in an out-of-order manner with a maximum throughput of one per cycle and a two-cycle total latency. Data returned from the cache is held in a rename register until the completion logic commits the value to a GPR or FPR.
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G2 Core and data. The MMUs also control access privileges for these spaces on block and page granularities. Referenced and changed status is maintained by the processor for each page to assist implementation of a demand-paged virtual memory system. A key bit is implemented to provide information about memory protection violations prior to page table search operations.
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G2 Core Note that there may be registers common to other processors that implement the PowerPC architecture that are not implemented in the PowerQUICC II’s processor core. Unsupported SPR values are treated as follows: • Any mtspr with an invalid SPR executes as a no-op. • Any mfspr with an invalid SPR cause boundedly undefined results in the target register.
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G2 Core SUPERVISOR MODEL—OEA Configuration Registers Hardware Machine State Implementation Register Registers1 USER MODEL UISA General-Purpose Registers GPR0 GPR1 HID0 SPR HID1 SPR HID2 SPR Processor Version Register MSR SPR 287 PVR Memory Management Registers Instruction BAT Registers GPR31 Floating-Point Registers FPR0 FPR1 Software Table Search Registers1 Data BAT Registers IBAT0U SPR 528 DBAT0U SPR 536 DMISS SPR 976 IBAT0L SPR 529 DBAT0L SPR 537 DCMP SPR 977 IBAT1U SPR 530
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G2 Core 2.3.1.2 PowerQUICC II-Specific Registers The set of registers specific to the MPC603e are also shown in Figure 2-2. Most of these are described in the G2 Core Reference Manual and are implemented in the PowerQUICC II as follows: • MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA. These registers facilitate the software required to search the page tables in memory. • IABR. This register facilitates the setting of instruction breakpoints.
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G2 Core Table 2-1. HID0 Field Descriptions (continued) Bits Name Description 7 PAR Disable precharge of ARTRY. 0 Precharge of ARTRY enabled 1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high (negated) state, allowing multiple ARTRY signals to be tied together. If this is done, the system must restore the signals to the high state. 8 DOZE Doze mode enable. Operates in conjunction with MSR[POW]. 1 0 Doze mode disabled. 1 Doze mode enabled.
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G2 Core Table 2-1. HID0 Field Descriptions (continued) Bits Name Description 18 ILOCK Instruction cache lock 0 Normal operation 1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-beat, however, CI still reflects the original state as determined by address translation independent of cache locked or disabled status.
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G2 Core Table 2-1. HID0 Field Descriptions (continued) Bits Name 29–30 — 31 NOOPTI 1 Description Reserved No-op the data cache touch instructions. 0 The dcbt and dcbtst instructions are enabled. 1 The dcbt and dcbtst instructions are no-oped globally. See Chapter 10, “Power Management,” of the G2 Core Reference Manual for more information. See Chapter 4, “Instruction and Data Cache Operation,” of the G2 Core Reference Manual for more information. 2 2.3.1.2.
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G2 Core Table 2-3. HID2 Field Descriptions (continued) Bits 24–26 27–31 2.3.1.2.4 Name Function DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical applications where deterministic behavior is required. See Section 2.4.2.3, “Cache Locking.” — Reserved Processor Version Register (PVR) Software can identify the PowerQUICC II’s processor core by reading the processor version register (PVR). The processor version number for .
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G2 Core 2.3.2.2 PowerPC Instruction Set The PowerPC instructions are divided into the following categories: • Integer instructions—These include arithmetic and logical instructions. — Integer arithmetic — Integer compare — Integer logical — Integer rotate and shift • Floating-point instructions—These include floating-point computational instructions, as well as instructions that affect the FPSCR.
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G2 Core Integer instructions operate on byte, half-word, and word operands. The PowerPC architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. Floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands.
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G2 Core 2.4.1 PowerPC Cache Model The PowerPC architecture does not define hardware aspects of cache implementations. For example, some processors, including the PowerQUICC II’s processor core, have separate instruction and data caches (Harvard architecture), while others implement a unified cache.
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G2 Core 128 Sets Block 0 Address Tag 0 State Words 0–7 Block 1 Address Tag 1 State Words 0–7 Block 2 Address Tag 2 State Words 0–7 Block 3 Address Tag 3 State Words 0–7 8 Words/Block Figure 2-6. Data Cache Organization Because the processor core data cache tags are single-ported, simultaneous load or store and snoop accesses cause resource contention.
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G2 Core tenures of a read operation). Because the processor can dynamically optimize run-time ordering of load/store traffic, overall performance is improved. 2.4.2.2 Instruction Cache The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an address tag, and a valid bit. The instruction cache may not be written to except through a block fill operation caused by a cache miss.
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G2 Core 2.5 Exception Model This section describes the PowerPC exception model and implementation-specific details of the PowerQUICC II core. 2.5.1 PowerPC Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions.
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G2 Core exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler. Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point exception modes, recoverable and nonrecoverable. These are not implemented on the PowerQUICC II. Asynchronous, maskable—The external, system management interrupt (SMI), and decrementer interrupts are maskable asynchronous exceptions.
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G2 Core Table 2-5. Exceptions and Conditions (continued) Exception Type Vector Offset (hex) Causing Conditions Machine check 00200 A machine check is caused by the assertion of the TEA signal during a data bus transaction, assertion of MCP, or an address or data parity error.
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G2 Core Table 2-5.
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G2 Core 2.5.3 Exception Priorities The exception priorities for the processor core are unchanged from those described in the G2 Core reference Manual except for the alignment exception, whose causes are prioritized as follows: 1. Floating-point operand not word-aligned 2. lmw, stmw, lwarx, or stwcx. operand not word-aligned 3. eciwx or ecowx operand misaligned 4. A multiple or string access is attempted with MSR[LE] set 2.
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G2 Core TLB with memory. In the PowerQUICC II, the processor core’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The PowerQUICC II’s core provides hardware assist for software table search operations through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.
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G2 Core 2.7 Instruction Timing The processor core is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is broken into discrete stages. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit at one time.
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G2 Core 2.8 Differences between the PowerQUICC II’s G2 Core and the MPC603e Microprocessor The PowerQUICC II’s processor core is a derivative of the MPC603e microprocessor design. Some changes have been made and are visible either to a programmer or a system designer. Any software designed around an MPC603e is functional when replaced with the PowerQUICC II except for the specific customer-visible changes listed in Table 2-7.
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Chapter 3 Memory Map The PowerQUICC II’s internal memory resources are mapped within a contiguous block of memory. The size of the internal space is 128 Kbytes. The location of this block within the global 4-Gbyte real memory space can be mapped on 128 Kbytes resolution through an implementation-specific special register called the internal memory map register (IMMR). For more information, see Section 4.3.2.7, “Internal Memory Map Register (IMMR).
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page — 24 bits — — 0x10029 Reserved 0x1002C 60x bus arbitration-level register high (first 8 clients) (PPC_ALRH) R/W 32 bits 0x0126_3457 4.3.2.3/4-30 0x10030 60x bus arbitration-level register low (next 8 clients) (PPC_ALRL) R/W 32 bits 0x89AB_CDEF 4.3.2.3/4-30 0x10034 Local arbiter configuration register (LCL_ACR) R/W 8 bits 0x02 4.3.2.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x1012C Option register bank 5 (OR5) R/W 32 bits undefined 11.3.2/11-15 0x10130 Base register bank 6 (BR6) R/W 32 bits 0x0000_0000 11.3.1/11-13 0x10134 Option register bank 6 (OR6) R/W 32 bits undefined 11.3.2/11-15 0x10138 Base register bank 7 (BR7) R/W 32 bits 0x0000_0000 11.3.1/11-13 0x1013C Option register bank 7 (OR7) R/W 32 bits undefined 11.3.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page — 24 bits — — 0x101A5 Reserved 0x101A8 Internal memory map register (IMMR) R/W 32 bits reset configuration 4.3.2.7/4-36 0x101AC PCI base register 0 (PCIBR0)2 R/W 32 bits 0x0000_0000 4.3.4.1/4-48 0x101B0 (PCIBR1)2 R/W 32 bits 0x0000_0000 4.3.4.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x10458 Outbound message register 0 (OMR0)2 R/W 32 bits undefined 9.12.1.2/9-66 0x1045C Outbound message register 1 (OMR1)2 R/W 32 bits undefined 9.12.1.2/9-66 R/W 32 bits 0x0000_0000 9.12.2.1/9-67 (ODR)2 0x10460 Outbound doorbell register 0x10468 Inbound doorbell register (IDR)2 R/W 32 bits 0x0000_0000 9.12.2.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x10608 DMA 2 current descriptor address register (DMACDAR2)2 R/W 32 bits 0x0000_0000 9.13.1.6.3/9-91 0x10610 DMA 2 source address register (DMASAR2)2 R/W 32 bits 0x0000_0000 9.13.1.6.4/9-92 R/W 32 bits 0x0000_0000 9.13.1.6.5/9-92 R/W 32 bits 0x0000_0000 9.13.1.6.6/9-93 R/W 32 bits 0x0000_0000 9.13.1.6.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x108E0 PCI inbound comparison mask register 1 (PICMR1)2 R/W 32 bits 0x0000_0000 9.11.1.17/9-43 0x108E8 PCI inbound translation address register 0 (PITAR0)2 R/W 32 bits 0x0000_0000 9.11.1.15/9-42 R/W 32 bits 0x0000_0000 9.11.1.16/9-42 R/W 32 bits 0x0000_0000 9.11.1.17/9-43 R/W 32 bits undefined 9.9.1.4.4/9-15 R/W 32 bits 0x0000_0000 9.9.1.4.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x10D0C Port A open drain register (PODRA) R/W 32 bits 0x0000_0000 40.2.1/40-1 0x10D10 Port A data register (PDATA) R/W 32 bits 0x0000_0000 40.2.2/40-2 — 12 bytes — — 0x10D14– Reserved 0x10D1F 0x10D20 Port B data direction register (PDIRB) R/W 32 bits 0x0000_0000 40.2.3/40-3 0x10D24 Port B pin assignment register (PPARB) R/W 32 bits 0x0000_0000 40.2.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x10D98 Timer 1 capture register (TCR1) R/W 16 bits 0x0000 18.2.5/18-7 0x10D9A Timer 2 capture register (TCR2) R/W 16 bits 0x0000 18.2.5/18-7 0x10D9C Timer 1 counter (TCN1) R/W 16 bits 0x0000 18.2.6/18-7 0x10D9E Timer 2 counter (TCN2) R/W 16 bits 0x0000 18.2.6/18-7 0x10DA0 Timer 3 mode register (TMR3) R/W 16 bits 0x0000 18.2.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register 0x11030 IDMA 3 event register (IDSR3) 0x11031 Reserved 0x11034 IDMA 3 mask register (IDMR3) 0x11035 Reserved 0x11038 IDMA 4 event register (IDSR4) 0x11039 Reserved 0x1103C IDMA 4 mask register (IDMR4) 0x1103D– Reserved 0x112FF R/W Size Reset Section/Page R/W 8 bits 0x00 19.8.4/19-24 — 24 bits — — R/W 8 bits 0x00 19.8.4/19-24 — 24 bits — — R/W 8 bits 0x00 19.8.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page — 24 bits — — 30.13.4/30-91 (ATM) 33.4.2.1.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 30.13.4/30-91 (ATM) 33.4.2.1.2/33-26 (IMA) 0x1133C FCC2 transmit internal rate registers for PHY0 (FTIRR2_PHY0) R/W 8 bits 0x00 0x1133D FCC2 transmit internal rate registers for PHY1 (FTIRR2_PHY1) R/W 8 bits 0x00 0x11133E FCC2 transmit internal rate registers for PHY2 (FTIRR2_PHY2) R/W 8 bits 0x00 R/W 8 bits 0x00 R/W 32 bits 0x0000_0000 29.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page R/W 16 bits 0x0000 34.4.1.1/34-7 R/W 16 bits 0x0000 34.4.1.2/34-9 R/W 16 bits 0x0000 34.4.1.3/34-10 R/W 16 bits 0x0000 34.4.1.4/34-11 R/W 16 bits 0x0000 34.4.1.4/34-11 R/W 16 bits 0x0000 34.4.3.6/34-13 R/W 16 bits 0x0000 34.4.3.4/34-12 R/W 16 bits 0x0000 34.4.3.5/34-12 R/W 16 bits 0x0000 34.4.3.2/34-12 R/W 16 bits 0x0000 34.4.3.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x1144C TC3 corrected cells counter (TC_CCC3)4 R/W 16 bits 0x0000 34.4.3.4/34-12 0x1144E TC3 idle cells counter (TC_ICC3)4 R/W 16 bits 0x0000 34.4.3.5/34-12 R/W 16 bits 0x0000 34.4.3.2/34-12 R/W 16 bits 0x0000 34.4.3.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 0x114A2 TC6 cell delineation state machine register (CDSMR6)4 R/W 16 bits 0x0000 34.4.1.2/34-9 0x114A4 TC6 event register (TCER6)4 R/W 16 bits 0x0000 34.4.1.3/34-10 R/W 16 bits 0x0000 34.4.1.4/34-11 R/W 16 bits 0x0000 34.4.1.4/34-11 R/W 16 bits 0x0000 34.4.3.6/34-13 R/W 16 bits 0x0000 34.4.3.4/34-12 R/W 16 bits 0x0000 34.4.3.5/34-12 R/W 16 bits 0x0000 34.4.3.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register 0x114F2 TC8 error cells counter (TC_ECC8)4 0x114F4 Reserved R/W Size Reset Section/Page R/W 16 bits 0x0000 34.4.3.3/34-12 — 12 bytes — — R 16 bits 0x0000 34.4.2.2/34-11 R/W 16 bits 0x0000 34.4.2.1/34-11 17.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 14.6.4/14-24 0x119D6 CP timers event register (RTER) R/W 16 bits 0x0000_0000 0x119DA CP timers mask register (RTMR) R/W 16 bits 0x0000_0000 0x119DC CP time-stamp timer control register (RTSCR) — 16 bits 0x0000 0x119DE Reserved R/W 16 bits — 0x119E0 CP time-stamp register (RTSR) R/W 32 bits 0x0000 14.3.9/14-11 17.1/17-2 14.3.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) 0x11A17 Register SCC1 status register (SCCS1) 0x11A18– Reserved 0x11A1F R/W Size Reset Section/Page R/W 8 bits 0x00 21.20/21-21 (UART) 22.12/22-14 (HDLC) 23.15/23-16 (BISYNC) 24.13/24-12 (Transparent) — 8 bytes — — 20.1.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) 0x11A37 Register SCC2 status register (SCCS2) 0x11A38– Reserved 0x11A3F R/W Size Reset Section/Page R/W 8 bits 0x00 21.20/21-21 (UART) 22.12/22-14 (HDLC) 23.15/23-16 (BISYNC) 24.13/24-12 (Transparent) — 8 bytes — — 20.1.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) 0x11A57 Register SCC3 status register (SCCS3) 0x11A58– Reserved 0x11A5F R/W Size Reset Section/Page R/W 8 bits 0x00 21.20/21-21 (UART) 22.12/22-14 (HDLC) 23.15/23-16 (BISYNC) 24.13/24-12 (Transparent) — 8 bytes — — 20.1.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register 0x11A78– Reserved 0x11A7F R/W Size Reset Section/Page — 8 bytes — — R/W 16 bits 0x0000 27.2.1/27-2 — 16 bits — — R/W 8 bits 0x00 — 24 bits — R/W 8 bits 0x00 27.3.11/27-18 (UART) 27.4.10/27-28 (Transparent) 27.5.9/27-34 (GCI) — 7 bytes — — R/W 16 bits 0x0000 27.2.1/27-2 — 16 bits — — R/W 8 bits 0x00 — 24 bits — R/W 8 bits 0x00 27.3.11/27-18 (UART) 27.4.10/27-28 (Transparent) 27.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page — 8 bits — — 0x11B03 Reserved 0x11B04 CPM mux FCC clock route register (CMXFCR) R/W 32 bits 0x0000_0000 16.4.4/16-13 0x11B08 CPM mux SCC clock route register (CMXSCR) R/W 32 bits 0x0000_0000 16.4.5/16-16 0x11B0C CPM mux SMC clock route register (CMXSMR) R/W 8 bits 0x00 16.4.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) Register R/W Size Reset Section/Page 15.5.2/15-17 SI2 Registers 0x11B40 SI2 TDMA2 mode register (SI2AMR) R/W 16 bits 0x0000 0x11B42 SI2 TDMB2 mode register (SI2BMR) R/W 16 bits 0x0000 0x11B44 SI2 TDMC2 mode register (SI2CMR) R/W 16 bits 0x0000 0x11B46 SI2 TDMD2 mode register (SI2DMR) R/W 8 bits 0x0000 0x11B48 SI2 global mode register (SI2GMR) R/W 8 bits 0x00 15.5.
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Memory Map Table 3-1. Internal Memory Map (continued) Address (offset) R/W Size Reset Section/Page R/W 512 bytes undefined 15.4.3/15-10 0x12E00– Reserved 0x12FFF — 512 bytes — — 0x13000– Reserved 0x137FF — 2048 bytes — — 0x13800– Reserved 0x13FFF — 2048 bytes — — 0x12C00– 0x12DFF 1 2 3 4 5 6 Register SI 2 receive routing RAM (SI2RxRAM) .25 µm (HiP4) devices only. Reserved on.29 µm (HiP3) devices. MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
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Part II Configuration and Reset Intended Audience Part II is intended for system designers and programmers who need to understand the operation of the PowerQUICC II at start up. It assumes understanding of the PowerPC programming model described in the previous chapters and a high level understanding of the PowerQUICC II. Contents Part II describes start-up behavior of the PowerQUICC II.
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example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value x n Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table II-1.
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Chapter 4 System Interface Unit (SIU) The system interface unit (SIU) consists of several functions that control system start-up and initialization, as well as operation, protection, and the external system bus.
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System Interface Unit (SIU) generates the clock signals used by the SIU and other PowerQUICC II modules. The SIU clocking scheme supports stop and normal modes. The 60x bus interface is a standard pipelined bus. The PowerQUICC II allows external bus masters to request and obtain system bus mastership. Chapter 8, “The 60x Bus,” describes bus operation, but 60x bus configuration is explained in this section.
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System Interface Unit (SIU) Figure 4-2 is a block diagram of the system configuration and protection logic. Module Configuration Bus clock/8 Bus Monitors timersclk Periodic Interrupt Timer Bus Clock Software Watchdog Timer timersclk Time Counter System Reset Core’s MCP TEA Interrupt System Reset Core’s MCP Interrupt Figure 4-2. System Configuration and Protection Logic Many aspects of system configuration are controlled by several SIU module configuration registers, described in Section 4.3.
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System Interface Unit (SIU) The user should select external clock and/or BRG1 programming to yield either 4 MHz or 32 KHz at this point. PISCR[PTF] PC[26] Divide by 4 timersclk for PIT Divide by 512 Ports Programming CPM clock timersclk for TMCNT PC[27] BRG1 PC[29] Ports Programming TMCNTSC[TCF] PC[25] Figure 4-3. Timers Clock Generation For details, see Section 40.2.4, “Port Pin Assignment Register (PPAR).
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System Interface Unit (SIU) SEC Interrupt timersclk for TMCNT (8,192 Hz) Divide by 8,192 32-Bit Counter = Alarm Interrupt 32-Bit Register Figure 4-4. TMCNT Block Diagram Section 4.3.2.15, “Time Counter Register (TMCNT),” describes the time counter register. 4.1.4 Periodic Interrupt Timer (PIT) The periodic interrupt timer consists of a 16-bit counter clocked by timersclk.
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System Interface Unit (SIU) This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF). 4.1.5 Software Watchdog Timer The SIU provides the software watchdog timer option to prevent system lock in case the software becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the SYPCR, described in Section 4.3.2.8, “System Protection Control Register (SYPCR).” The software watchdog timer is enabled after reset to cause a hard reset if it times out.
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System Interface Unit (SIU) SWSR Service Logic SWE Bus Clock Clock Disable SYPCR[SWTC] Divide By 2,048 Reload MUX 16-Bit SWR/Decrementer Rollover = 0 SWP Time-out Reset or MCP Figure 4-7. Software Watchdog Timer Block Diagram In Figure 4-7, the range is determined by SYPCR[SWTC]. The value in SWTC is then loaded into a 16-bit decrementer clocked by the system clock. An additional divide-by-2,048 prescaler is used when needed. The decrementer begins counting when loaded with a value from SWTC.
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System Interface Unit (SIU) 4.2.1 Interrupt Configuration Figure 4-8 shows the PowerQUICC II interrupt structure. The interrupt controller receives interrupts from internal sources, such as the PIT or TMCNT, from the CPM, the PCI bridge (with its own interrupt controller), and from external pins (port C parallel I/O pins).
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System Interface Unit (SIU) If the software watchdog timer is programmed to generate an interrupt, it always generates a machine check interrupt to the core. The external IRQ0 can generate MCP as well. Note that the core takes the machine check interrupt when MCP is asserted; it takes an external interrupt for any other interrupt asserted by the interrupt controller. The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block event are also maskable.
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System Interface Unit (SIU) relative ordering of the interrupts, but, in general, relative priorities are as shown. A single interrupt priority number is associated with each table entry. Note that the group and spread options, shown with YCC entries in Table 4-2, are described in Section 4.2.2.1, “SCC, FCC, and MCC Relative Priority.” Table 4-2.
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System Interface Unit (SIU) Table 4-2.
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System Interface Unit (SIU) Table 4-2.
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System Interface Unit (SIU) • Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed in the SICR but cannot be changed dynamically. 4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority The PowerQUICC II has seven general-purpose interrupt requests (IRQs), five of which, with the PIT, the PCI interrupt controller, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have fixed priority. 4.2.2.
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System Interface Unit (SIU) SCCE SIPNR Event Bit 13 Input (or 13 Event Bits) Request to the core (Other Unmasked Requests) SCCM SIMR Mask Bit Mask Bit Figure 4-9. Interrupt Request Masking 4.2.4 Interrupt Vector Generation and Calculation Pending unmasked interrupts are presented to the core in order of priority. The interrupt vector that allows the core to locate the interrupt service routine is made available to the core by reading SIVEC.
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System Interface Unit (SIU) Table 4-3.
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System Interface Unit (SIU) Table 4-3.
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System Interface Unit (SIU) Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR is cleared on system reset so pins left floating do not cause false interrupts. 4.3 Programming Model The SIU registers are grouped into the following three categories: • Interrupt controller registers. These registers control configuration, prioritization, and masking of interrupts. They also include registers for determining the interrupt sources.
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System Interface Unit (SIU) The SICR register bits are described in Table 4-4. Table 4-4. SICR Field Descriptions Bits Name Description 0–1 — Reserved, should be cleared. 2–7 HP Highest priority. Specifies the 6-bit interrupt number of the single interrupt controller interrupt source that is advanced to the highest priority in the table. HP can be modified dynamically. To retain the original priority, program HP to the interrupt number assigned to XSIU1. 8–13 — Reserved, should be cleared.
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System Interface Unit (SIU) Table 4-5. SIPRR Field Descriptions Bits Name Description 0–2 XS1P–XSIU1 Priority order. Defines which PIT/TMCNT/PCI/IRQs asserts its request in the XSIU1 priority position. The user should not program the same PIT/TMCNT/PCI/IRQs to more than one priority position (1–8). These bits can be changed dynamically. 000 TMCNT asserts its request in the XSIU1 position. 001 PIT asserts its request in the XSIU1 position.
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System Interface Unit (SIU) Table 4-6. SCPRR_H Field Descriptions Bits Name 0–2 XC1P–XCC1 Priority order. Defines which FCC/MCC asserts its request in the XCC1 priority position. The user should not program the same FCC/MCC to more than one priority position (1–8). These bits can be changed dynamically. 000 FCC1 asserts its request in the XCC1 position. 001 FCC2 asserts its request in the XCC1 position. 010 FCC3 asserts its request in the XCC1 position.1 011 XCC1 position not active.
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System Interface Unit (SIU) Table 4-7. SCPRR_L Field Descriptions Bits Name Description 0–2 YC1P–YCC1 Priority order. Defines which SCC asserts its request in the YCC1 priority position. Do not program the same SCC to multiple priority positions. This field can be changed dynamically. 000 SCC1 asserts its request in the YCC1 position. 001 SCC2 asserts its request in the YCC1 position. 010 SCC3 asserts its request in the YCC1 position. 011 SCC4 asserts its request in the YCC1 position.
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System Interface Unit (SIU) 0 1 2 Field FCC1 FCC2 FCC3 3 — 4 5 6 MCC1 MCC2 7 — 8 9 10 11 SCC1 SCC2 SCC3 SCC4 12 13 2 TC 15 — 0000_0000_0000_00001 Reset R/W R/W Addr 0x0x10C0C 16 Field I2C 17 SPI 18 19 20 21 22 23 24 25 RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA 26 — 27 28 29 30 TIMER1 TIMER2 TIMER3 TIMER4 — 0000_0000_0000_0001 Reset R/W R/W Addr 0x10C0E 31 01 1 These 2 fields are zero after reset because their corresponding mask register bits are clear
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System Interface Unit (SIU) 0 1 2 3 4 5 6 7 8 9 10 11 12 Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 Reset R/W Addr 0x0x10C1C 16 17 — 18 19 20 21 22 23 24 28 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reset 15 PC14 PC15 29 30 31 TMCNT PIT PCI 1 11 12 13 SCC4 TC3 27 28 — 0000_0000_0000_0000 R/W R/W Addr 0x10C1E 1 PC13 14 0000_0000_0000_0000 R/W Field 13 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices Figure 4-16.
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System Interface Unit (SIU) 4.3.1.6 SIU Interrupt Vector Register (SIVEC) The SIU interrupt vector register (SIVEC), shown in Figure 4-18, contains an 8-bit code representing the unmasked interrupt source of the highest priority level.
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System Interface Unit (SIU) INTR: • • • INTR: • • • Save state R3 <- @ SIVEC R4 <-- BASE OF BRANCH TABLE Save state R3 <- @ SIVEC R4 <-- BASE OF BRANCH TABLE ••• ••• lbz add mtspr bctr RX, R3 (0) # load as byte RX, RX, R4 CTR, RX BASE b Routine1 lhz add mtspr bctr BASE RX, R3 (0) # load as half RX, RX, R4 CTR, RX 1st Instruction of Routine1 • BASE + 4 b Routine2 BASE + 400 1st Instruction of Routine2 • BASE + 8 b Routine3 BASE + 800 1st Instruction of Routine3 BASE + C b Routine4
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System Interface Unit (SIU) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC EDPC EDPC EDPC EDPC EDPC 10 Reset 11 12 13 14 15 0000_0000_0000_0000 R/W R/W Addr 0x0x10C24 16 Field EDI0 17 18 19 20 21 22 23 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7 Reset 24 31 — 0000_0000_0000_0000 R/W R/W Addr R 0x10C26 Figure 4-20. SIU External Interrupt Control Register (SIEXR) Table 4-8 describes SIEXR fields.
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System Interface Unit (SIU) 0 1 Field EBM Reset 3 1 4 APD 5 L2C 7 L2D 18 NPQM 19 20 — Reset 2 10 PLDP — DAM 11 12 13 14 15 EAV ETM LETM EPAR LEPAR R/W 16 1 9 000_0000_0000_0000 — R/W Field 8 21 22 EXDD 25 — 26 27 2 SPAR ISPS 0000_0000_000 28 1 — R/W R/W Addr 0x0x10024 31 — 0000 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.” MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Figure 4-21.
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System Interface Unit (SIU) Table 4-9. BCR Field Descriptions (continued) Bits Name Description 11 EAV Enable address visibility. Normally, when the PowerQUICC II is in single-PowerQUICC II bus mode, the bank select signals for SDRAM accesses are multiplexed on the 60x bus address lines. So, for SDRAM accesses, the internal address is not visible for debug purposes. However the bank select signals can also be driven on dedicated pins (see SIUMCR[APPC]).
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System Interface Unit (SIU) Table 4-9. BCR Field Descriptions (continued) Bits Name 21 Description EXDD External master delay disable. Generally, the PowerQUICC II adds one clock cycle delay for each external master access to a region controlled by the memory controller. This occurs because the external master drives the address on the external pins (compared to internal master, like PowerQUICC II’s DMA, which drives the address on an internal bus in the chip).
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System Interface Unit (SIU) Table 4-10. PPC_ACR Field Descriptions Bits Name 0–1 — 2 DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for 60x bus master-initiated data operations. This is the minimum delay between TS and DBG. 0 DBG is asserted with TS if the data bus is free. 1 DBG is asserted one cycle after TS if the data bus is not busy. See Section 8.5.1, “Data Bus Arbitration.” 3 EARB External arbitration. 0 Internal arbitration is performed. See Section 8.3.
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System Interface Unit (SIU) PPC_ALRL, shown in Figure 4-24, defines arbitration priority of 60x bus masters 8–15. Priority field 0 is the highest-priority arbitration level. For information about the PowerQUICC II bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10.
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System Interface Unit (SIU) Table 4-11. LCL_ACR Field Descriptions (continued) Bits Name 4–7 PRKM Parking master. Defines the parked master.
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System Interface Unit (SIU) 0 3 4 7 8 11 12 15 Field Priority Field 8 Priority Field 9 Priority Field 10 Priority Field 11 Reset 1000 1001 1010 1011 R/W R/W Addr 0x0x1003C 16 19 20 23 24 27 28 31 Field Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Reset 1100 1101 1110 1111 R/W R/W Addr 0x1003E Figure 4-27. LCL_ALRL 4.3.2.
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System Interface Unit (SIU) Table 4-12. SIUMCR Register Field Descriptions (continued) Bits Name Description 2 PBSE Parity byte select enable. 0 Parity byte select is disabled. GPL4 output of UPM is available for memory control. 1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the PowerQUICC II. Note: Should not be set if BRx[DECC] = 00. Refer to Section 11.3.1, “Base Registers (BRx).” 3 CDIS Core disable. 0 The PowerQUICC II core is enabled.
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System Interface Unit (SIU) Table 4-12. SIUMCR Register Field Descriptions (continued) Bits Name Description 10–11 APPC Address parity pins configuration. Note that during power on reset the MODCK pins are used for PLL configuration. The pin multiplexing indicated in the table applies only to normal operation. Selection between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin is INT_OUT; otherwise it is IRQ7.
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System Interface Unit (SIU) Table 4-12. SIUMCR Register Field Descriptions (continued) Bits Name Description 18 LPBSE Local bus parity byte select enable. 0 Parity byte select is disabled. LGPL4 output of UPM is available for memory control. 1 Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the PowerQUICC II. 19–31 — 4.3.2.7 Reserved, should be cleared.
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System Interface Unit (SIU) Table 4-13. IMMR Field Descriptions Bits Name Description 0–14 ISB Internal space base. Defines the base address of the internal memory space. The value of ISB is configured at reset to one of eight addresses; it can then be changed to any value by the software. The default is 0, which maps to address 0x0000_0000. (See Section 5.4.1, “Hard Reset Configuration Word.”) ISB defines the 15 msbs of the memory map register base address.
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System Interface Unit (SIU) Table 4-14 describes SYPCR fields. Table 4-14. SYPCR Field Descriptions Bits Name Description 0–15 SWTC Software watchdog timer count. Contains the count value for the software watchdog timer. 16–23 BMT 24 PBME 60x bus monitor enable. 0 60x bus monitor is disabled. 1 The 60x bus monitor is enabled. 25 LBME Local bus monitor enable. 0 Local bus monitor is disabled. 1 The local bus monitor is enabled. 26–28 — 29 SWE Software watchdog enable.
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System Interface Unit (SIU) 0 Field BM 1 2 ISBE PAR 3 4 ECC2 5 ECC1 WP Reset 9 EXT TC R/W R/W Addr 0x0x10040 Field — 17 DMD 18 — 19 20 1 21 2 22 2 23 2 PCIMCP DER IRQ0 SWD ADO Reset 2 7 10 11 — 15 TT 0000_0000_0000_0000 16 1 6 24 2 31 ECNT 0000_0000_0000_0000 R/W R/W Addr 0x10042 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Reserved on .29µm (HiP3) Rev A.1 devices.
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System Interface Unit (SIU) Table 4-15. TESCR1 Field Descriptions (continued) Bits Name Description 7–9 TC Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA or MCP. See Section 8.4.3.2, “Transfer Code Signals TC[0–2],” for a description of the various transfer codes. 10 — Reserved, should be cleared. 11–15 TT Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA or MCP. See Section 8.4.3.
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System Interface Unit (SIU) 0 Field 1 — 2 REGS DPR 3 — 4 PCI0 5 1 PCI1 1 Reset 6 7 8 — LCL PB 0000_0000_0000_0000 R/W R/W Addr 0x0x10044 16 27 Field BNK Reset 1 15 28 31 — 0000_0000_0000_0000 R/W R/W Addr 0x10046 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Note: all bits are status bits and are cleared by writing 1s. Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2) The TESCR2 register is described in Table 4-16.
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System Interface Unit (SIU) 4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) The local bus transfer error status and control register 1 (L_TESCR1) is shown in Figure 4-33. 0 Field BM 1 2 — PAR 3 4 — 5 6 WP — Reset 9 TC R/W R/W Addr 0x0x10048 Field 10 11 — 15 TT 0000_0000_0000_0000 16 — 17 DMD 18 19 — 20 DER 21 31 1 Reset 1 7 — 0000_0000_0000_0000 R/W R/W Addr 0x1004A .29µm (HiP3) Rev B.3 silicon and forward. Reserved on .29µm Rev A.
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System Interface Unit (SIU) Table 4-17. L_TESCR1 Field Descriptions (continued) Bits Name 17 DMD 18–19 — Reserved, should be cleared. 20 — .29µm (HiP3) Rev A.1 silicon: reserved, should be cleared. DER 21–31 4.3.2.13 — Description Data errors disable. Setting this bit disables parity errors on the local bus. .29µm (HiP3) Rev B.3 silicon and forward: Data error. Set when a core machine check is asserted due to parity errors in the local bus. Reserved, should be cleared.
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System Interface Unit (SIU) 4.3.2.14 Time Counter Status and Control Register (TMCNTSC) The time counter status and control register (TMCNTSC), shown in Figure 4-35, is used to enable the different TMCNT functions and for reporting the source of the interrupts. The register can be read at any time. Status bits are cleared by writing ones; writing zeros does not affect the value of a status bit. .
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System Interface Unit (SIU) 0 15 Field TMCNT Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x10224 16 31 Field TMCNT Reset 0000_0000_0000_0000 R/W R/W Addr 0x10226 Figure 4-36. Time Counter Register (TCMCNT) 4.3.2.16 Time Counter Alarm Register (TMCNTAL) The time counter alarm register (TMCNTAL), shown in Figure 4-37, holds a value (ALARM). When the value of TMCNT equals ALARM, a maskable interrupt is generated.
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System Interface Unit (SIU) 4.3.3 Periodic Interrupt Registers The periodic interrupt registers are described in the following sections. 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR) The periodic interrupt status and control register (PISCR), shown in Figure 4-38, contains the interrupt request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded in a modulus counter.
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System Interface Unit (SIU) 0 15 Field PITC Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x10244 16 31 Field — Reset 0000_0000_0000_0000 R/W R/W Addr 0x10246 Figure 4-39. Periodic interrupt Timer Count Register (PITC) Table 4-22 describes PITC fields. Table 4-22. PITC Field Descriptions Bits Name 0–15 PITC 16–31 — 4.3.3.3 Description Periodic interrupt timing count. Bits 0–15 are defined as the PITC, which contains the count for the periodic timer.
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System Interface Unit (SIU) Table 4-23 describes PITR fields. Table 4-23. PITR Field Descriptions Bits Name 0–15 PITC 16–31 — 4.3.4 Description Periodic interrupt timing count. Bits 0–15 are defined as the PIT. It contains the current count remaining for the periodic timer. Writes have no effect on this field. Reserved, should be cleared. PCI Control Registers NOTE This section applies only to the MPC8250, the MPC8265, and the MPC8266.
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System Interface Unit (SIU) Table 4-24 describes PCIBRx fields. Table 4-24. PCIBRx Field Descriptions Bits Name Description 0–16 BA Base Address. The upper 17 bits of each base address register are compared to the address on the 60x bus address bus to determine if the access should be claimed by the PCI bridge. Used with PCIMSKx[AM] 17–30 — Reserved. Should be cleared. 31 V Valid bit. Indicates that the contents of the PCIBRx and PCIMSKx pairs are valid.
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System Interface Unit (SIU) Table 4-26.
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Chapter 5 Reset The PowerQUICC II has several inputs to the reset logic: • Power-on reset (PORESET) • External hard reset (HRESET) • External soft reset (SRESET) • Software watchdog reset • Bus monitor reset • Checkstop reset • JTAG reset All of these reset sources are fed into the reset controller and, depending on the source of the reset, different actions are taken. The reset status register, described in Section 5.2, “Reset Status Register (RSR),” indicates the last sources to cause a reset. 5.
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Reset 5.1.1 Reset Actions The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration.
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Reset Figure 5-4 shows the power-on reset flow. PORESET Input External pin is asserted for min 16 RSTCONF is sampled for master determination PORESET Internal MODCK[1–3] are sampled. MODCK_HI bits are ready for PLL HRESET Output PLL is locked (no external indication) SRESET Output PLL locking period PORESET to internal logic is extended for 1024 CLKIN. HRESET /SRESET are extended for 512/515 CLKIN (respectively), from PLL lock time. Interval depends on PLL locking time.
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Reset 5.2 Reset Status Register (RSR) The reset status register (RSR), shown in Figure 5-2, is memory-mapped into the PowerQUICC II’s SIU register map. 0 15 Field — R/W R/W Reset 0000_0000_0000_0000 Addr 0x10C90 16 25 Field — 26 27 JTRS CSRS R/W 28 SWRS 29 30 31 BMRS ESRS EHRS R/W Reset 0000_0000_0000_0011 Addr 0x10C92 Figure 5-2. Reset Status Register (RSR) Table 5-3 describes RSR fields. Table 5-3.
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Reset Table 5-3. RSR Field Descriptions (continued) Bits Name Function 30 ESRS External soft reset status. When an external soft reset event is detected, ESRS is set and it remains that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect). 0 No external soft reset event has occurred 1 An external soft reset event has occurred 31 EHRS External hard reset status.
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Reset Table 5-4. RMR Field Descriptions Bits Name 0–30 — 31 5.4 Function Reserved, should be cleared. CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception conditions. Setting CSRE configures the chip to perform a hard reset sequence whenever the core enters checkstop state. 0 Reset not generated when core enters checkstop state. 1 Reset generated when core enters checkstop state. Note: When the core is disabled, CSRE must be cleared.
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Reset Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems (continued) Configured Device RSTCONF Connection Sixth configuration slave A5 Seventh configuration slave A6 The configuration words for all PowerQUICC IIs are assumed to reside in an EPROM connected to CS0 of the configuration master.
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Reset 5.4.1 Hard Reset Configuration Word The contents of the hard reset configuration word are shown in Figure 5-4. 0 1 2 3 Field EARB EXMC CDIS EBM 4 5 BPS Reset 17 BMS BBD Reset 1 7 CIP ISPS 8 9 L2CPC 10 11 DPPC 12 13 — 15 ISB 0000_0000_0000_0000 16 Field 6 18 19 MMR 20 21 22 LBPC 23 APPC 24 25 CS10PC 26 27 ALD_EN 1 — 28 31 MODCK_H 0000_0000_0000_0000 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Figure 5-4.
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Reset Table 5-7. Hard Reset Configuration Word Field Descriptions (continued) Bits Name Description 13–15 ISB Initial internal space base select. Defines the initial value of IMMR[0–14] and determines the base address of the internal memory space. 000 0x0000_0000 001 0x00F0_0000 010 0x0F00_0000 011 0x0FF0_0000 100 0xF000_0000 101 0xF0F0_0000 110 0xFF00_0000 111 0xFFF0_0000 See Section 4.3.2.7, “Internal Memory Map Register (IMMR).” 16 BMS Boot memory space. Defines the initial value for BR0[BA].
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Reset 1 The user should exercise caution when changing this bit. This bit has an immediate effect on the external bus and may result in unstable system operation. 5.4.2 Hard Reset Configuration Examples This section presents some examples of hard reset configurations in different systems. 5.4.2.1 Single PowerQUICC II with Default Configuration This is the simplest configuration scenario. It can be used if the default values achieved by clearing the hard reset configuration word are desired.
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Reset PORESET Configuration Master Chip HRESET Address Bus EPROM Control Signals VCC Boot EPROM A[..] A[0–31] D[0–31] RSTCONF Data Bus PORESET D[0–7] Figure 5-6. Configuring a Single Chip from EPROM 5.4.2.3 Multiple PowerQUICC IIs Configured from Boot EPROM For a complex system with multiple PowerQUICC II devices that may each be configured differently, configuration is done by assigning one configuration master and multiple configuration slaves.
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Reset PORESET EPROM Control Signals Configuration Master Chip HRESET Address Bus VCC Boot EPROM A[..] A[0–31] PORESET D[0–7] D[0–31] HRESET PORESET Configuration Slave Chip 1 D[0–31] RSTCONF HRESET PORESET Data Bus RSTCONF A0 Configuration Slave Chip 2 D[0–31] RSTCONF A1 Configuration Slave Chip 7 HRESET PORESET D[0–31] RSTCONF A6 Figure 5-7. Configuring Multiple Chips In this system, the configuration master initially reads its own configuration word.
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Reset shows, this complex configuration is done without additional glue logic. The configuration master controls the whole process by asserting the EPROM control signals and the system’s address signals as needed. 5.4.2.4 Multiple PowerQUICC IIs in a System with No EPROM In some cases, the configuration master capabilities of the PowerQUICC II cannot be used. This can happen for example if there is no boot EPROM in the system or the boot EPROM is not controlled by an PowerQUICC II.
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Reset MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Part III The Hardware Interface Intended Audience Part III is intended for system designers who need to understand how each PowerQUICC II signal works and how those signals interact. Contents Part III describes external signals, clocking, memory control, and power management of the PowerQUICC II. It contains the following chapters: • Chapter 6, “External Signals,” shows a functional pinout of the PowerQUICC II and describes the PowerQUICC II signals.
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MPC82xx Documentation Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes. Conventions This document uses the following notational conventions: Bold entries in figures and tables showing registers and parameter RAM should Bold be initialized by the user. mnemonics Instruction mnemonics are shown in lowercase bold.
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Table III-1.
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Table III-1. Acronyms and Abbreviated Terms (continued) Term Meaning PRI Primary rate interface Rx Receive SCC Serial communications controller SCP Serial control port SDLC Synchronous data link control SDMA Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SNA Systems network architecture.
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Chapter 6 External Signals This chapter describes the external signals. A more detailed description of 60x bus signals is provided in Chapter 8, “The 60x Bus.” 6.1 Functional Pinout Figure 6-1 shows PowerQUICC II signals grouped by function. Note that many signals are multiplexed and this figure does not indicate how these signals are multiplexed. NOTE A bar over a signal name indicates that the signal is active low—for example, BB (bus busy).
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External Signals VCCSYN/GNDSYN/VCCSYN1//VDDH/ ⎯⎯⎯> 100 VDD/VSS <⎯⎯> 1 PCI_PAR1 /L_A14 SMI/PCI_FRAME1/L_A15 <⎯⎯> 1 PCI_TRDY1/L_A16 <⎯⎯> 1 CKSTOP_OUT/PCI_IRDY1/L_A17 <⎯⎯> 1 PCI_STOP1/L_A18 <⎯⎯> 1 PCI_DEVSEL1/L_A19 <⎯⎯> 1 PCI_IDSEL1/L_A20 <⎯⎯> 1 PCI_PERR1/L_A21 <⎯⎯> 1 PCI_SERR/1 L_A22 <⎯⎯> 1 PCI_REQ01/L_A23 <⎯⎯> 1 1 CPCI_HS_ES /PCI_REQ11/L_A24 <⎯⎯> 1 PCI_GNT01/L_A25 <⎯⎯> 1 1 CPCI_HS_LED /PCI_GNT11/L_A26 <⎯⎯⎯ 1 CPCI_HS_ENUM1/GNT21/L_A27 <⎯⎯> 1 CORE_SRESET/PCI_RST1/L_A28 <⎯⎯> 1 PCI_INTA1/L_A29 <⎯⎯> 1 PCI_REQ21/L
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External Signals Table 6-1. External Signals Signal Description BR 60x bus request—This is an output when an external arbiter is used and an input when an internal arbiter is used. As an output the PowerQUICC II asserts this pin to request ownership of the 60x bus. As an input an external master should assert this pin to request 60x bus ownership from the internal arbiter. BG 60x bus grant—This is an output when an internal arbiter is used and an input when an external arbiter is used.
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External Signals Table 6-1. External Signals (continued) Signal Description DBB 60x data bus busy—(Input/output) As an output the PowerQUICC II asserts this pin for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the PowerQUICC II negates DBB for a fraction of a bus cycle and than stops driving this pin. As an input, the PowerQUICC II does not assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus master.
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External Signals Table 6-1. External Signals (continued) Signal Description IRQ3 Interrupt request 3—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. DP[3] 60x data parity 3—(Input/output) The 60x agent that drives the data bus drives also the data parity signals. The value driven on data parity 3 pin should give odd parity (odd number of 1’s) on the group of signals that includes data parity 3 and D[24–31].
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External Signals Table 6-1. External Signals (continued) Signal Description IRQ7 Interrupt request 7—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. DP[7] 60x data parity 7—(Input/output) The 60x master or slave that drives the data bus drives also the data parity signals.
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External Signals Table 6-1. External Signals (continued) Signal Description WT Write through—Output used for L2 cache control. For each core-initiated PowerQUICC II 60x transaction, the state of this pin indicates if the transaction should be cached using write-through or copy-back mode. Assertion of WT indicates that the transaction should be cached using the write-through mode. BADDR30 Burst address 30—There are five burst address output pins. These pins are outputs of the 60x memory controller.
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External Signals Table 6-1. External Signals (continued) Signal Description CS[11] Chip select—Output that enable specific memory devices or peripherals connected to PowerQUICC II buses. AP[0] Address parity 0—(Input/output) The 60x master that drives the address bus, drives also the address parity signals. The value driven on address parity 0 pin should give odd parity (odd number of ‘1’s) on the group of signals that includes address parity 0 and A[0–7].
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External Signals Table 6-1. External Signals (continued) Signal Description PSDCAS 60x bus SDRAM CAS—Output from the 60x bus SDRAM controller. Should be connected to SDRAMs’ CAS input. PGPL3 60x bus UPM general purpose line 3—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM. PGTA 60x GPCM TA—This input pin is used for transaction termination during GPCM operation. Requires external pull up resistor for proper operation.
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External Signals Table 6-1. External Signals (continued) Signal LSDWE LGPL1 Description Local bus SDRAM write enable—Output from the local bus SDRAM controller. Should be connected to the WE inputs of the SDRAMs. Local bus UPM general purpose line 1—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM. PCI_MODCK_H11 PCI MODCK_H1—In PCI mode, defines the operating mode of internal clock circuits.
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External Signals Table 6-1. External Signals (continued) Signal Description L_A15 Local bus address 15—Local bus address bit 15 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant. SMI System management interrupt—System management interrupt input to the core. PCI_FRAME1 PCI frame—PCI cycle frame input/output pin. Used by the current PCI master to indicate the beginning and duration of an access.
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External Signals Table 6-1. External Signals (continued) Signal Description L_A22 Local bus address 22—Local bus address bit 22 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant. PCI_SERR1 PCI system error—PCI system error input/output pin. Assertion of this pin indicates that a PCI system error was detected during a PCI transfer.
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External Signals Table 6-1. External Signals (continued) Signal Description L_A27 Local bus address 27—Local bus address bit 27 output pin. In the local address bus bit 14 is most significant and bit 31 is least significant. PCI_GNT21 PCI arbiter grant 2—PCI grant 2 output pin. When the PowerQUICC II’s internal PCI arbiter is used, assertion of PCI_GNT2 indicates that the external PCI device that requested the PCI bus with PCI_REQ2 pin is granted the bus.
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External Signals Table 6-1. External Signals (continued) Signal Description LCL_DP[0–3] Local bus data parity—Local bus data parity input/output pins. In local bus write operations the PowerQUICC II drives these pins. In local bus read operations the accessed device drives these pins. LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0–7]. LCL_DP[1] is driven with a value that gives odd parity with LCL_D[8–15]. LCL_DP[2] is driven with a value that gives odd parity with LCL_D[16–23].
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External Signals Table 6-1. External Signals (continued) Signal Description RSTCONF RSTCONF —Input used during reset configuration sequence of the chip. Find detailed explanation of its function in Section 5.1.2, “Power-On Reset Flow,” and Section 5.4, “Reset Configuration.” MODCK1 MODCK1—Clock mode input. Defines the operating mode of internal clock circuits. AP[1] Address parity 1—(Input/output) The 60x master that drives the address bus, drives also the address parity signals.
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External Signals Table 6-1. External Signals (continued) Signal Description PA[0–31] General-purpose I/O port A bits 0–31—CPM port multiplexing is described in Chapter 40, “Parallel I/O Ports.” PB[4–31] General-purpose I/O port B bits 4–31—CPM port multiplexing is described in Chapter 40, “Parallel I/O Ports.” PC[0–31] General-purpose I/O port C bits 0–31—CPM port multiplexing is described in Chapter 40, “Parallel I/O Ports.
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Chapter 7 60x Signals This chapter describes the PowerQUICC II processor’s external signals. It contains a concise description of individual signals, showing behavior when a signal is asserted and negated, when the signal is an input and an output, and the differences in how signals work in external-master or internal-only configurations. NOTE A bar over a signal name indicates that the signal is active low– for example, ARTRY (address retry) and TS (transfer start).
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60x Signals 7.1 Signal Configuration Figure shows the grouping of the PowerQUICC II’s 60x bus signal configuration. NOTE The PowerQUICC II hardware specifications provides a pinout showing pin numbers. These are shown in Figure 7-1.
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60x Signals 7.2.1 Address Bus Arbitration Signals The address arbitration signals are a collection of input and output signals devices use to request address bus mastership, recognize when the request is granted, and indicate to other devices when mastership is granted. For a detailed description of how these signals interact, see Section 8.4.1, “Address Arbitration.” Bus arbitration signals have no meaning in internal-only mode. 7.2.1.
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60x Signals a snoop copyback; may also be negated if the external master cancels a bus request internally before receiving a qualified BG. High Impedance—Occurs during a hard reset or checkstop condition. 7.2.1.2 Bus Grant (BG) The address bus grant (BG) signal is both an input and an output signal. 7.2.1.2.1 Bus Grant (BG)—Input The following are the state meaning and timing comments for the BG signal input.
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60x Signals 7.2.1.3 Address Bus Busy (ABB) The address bus busy (ABB) signal is both an input and an output signal. 7.2.1.3.1 Address Bus Busy (ABB)—Output Following are the state meaning and timing comments for the ABB output signal. State Meaning Asserted—Indicates that the PowerQUICC II is the current address bus master. The PowerQUICC II may not assume address bus ownership in case a bus request is internally cancelled by the cycle a qualified BG would have been recognized.
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60x Signals Timing Comments 7.2.2.2 bus request if the transfer attributes TT[0–4] indicate that a data tenure is required for the transaction. Negated—Has no special meaning during a normal transaction. Assertion/Negation—Driven and asserted on the cycle after a qualified BG is accepted by PowerQUICC II; remains asserted for one clock only. Negated for the remainder of the address tenure. Assertion is coincident with the first clock that ABB is asserted.
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60x Signals State Meaning Timing Comments 7.2.4 Asserted—Indicates that another device has begun a bus transaction and that the address bus and transfer attribute signals are valid for snooping and in slave mode. Negated—Has no special meaning. Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled by the processor only on this cycle. Address Transfer Attribute Signals In internal only mode the address transfer attribute signals have no meaning.
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60x Signals High Impedance—Same as A[0–31]. 7.2.4.3 Transfer Burst (TBST) The transfer burst (TBST) signal is an input/output signal on the PowerQUICC II. Following are the state meaning and timing comments for the TBST output/input signal. State Meaning Timing Comments 7.2.4.4 Asserted—Indicates that a burst transfer is in progress (see Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer”).
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60x Signals State Meaning Timing Comments 7.2.4.6 Asserted—Indicates that the transaction in progress should not be cached. CI reflects the I bit (WIM bits) from the MMU except during certain transactions. Negated—Indicates that the transaction should be cached. Assertion/Negation—Same as A[0–31]. High Impedance—Same as A[0–31]. Write-Through (WT)—Output The write-through (WT) signal is an output signal on the PowerQUICC II. Following are the state meaning and timing comments for WT.
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60x Signals State Meaning Timing Comments Asserted—Indicates that a 60x bus slave is terminating the address tenure. On the cycle following the assertion of AACK, the bus master releases the address tenure related signals to the high-impedance state and samples ARTRY. Negated—Indicates that the address tenure must remain active and the address tenure related signals driven. Assertion—Occurs during the 60x bus slave access, at least two clocks after TS. Negation—Occurs one clock after assertion. 7.2.5.
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60x Signals Timing Comments 7.2.6 Assertion—May occur as early as the second cycle following the assertion of TS and must occur by the bus clock cycle immediately following the assertion of AACK if an address retry is required. Negation—Must occur during the second cycle after the assertion of AACK. Data Bus Arbitration Signals The data bus arbitration signals have no meaning in internal-only mode.
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60x Signals Timing Comments 7.2.6.2 Negated—Indicates that an external device is not granted mastership of the data bus. Assertion—Occurs on the first clock in which the data bus is not busy and the processor has the highest priority outstanding data transaction. Negation—Occurs one clock after assertion. Data Bus Busy (DBB) The data bus busy (DBB) signal is both an input and output signal on the PowerQUICC II. 7.2.6.2.
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60x Signals State Meaning Timing Comments 7.2.7.1.1 The data bus holds 8 byte lanes assigned as shown in Table 7-2. The number of times the data bus is driven depends on the transfer size, port size, and whether the transfer is a single-beat or burst operation. Data Bus (D[0–63])—Output Following are the state meaning and timing comments for the D[0–63] output signals. State Meaning Asserted/Negated—Represents the state of data during a data write.
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60x Signals State Meaning Asserted/Negated—Represents odd parity for each of 8 bytes of data write transactions. Odd parity means that an odd number of bits, including the parity bit, are driven high. The signal assignments are listed in Table 7-2. Table 7-2. DP[0–7] Signal Assignments Timing Comments 7.2.7.2.
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60x Signals Timing Comments asserted for each data beat in a burst transaction. For more information, see Section 8.5.3, “Data Bus Transfers and Normal Termination.” Negated—(During assertion of DBB) indicates that, until TA is asserted, the PowerQUICC II must continue to drive the data for the current write or must wait to sample the data for reads.
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60x Signals Negation—Occurs after the clock cycle of the final (or only) data beat of the transfer. For a burst transfer, TA may be negated between beats to insert one or more wait states before the completion of the next beat. 7.2.8.2 Transfer Error Acknowledge (TEA) The transfer error acknowledge (TEA) signal is both input and output on the PowerQUICC II. 7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input Following are the state meaning and timing comments for the TEA input signal.
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60x Signals Timing Comments 7.2.8.3.2 transaction,. For more information, see Section 8.5.5, “Port Size Data Bus Transfers and PSDVAL Termination.” Negated—(During DBB) indicates that, until PSDVAL is asserted, the PowerQUICC II must continue to drive the data for the current write or must wait to sample the data for reads.
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60x Signals MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 8 The 60x Bus The 60x bus, which is used by processors that implement the PowerPC architecture, provides flexible support for the on-chip MPC603 processor as well as other internal and external bus devices. The 60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-, 32-, and 64-bit data ports.
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The 60x Bus Table 8-1. Terminology (continued) Term Definition Parking Granting potential bus mastership without requiring a bus request from that device. This eliminates the arbitration delay associated with the bus request. Pipelining Initiating a bus transaction before the current one finishes. This involves running an address tenure for a new bus transaction before the data tenure for a current bus transaction completes. Slave The device addressed by the master.
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The 60x Bus PowerQUICC II APE TS Latch & A[0–31] DRAM MUX I/O TT[0–4] TBST CI WT Address + Attributes TSIZ[0–3] MEM GBL DBG D[0–63] DP[0–7] TA Memory Controller Signals ARTRY Data + Attributes AACK TEA Memory Control Signals Figure 8-1. Single-PowerQUICC II Bus Mode NOTE In single-PowerQUICC II bus mode, the PowerQUICC II uses the address bus as a memory address bus. Slaves cannot use the 60x bus signals because the addresses have memory timing, not address tenure timing. 8.2.
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The 60x Bus operations and maintains coherency between the primary caches and main memory. Figure 8-2 shows how an external processor is attached to the PowerQUICC II. PowerQUICC II APE TS BR BG TS A[0–31] AP[0–3] Latch I/O TT[0–4] TSIZ[0–3] GBL AACK ARTRY Data + Attributes WT Address + Attributes CI Memory Controller Signals TBST Latch & MEM DRAM MUX DBG External Device Memory Control Signals BR D[0–63] BG DP[0–7] DBG TA TEA Figure 8-2. 60x-Compatible Bus Mode 8.
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The 60x Bus require data transfer termination signals for each beat of data. Note that the PowerQUICC II supports port sizes of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not defined by the 60x bus specification. For more information, see Section 8.5.5, “Port Size Data Bus Transfers and PSDVAL Termination.
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The 60x Bus system reset by sampling configuration pins. See Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR),” for more information. The PowerQUICC II controls bus access through the bus request (BR) and bus grant (BG) signals. It determines the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and it qualifies them with ABB and DBB.
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The 60x Bus External arbitration (as provided by the PowerQUICC II) is required in systems in which multiple devices share the system bus. The PowerQUICC II uses the address acknowledge (AACK) signal to control pipelining. The PowerQUICC II supports both one- and zero-level bus pipelining. One-level pipelining is achieved by asserting AACK to the current address bus master and granting mastership of the address bus to the next requesting master before the current data bus tenure has completed.
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The 60x Bus with BG INT-asserted (note that BG INT is an internal signal not seen by the user at the pins), which lets it start an address bus tenure by asserting TS. During the same clock cycle, the external master’s bus request is asserted to request access to the 60x bus, thereby causing the negation of BG INT internally and the assertion of BG at the pin. Following PowerQUICC II’s address tenure, the external master takes the bus and initiates its address transaction.
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The 60x Bus CLKOUT ADDR + ATTR TS AACK DBG TA Address Tenure Address 1 Data Tenure Address 2 Data 1 Data 2 Figure 8-5. Address Pipelining 8.4.3 Address Transfer Attribute Signals During the address transfer, the address is placed on the address signals, A[0–31]. The bus master provides other signals that characterize the address transfer—transfer type (TT[0–4]), transfer code (TC[0–2]), transfer size (TSIZ[0–3]), and transfer burst (TBST) signals.
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The 60x Bus Table 8-2. Transfer Type Encoding 60x Bus Specification2 TT[0–4] PowerQUICC II as Bus Master 1 Command Transaction Bus Trans. Transaction Source PowerQUICC I I as Snooper PowerQUICC II as Slave Action on Hit Action on Slave Hit 00000 Clean block Address only Address only (if enabled) dcbst (if enabled) Not applicable AACK asserted; PowerQUICC II takes no further action.
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The 60x Bus Table 8-2. Transfer Type Encoding (continued) 60x Bus Specification2 PowerQUICC II as Bus Master TT[0–4]1 Command Transaction 1 2 — Bus Trans.
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The 60x Bus • • • 8.4.3.2 For reads, the processor cleans or flushes during a snoop based on the TBST input. The processor cleans for single-beat reads (TBST negated) to emulate read-with-no-intent-to-cache operations. Castouts and snoop copybacks are generally marked as non-global and are not snooped (except for reservation monitoring).
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The 60x Bus The PowerQUICC II supports critical-word-first burst transactions (double-word-aligned) from the processor. The PowerQUICC II transfers the critical double word of data first, followed by the double words from increasing addresses, wrapping back to the beginning of the eight-word block as required. Table 8-4.
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The 60x Bus Table 8-5. Burst Ordering Double-Word Starting Address: Data Transfer A[27–28] = 001 A[27–28] = 01 A[27–28] = 10 A[27–28] = 11 1st data beat DW02 DW1 DW2 DW3 2nd data beat DW1 DW2 DW3 DW0 3rd data beat DW2 DW3 DW0 DW1 4th data beat DW3 DW0 DW1 DW2 1 A[27–28] specifies the first double word of the 32-byte block being transferred; any subsequent double words must wrap-around the block. A[29–31] are always 0b000 for burst transfers by the PowerQUICC II.
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The 60x Bus Table 8-6. Aligned Data Transfers (continued) Data Bus Byte Lanes Program Transfer Size TSIZ[0–3] Word Double-Word A[29–31] D0... ...D31 D32... ...D63 B0 B1 B2 B3 B4 B5 B6 B7 0 1 0 0 000 OP0 OP1 OP2 OP3 — — — — 0 1 0 0 100 — — — — OP4 OP5 OP6 OP7 0 0 0 0 000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 1 OPn: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand and OP7 is the least-significant byte.
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The 60x Bus Table 8-7. Unaligned Data Transfer Example (4-Byte Example) (continued) Data Bus Byte Lanes Program Size of Word (4 bytes) TSIZ[1–3] A[29–31] D0... ...D31 D32... ...D63 B0 B1 B2 B3 B4 B5 B6 B7 Misaligned—1st access 0 1 0 1 1 0 — — — — — — A A 2nd access 0 1 0 0 0 0 A A — — — — — — Misaligned—1st access 0 0 1 1 1 1 — — — — — — — A 2nd access 0 1 1 0 0 0 A A A — — — — — 1 2 A: Byte lane used —: Byte lane not used 8.4.3.
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The 60x Bus Interface Output Register 0 31 OP0 D[0–7] OP0 OP1 OP2 D[8–15] OP1 OP3 D[15–23] OP2 D[24–31] OP3 63 OP4 OP5 D[32–39] OP4 OP6 D[40–47] OP5 D[48–55] OP6 OP7 D[56–63] OP7 64-Bit Port Size OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size OP7 Figure 8-6. Interface to Different Port Size Devices MPC8260 PowerQUICC II Family Reference Manual, Rev.
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The 60x Bus Table 8-8.
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The 60x Bus calculation state machine. Note that the address and size states are for internal use and are not transferred on the address or TSIZ pins. Extended transactions (16- and 24-byte) are not described here but can be determined by extending this table for 9-, 10-, 16-, 23-, and 24-byte transactions. Table 8-9.
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The 60x Bus 16-, or 24-byte extended transfers. These transactions are compatible with the 60x bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable this type of transaction. This places the PowerQUICC II in strict 60x bus mode. The following tables are extensions to Table 8-7, Table 8-8, and Table 8-9. Table 8-10 lists the patterns of the extended data transfer for write cycles when PowerQUICC II initiates an access.
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The 60x Bus Table 8-12.
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The 60x Bus Table 8-12. Address and Size State for Extended Transfers (continued) Size State [0–3] 7-Byte Address State[0–4] x x 0 0 0 x x 0 0 1 x x 0 0 0 x x 0 0 1 x x 0 0 0 x x 0 0 1 x x x x x Port Size Next Size State [0–3] Byte 6-Byte Half Word Double Next Address State[0–4] x x 0 0 1 x x 0 1 0 5-Byte x x 0 1 0 6-Byte x x 0 1 0 3-Byte x x 1 0 0 4-Byte x x 1 0 0 Stop Extended transfer mode is enabled by setting the BCR[ETM].
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The 60x Bus CLKOUT BR INT BG INT BR External BG ABB ADDR + ATTR PowerQUICC II External PowerQUICC II TS AACK ARTRY Figure 8-7. Retry Cycle As a bus master, the PowerQUICC II recognizes either an early or qualified ARTRY and prevents the data tenure associated with the retried address tenure. If the data tenure has begun, the PowerQUICC II terminates the data tenure immediately even if the burst data has been received.
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The 60x Bus TA/ARTRY relationship is not met, the master may enter an undefined state. Users may use PPC_ACR[DBGD] to ensure correct operation of the system. During the clock of a qualified ARTRY, each device master determines whether it should negate BR and ignore BG on the following cycle. The following cycle is referred to as the window-of-opportunity for the snooping master. During this window, only the snooping master that asserted ARTRY and requires a snoop copyback operation is allowed to assert BR.
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The 60x Bus • 8.5 one-level pipelining). When the internal arbiter counts a pipeline depth of two (two assertions of AACK before the assertion of the current data tenure) it negates all address bus grant (BG) signals. No-pipeline mode—The PowerQUICC II does not assert AACK until the corresponding data tenure ends. Data Tenure Operations This section describes the operation of the PowerQUICC II during the data bus arbitration, transfer, and termination phases of the data tenure.
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The 60x Bus • 8.5.2 External masters connected to the 60x bus must assert DBB only for the duration of its data tenure. External masters should not use DBB to prevent other masters from using the data bus after their data tenure has ended. Data Streaming Mode The PowerQUICC II supports a special data streaming mode that can improve bus performance in some conditions. Generally, the bus protocol requires one idle cycle between any two data tenures.
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The 60x Bus Figure 8-8 shows both a single-beat and burst data transfer. The PowerQUICC II asserts TA to mark the cycle in which data is accepted. In a normal burst transfer, the fourth assertion of TA signals the end of a transfer. CLKOUT ADDR + ATTR TS AACK DBG TA PSDVAL D[0–63] D0 D1 D2 D3 Figure 8-8. Single-Beat and Burst Data Transfers 8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration The PowerQUICC II allows an address tenure to overlap its associated data tenure.
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The 60x Bus CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0–31] D0 D1 D2 D3 Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port Size Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two port-sized beats such that the four double words are transferred in eight beats. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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The 60x Bus CLKOUT ADDR + ATTR TS AACK DBG PSDVAL TA D[0–31] D0 D1 D2 D3 D4 D5 D6 D7 Figure 8-10. Burst Transfer to 32-Bit Port Size 8.5.6 Data Bus Termination by Assertion of TEA If a device initiates a transaction that is not supported by the PowerQUICC II, the PowerQUICC II signals an error by asserting TEA.
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The 60x Bus CLKOUT ADDR + ATTR For Single For Burst TS AACK DBG TA TEA Data Figure 8-11. Data Tenure Terminated by Assertion of TEA The PowerQUICC II interprets the following bus transactions as bus errors: • Direct-store transactions, as indicated by the assertion of XATS. • Bus errors asserted by slaves (internal or external). 8.
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The 60x Bus snooping condition). No snoop update to the PowerQUICC II processor cache occurs if the transaction is not marked global. This includes invalidation cycles. When the PowerQUICC II processor detects a qualified snoop condition, the address associated with the TS is compared against the data cache tags. Snooping completes if no hit is detected. However, if the address hits in the cache, the PowerQUICC II processor reacts according to the MEI protocol shown in Figure 8-12.
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The 60x Bus 8.7.1 Support for the lwarx/stwcx. Instruction Pair The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions provide a way to update memory atomically by setting a reservation on the load and checking that the reservation is still valid before the store is performed. In the PowerQUICC II, reservations are made on behalf of aligned, 32-byte sections of the memory address space.
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Chapter 9 PCI Bridge NOTE The functionality described in this chapter is available only on the MPC8250, the MPC8265, and the MPC8266. The PCI bridge enables the PowerQUICC II to gluelessly bridge PCI devices to a processor that implements the PowerPC architecture, to serve as a PCI interface for CompactPCI™ (CPCI) systems or as a basis for passive PCI NIC implementations. In addition, multiple PowerQUICC II processors can interface with each other over the PCI bus.
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PCI Bridge PowerQUICC II G2 Core 60x Bus PCI Bridge 0 Mux SDMA Communications Processor DPRAM Module PCI Bus 1 60x-to-Local Bridge PCI_MODE Figure 9-1. PCI Bridge in the PowerQUICC II PowerQUICC II 60x Bus/Local SDMA PowerQUICC II Internal PCI Bridge I/O Sequencer 60x Interface Buffer Pool Embedded Utilities DMA PCI Interface I2O Regs PCI Bus Figure 9-2. PCI Bridge Structure MPC8260 PowerQUICC II Family Reference Manual, Rev.
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PCI Bridge 9.1 Signals To avoid the need for additional pins, the PCI bridge is designed to make use of the local bus signals. Therefore, many of these pins perform different functions, depending on how the user configures them. PCI bridge signals are described in Chapter 6, “External Signals.” 9.2 Clocking PCI bridge clocking is described in Chapter 10, “Clocks and Power Control.” 9.3 PCI Bridge Initialization The PCI bridge uses fields from the hard reset configuration word (refer to Section 5.4.
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PCI Bridge NOTE Although the user can direct the SDMA to the 60x bus, transactions can be redirected to the PCI bridge if they fall in one of the PCI windows of the 60x bus memory map (PCIBR0 or PCIBR1; refer to Section 4.3.4.1, “PCI Base Register (PCIBRx)”). Data flow of this kind is not recommended because it is not optimal. However, if it is implemented, the user must set strict 60x bus mode (BCR[ETM] = 0). 9.
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PCI Bridge 9.8 CompactPCI Hot Swap Specification Support CompactPCI is an open specification supported by the PCI Industrial Computer Manufacturers Group (PICMG) and is intended for embedded applications using PCI. CompactPCI Hot Swap is an extension of the CompactPCI specification and allows the insertion and extraction (or “hot swapping”) of boards without adversely affecting system operation.
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PCI Bridge • Address translation units for address mapping between host and agent. Efforts were made to keep the terminology in this chapter consistent with the PCI Specification, revision 2.2, and other PCI documentation; therefore, the terms found in Table 9-1 may differ from most documentation for processors that implement the PowerPC architecture (for example, architecture specification or reference manuals). Table 9-1.
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PCI Bridge Table 9-2. PCI Command Definitions Supported as: PCI_C/BE[3-0] Command Type Definition Initiator Target 0b0000 Interrupt acknowledge YES NO A read implicitly addressed to the system interrupt controller. The size of the vector to be returned is indicated on the byte enables after the address phase. 0b0001 Special cycle YES NO Provides a simple message broadcast mechanism. See Section 9.9.1.4.6, “Special Cycle Command.
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PCI Bridge 9.9.1.2.1 Basic Transfer Control PCI data transfers are controlled with three fundamental signals: • FRAME is driven by an initiator to indicate the beginning and end of a transaction. • IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles. • TRDY (target ready) is driven by a target, allowing it to force wait cycles. The bus is idle when both FRAME and IRDY are negated. The first clock cycle in which FRAME is asserted indicates the beginning of the address phase.
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PCI Bridge line, and disconnects after reading one cache line. If AD[1-0] is 0bx1 (a reserved encoding) and the PCI_C/BE[3-0] signals indicate a memory transaction, it executes a target disconnect after the first data phase is completed. Note that AD[1-0] are included in parity calculations. 9.9.1.2.3 Byte Enable Signals The byte enable signals (BE[3-0]) indicate which byte lanes carry valid data. The byte enable signals may enable different bytes for each of the data phases.
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PCI Bridge A read transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals indicate a read command. Figure 9-3 shows an example of a single beat read transaction. PCI_CLK AD[31:0] ADDR PCI_C/BE[3:0] CMD DATA BYTE ENABLES FRAME IRDY DEVSEL TRDY Figure 9-3. Single Beat Read Example Figure 9-4 shows an example of a burst read transaction. PCI_CLK AD[31:0] ADDR PCI_C/BE[3:0] CMD DATA1 BYTE ENABLES 1 DATA2 BYTE ENABLES 2 FRAME IRDY DEVSEL TRDY Figure 9-4.
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PCI Bridge PCI_CLK AD[31:0] ADDR DATA PCI_C/BE[3:0] CMD BYTE ENABLES FRAME IRDY DEVSEL TRDY Figure 9-5. Single Beat Write Example Figure 9-6 shows an example of a burst write transaction. PCI_CLK AD[31:0] ADDR DATA1 DATA2 DATA3 DATA4 PCI_C/BE[3:0] CMD BEs 1 BEs 2 BEs 3 BEs 4 FRAME IRDY DEVSEL TRDY Figure 9-6.
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PCI Bridge When the PCI bridge as a target needs to suspend a transaction, it asserts STOP. Once asserted, STOP remains asserted until FRAME is negated. Depending on the circumstances, data may or may not be transferred during the request for termination. If TRDY and IRDY are asserted during the assertion of STOP, data is transferred. This type of target-initiated termination is called a ‘disconnect B,’ shown in Figure 9-7.
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PCI Bridge • • • • AD[1-0] is 0bx1 (a reserved burst ordering encoding) during the address phase and one data phase has completed. The PCI command is a configuration command and one data phase has completed when a streaming transaction crosses a 4K page boundary. A streaming transaction runs out of I/O sequencer buffer entries. A cache line wrap transaction has completed a cache line transfer. Another target-initiated termination is the retry termination.
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PCI Bridge target qualifies the address/data lines with FRAME before asserting DEVSEL. DEVSEL is asserted at or before the clock edge at which the PCI bridge enables its TRDY, STOP, or data (for a read). DEVSEL is not negated until FRAME is negated, with IRDY asserted and either STOP or TRDY asserted. The exception to this is a target-abort; see Section 9.9.1.3.2, “Transaction Termination.
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PCI Bridge For core- or DMA-initiated transfers, the PCI bridge streams over cache line boundaries if the prefetch bit in the corresponding outbound ATU is enabled and the address space identified by the outbound ATU is marked as PCI memory space. 9.9.1.4.4 Host Mode Configuration Access The PCI bridge provides two types of configuration accesses to support hierarchical bridges.
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PCI Bridge the AD lines, reaches a stable value. This means that a valid address and command are driven on the AD and PCI_C/BE lines one cycle before the assertion of FRAME. For Type 1 translations, the PCI bridge copies the contents of the CONFIG_ADDR register directly onto the PCI address/data lines during the address phase of a configuration cycle, with the exception that AD[1-0] contains 0b01 (not 0b00 as in Type 0 translations).
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PCI Bridge When the CONFIG_ADDRESS register gets written with a value such that the bus number matches the bridge’s bus, the device number is all ones, the function number is all ones and the register number is zero, the next time the CONFIG_DATA register is accessed the PCI bridge does either a special cycle or an interrupt acknowledge command.
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PCI Bridge 9.9.1.5.2 Error Reporting Except for setting the detected-parity-error bit, all parity error reporting and response is controlled by the parity-error-response bit (see Section 9.11.2.3, “PCI Bus Command Register”). If the parity-error-response bit is cleared, the PCI bridge completes all transactions regardless of parity errors (address or data).
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PCI Bridge As a target that asserts SERR on an address parity, the PCI bridge completes the transaction on the PCI bus, aborting internally if the transaction is a write to system memory. If PERR is asserted during a PCI bridge write to PCI, the PCI bridge attempts to continue the transfer, allowing the target to abort/disconnect if desired.
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PCI Bridge is the master that is currently using the bus, and the highest priority device is the next one to follow the current master. This is considered to be a fair algorithm because a given device cannot prevent other devices from having access to the bus—a given device automatically becomes the lowest priority device as soon as it begins to use the bus. If a master is not requesting the bus, the transaction slot is given to the next requesting device within the priority group.
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PCI Bridge completes one more data phase and relinquishes the bus. The master latency timer can be disabled if needed (see Section 9.11.2.22, “PCI Bus Function Register”). 9.10 Address Map A transaction sent to the PCI bridge from any 60x bus master side falls into one of the following three cases: • If the transaction address is within the internal register space of the PowerQUICC II, the transaction is handled by the PCI bridge internal register logic.
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PCI Bridge • If the transaction address is within one of the two inbound PCI translation windows, the transaction is sent to the core side of the PCI bridge with address translation. This window is provided for the PCI master to access the PowerQUICC II's internal (dual port) registers/area. Its size is assumed to be fixed at 128K bytes. It translates to MPC8256A's IMMR value for the upper bits of the address. This way, the PCI master can access any of the PCI bridge registers (DMA/MU, etc.
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PCI Bridge NOTE When a transaction is performed by a PCI master, the bridge checks the address against inbound ATUs and if it does not hit, it then checks against PIMMR; if it is a hit, the bridge translates it to a 60x cycle. Because PIMMR does not have an associated translation register and window size definition, the translation is performed as follows: a 128-Kbyte window is provided for the PCI master to access the PowerQUICC II’s internal (dual port) registers.
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PCI Bridge 60x bus master view PCI master memory view 0 0 PCI master I/O view 0 Address translation Address translation Address translation PCI bridge Address translation PCI memory Address translation Internal registers Internal registers 4G 4G 4G Figure 9-14. Address Map Example 9.10.1 Address Map Programming The address map has a number of programmable ranges to determine the PCI bridge’s response to all transactions.
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PCI Bridge are routed to the PCI bus with address translation disabled. The reset configuration for inbound transactions are that all inbound requests from the PCI bus are disabled. 9.10.2.1 PCI Inbound Translation For inbound transactions (transactions generated by an external master on the PCI bus where the PCI bridge responds as a slave device), the PCI bridge only responds to PCI addresses within the windows mapped by the PCI inbound base address registers (PIBARs).
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PCI Bridge 9.10.2.2 PCI Outbound Translation Outbound address translation is provided to allow the outbound transactions to access any address over the PCI memory or I/O space. Translation window’s base addresses are defined in the PCI outbound base address registers (refer to Section 9.11.1.4, “PCI Outbound Base Address Registers (POBARx)”). Transactions to these address ranges are issued on the PCI bus with a translated address.
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PCI Bridge 9.11 Configuration Registers There are two types of configuration registers in the PCI bridge: PCI-specified and memory-mapped. The PCI-specified type, referred to as PCI configuration registers, are accessed through PCI configuration cycles (refer to Section 9.11.2, “PCI Bridge Configuration Registers”). The memory-mapped configuration registers are placed in the internal memory map of the PowerQUICC II and are accessed like other internal registers (refer to Section 9.11.
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PCI Bridge Table 9-3. Internal Memory Map (continued) Address (offset) Register Access Reset Section/Page 0x10458 Outbound message register 0 (OMR0) R/W undefined 9.12.1.2/9-66 0x1045C Outbound message register 1 (OMR1) R/W undefined 9.12.1.2/9-66 0x10460 Outbound doorbell register (ODR) R/W 0x0000_0000 9.12.2.1/9-67 0x10468 Inbound doorbell register (IDR) R/W 0x0000_0000 9.12.2.2/9-68 0x10480 Inbound message interrupt status register (IMISR) R/W 0x0000_0000 9.12.3.4.
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PCI Bridge Table 9-3. Internal Memory Map (continued) Address (offset) Register Access Reset Section/Page 0x10608 DMA 2 current descriptor address register (DMACDAR2) R/W 0x0000_0000 9.13.1.6.3/9-91 0x10610 DMA 2 source address register (DMASAR2) R/W 0x0000_0000 9.13.1.6.4/9-92 0x10618 DMA 2 destination address register (DAR2) R/W 0x0000_0000 9.13.1.6.5/9-92 0x10620 DMA 2 byte count register (DMABCR2) R/W 0x0000_0000 9.13.1.6.
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PCI Bridge Table 9-3. Internal Memory Map (continued) Address (offset) Register Access Reset Section/Page 0x108E0 PCI inbound comparison mask register 1 (PICMR1) R/W 0x0000_0000 9.11.1.17/9-43 0x108E8 PCI inbound translation address register 0 (PITAR0) R/W 0x0000_0000 9.11.1.15/9-42 0x108F0 PCI inbound base address register 0 (PIBAR0) R/W 0x0000_0000 9.11.1.16/9-42 0x108F8 PCI inbound comparison mask register 0 (PICMR0) R/W 0x0000_0000 9.11.1.
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PCI Bridge Table 9-4. POTARx Field Descriptions Bits Name 31–20 — 19–0 Translation Address 9.11.1.4 Description Reserved, should be cleared. PCI address which indicates the starting point of the outbound translated address. The translation address must be aligned based on the window’s size.
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PCI Bridge Field 31 30 29 28 EN I/O PRE 20 19 16 — Reset CM 0000_0000_0000_0000 R/W R/W Addr 0x10812 (POCMR0); 0x2082A (POCMR1); 0x10842 (POCMR2) 15 0 Field CM Reset 0000_0000_0000_0000 R/W R/W Addr 0x10810 (POCMR0); 0x20828 (POCMR1); 0x10840 (POCMR2) Figure 9-19. PCI Outbound Comparison Mask Registers (POCMRx) Table 9-6. describes POCMRx. Table 9-6.
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PCI Bridge 31 Field 30 24 EN 23 16 — Reset PTV 0000_0000_0000_0000 R/W R/W Addr 0x1087A 15 0 Field PTV Reset 0000_0000_0000_0000 R/W R/W Addr 0x10878 Figure 9-20. Discard Timer Control register (PTCR) Table 9-7. describes PTCR fields. Table 9-7. PTCR Field Descriptions Bits Name 31 Enable 30–24 — 23–0 Preload timer value 9.11.1.7 Description Discard timer enable. 0 Disable the discard timer 1 Enable the discard timer Reserved Preload value for 24-bit discard timer.
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PCI Bridge 31 20 Field — Reset 18 17 DMABC 16 — 0000_0000_0000_0000 R/W R/W Addr 0x1087E Field 19 15 14 13 — INTPCI MCP2PCI Reset 12 1 — 0 LE_MODE 0000_0000_0000_0000 R/W R/W Addr 0x1087C Figure 9-21. General Purpose Control Register (GPCR) Table 9-8. describes GPCR fields. Table 9-8. GPCR Field Descriptions Bits Name Description 31–20 — 19–18 DMABC 17–15 — 14 INT2PCI Interrupt reroute to PCI. 0 Interrupts are not rerouted to the PCI.
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PCI Bridge Table 9-8. GPCR Field Descriptions (continued) Bits Name 12–1 — 0 LE_MODE 9.11.1.8 Description Reserved, should be cleared. Little endian mode. Controls the translation of 60x-PCI and PCI-60x. Refer to Section 9.11.2.27.1, “Additional Information on Endianess” for more details. 0 Big endian mode. 1 Little endian mode.
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PCI Bridge 31 16 Field — Reset 0000_0000_0000_0000 R/W R/W Addr 0x10886 15 Field 13 — 12 11 10 I2O_ DBMC NMI IRA Reset 9 8 7 6 5 4 I2O_ I2O_ PERR_ PERR_ PCI_ TAR_ IPQO OFQO WR RD SERR ABT 3 NO_ RSP 2 1 0 DATA_ DATA_ ADDR_ PAR_ PAR_ PAR WR RD 0000_0000_0000_0000 R/W R/W Addr 0x10884 Figure 9-23. Error Status Register (ESR) Table 9-10. describes ESR fields. Table 9-10. ESR Field Descriptions Bits Name Description 31–13 — 12 I2O_DBMC Reserved, should be cleared.
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PCI Bridge Table 9-10. ESR Field Descriptions (continued) Bits Name Description 3 PCI_NO_RSP 2 PCI_DATA_PAR_RD PCI read data parity error. 1 PCI_DATA_PAR_WR PCI write data parity error. 0 PCI_ADDR_PAR PCI no response (no DEVSEL; master abort). PCI address parity error (read or write). 9.11.1.
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PCI Bridge Table 9-11. EMR Field Descriptions (continued) Bits Name Description 7 PCI_PERR_WR PCI parity error received on a write. The PowerQUICC II sinks PERR. This error is only a function of data. 6 PCI_PERR_RD PCI parity error received on a read. The PowerQUICC II sinks PERR. This error is only a function of data. 5 PCI_SERR 4 PCI_TAR_ABT PCI target abort 3 PCI_NO_RSP PCI no response (no DEVSEL; master abort). 2 PCI_DATA_PAR_RD PCI read data parity error.
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PCI Bridge Table 9-12. ECR Field Descriptions Bits Name Description 31–13 — 12 I2O_DBMC 11 NMI General error/interrupt indication. 10 IRA Illegal register access with incorrect size. 9 I2O_IPQO I2O inbound post queue overflow. 8 I2O_OFQO I2O outbound free queue overflow. 7 PCI_PERR_WR PCI parity error received on a write. 6 PCI_PERR_RD PCI parity error received on a read. 5 PCI_SERR 4 PCI_TAR_ABT PCI Target Abort 3 PCI_NO_RSP PCI no response (no DEVSEL; master abort).
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PCI Bridge Table 9-13. PCI_EACR Field Descriptions Bits Name Description 31–0 PCI_EAR The address associated with the first error captured. 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) The PCI error data capture register (PCI_EDCR), shown in Figure 9-27, stores the data associated with the first PCI error captured. 31 16 Field PCI_EDR Reset 0000_0000_0000_0000 R/W R/W Addr 0x1089A 15 0 Field PCI_EDR Reset 0000_0000_0000_0000 R/W R/W Addr 0x10898 Figure 9-27.
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PCI Bridge 31 Field 30 — 28 27 FET 24 23 BN Reset 21 — 20 19 16 TS ES 0000_0000_0000_0000 R/W R/W Addr 0x108A2 15 Field 22 12 11 CMD 8 7 4 — Reset 3 BE 2 — 1 0 PB VI 0000_0000_0000_0000 R/W R/W Addr 0x108A0 Figure 9-28. PCI Error Control Capture Register (PCI_ECCR) Table 9-15 describes PCI_ECCR fields. Table 9-15. PCI_ECCR Field Descriptions Bits Name Description 31 — 30–28 First error type Reserved, should be cleared. Type of first PCI error captured.
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PCI Bridge Table 9-15. PCI_ECCR Field Descriptions (continued) Bits Name Description 1 Parity bit Parity bit for PCI bus data word. 0 Valid info When this bit is set, the PCI bus error capture registers (PCI_EACR, PCI_EDCR, and PCI_ECCR) contain valid information. Writing ‘0’ to this bit enables the capture of a new error in the PCI bus error capture registers (PCI_EACR, PCI_EDCR, and PCI_ECCR). 9.11.1.
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PCI Bridge in a PIBARx register causes a change in the GPLABARx in the base address bits that are non-masked by PICMRx, and vice versa. The system host is responsible for the configuration of the base address by writing to GPLABARx; therefore, in PCI agent mode, the PIBARx registers should be read-only. However, if the PCI bridge is defined as the PCI host, it may be easier to configure its own inbound base address by writing directly to the PIBARx registers.
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PCI Bridge 31 Field EN 30 29 NO_ SNOOP_ PRE EN Reset 28 20 19 16 — CM 0000_0000_0000_0000 R/W R/W Addr 0x108FA (PICMR0); 0x108E2 (PICMR1) 15 0 Field CM Reset 0000_0000_0000_0000 R/W R/W Addr 0x108F8 (PICMR0); 0x108E0 (PICMR1) Figure 9-31. PCI Inbound Comparison Mask Registers (PICMRx) Table 9-18. describes PICMRx. Table 9-18.
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PCI Bridge 9.11.2 PCI Bridge Configuration Registers The PCI Local Bus Specification defines the configuration registers from 0x00 through 0x3F. Additionally, the PCI bridge specifies these additional registers: the PCI function register (at offset 0x44), the PCI arbiter control register (at offset 0x46), and the PCI Hot Swap register block (at offset 0x48). Table 9-19 and Figure 9-32 shows the PCI configuration registers provided by the PCI bridge for the PCI bus.
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PCI Bridge Table 9-19. PCI Bridge PCI Configuration Registers (continued) Address (offset) Register Access Reset Section/Page 3E MIN GNT R 0x00 9.11.2.20/9-57 3F MAX LAT R 0x00 9.11.2.21/9-58 40 Reserved — — 44 PCI function R/W 0x0000 46 PCI arbiter control register R/W 48 Hot swap register block R/W — 9.11.2.22/9-58 Mode-dependent 9.11.2.23/9-59 0x00nn_0006 9.11.2.24/9-60 9.11.2.
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PCI Bridge 15 0 Field VID Reset 0001_0000_0101_0111 R/W R Addr 0x00 Figure 9-33. Vendor ID Register Table 9-20. Vendor ID Register Description Bits Name 15–0 Vendor ID 9.11.2.2 Description Identifies the manufacturer of the device (0x1057 = Freescale) Device ID Register Figure 9-34 and Table 9-21 describes the device ID register. 15 0 Field DID Reset 0001_1000_1100_0000 R/W R Addr 0x02 Figure 9-34. Device ID Register Table 9-21.
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PCI Bridge Table 9-22. PCI Bus Command Register Description Bits Name 15–10 — 9 Fast back-to-back 8 SERR 7 — 6 Parity error response 5 — 4 Memory-write-andinvalidate Hardwired to 0, indicating that the PCI bridge acting as a master does not generate the memory-write-and-invalidate command. The PCI bridge generates a memory-write command instead. 3 Special-cycles Hardwired to 0, indicating that the PCI bridge as a target ignores all special-cycle commands.
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PCI Bridge 15 14 13 12 11 10 9 8 7 Field DPERR SSERR RM-A RT-A ST-A DEVSEL_T DPD FB-BC Reset 6 5 4 — 66MHzC CL 3 0 — 0000_0000_1011_0000 R/W R/W Addr R R/W 0x06 Figure 9-36. PCI Bus Status Register Table 9-23. describes the PCI bus status register fields. Table 9-23.
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PCI Bridge 7 0 Field RID Reset Refer to Table 9-24. R/W R Addr 0x08 Figure 9-37. Revision ID Register Table 9-24. Revision ID Register Description Reset Value Bits Name 7–0 Revision ID 9.11.2.6 Description Revision Specifies a device-specific revision code for the PowerQUICC II Dependent (assigned by Freescale). Revision ID = 0x11 for .25 micron revisions A.0, B.1, and C.
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PCI Bridge 7 0 Field SC Reset 0000_0000 R/W R Addr 0x0A Figure 9-39. Subclass Code Register Table 9-26. Subclass Code Register Description Bits Name 7–0 Subclass code 9.11.2.8 Description Identifies more specifically the function of the PCI bridge (0x00 = host bridge) PCI Bus Base Class Code Register Figure 9-40 and Table 9-27 describe the PCI bus class code register. 7 0 Field BCC Reset Refer to Table 9-27. R/W R Addr 0x0B Figure 9-40.
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PCI Bridge 7 0 Field CLS Reset 0000_0000 R/W R/W Addr 0x0C Figure 9-41. PCI Bus Cache Line Size Register Table 9-28. PCI Bus Cache Line Size Register Description Bits Name Description 7–0 Cache line size Represents the cache line size of the system in terms of 32-bit words (eight 32-bit words = 32 bytes). This register is read-write; however, an attempt to program this register to any value other than 8 results in it being cleared. 9.11.2.
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PCI Bridge 7 Field 6 0 MD HT Reset 0000_0000 R/W R Addr 0x0E Figure 9-43. Header Type Register Table 9-30. Header Type Register Description Bits Name Description 7 Multifunction device 6–0 Header type The PCI bridge is not a multifunction PCI device. Identifies the layout of bytes 0x10–0x3F of the configuration address space. 9.11.2.12 BIST Control Register Figure 9-44 and Table 9-31 describe the BIST control register.
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PCI Bridge 31 17 Field BA Reset 16 BA 0000_0000_0000_0000 R/W R/W Addr 0x12 15 4 Field BA Reset 3 2 PRE 1 T 0 MSI 0000_0000_0000_0000 R/W R/W Addr 0x10 Figure 9-45. PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR) Table 9-32 describes PIMMRBAR fields. Table 9-32. PIMMRBAR Field Descriptions Bits Name 31–17 Base address Indicates the base address for the inbound configuration window.
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PCI Bridge 31 16 Field BA Reset 0000_0000_0000_0000 R/W R/W Addr 0x16 (GPLABAR0); 0x1A (GPLABAR1) 15 12 Field 11 4 BA BA Reset 3 PRE 2 1 T 0 MSI 0000_0000_0000_0000 R/W R/W Addr 0x14 (GPLABAR0); 0x18 (GPLABAR1) Figure 9-46. General Purpose Local Access Base Address Registers (GPLABAR x) Table 9-33 describes GPLABARx fields. Table 9-33. GPLABARx Field Descriptions Bits Name Description 31–12 Base address Represents the base address for the inbound GPLA memory window.
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PCI Bridge Table 9-34. Subsystem Vendor ID Register Description Bits Name Description 15–0 Vendor ID Identifies the add-in board or subsystem where the PCI device resides. 9.11.2.16 Subsystem Device ID Register Figure 9-48 and Table 9-35 describe the subsystem ID register. 15 0 Field SDID Reset 0000_0000_0000_0000 R/W R/W Addr 0x2E Figure 9-48. Subsystem Device ID Register Table 9-35.
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PCI Bridge 7 0 Field IL Reset 0000_0000 R/W R/W Addr 0x3C Figure 9-50. PCI Bus Interrupt Line Register Table 9-37. PCI Bus Interrupt Line Register Description Bits Name Description 7–0 Interrupt line Contains the interrupt routing information. Software can use this register to hold information regarding which input of the system interrupt controller the INTA signal is attached to. Values in this register are specific to the system architecture. 9.11.2.
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PCI Bridge Table 9-39. PCI Bus MIN GNT Description Bits Name Description 7–0 MIN GNT Specifies the length of the device’s burst period. The value 0x00 indicates that the PCI bridge has no major requirements for the settings of latency timers. 9.11.2.21 PCI Bus MAX LAT Figure 9-53 and Table 9-40 describe the PCI bus MAX LAT register. 7 0 Field MAX LAT Reset 0000_0000 R/W R Addr 0x3F Figure 9-53. PCI Bus MAX LAT Table 9-40.
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PCI Bridge Table 9-41. PCI Bus Function Register Field Descriptions Bits Name Description 15–6 — 5 CFG_LOCK Reserved, should be cleared. Agent mode: Setting CFG_LOCK prevents an external PCI master from accessing the configuration space while the 60x bus is doing internal configuration. It is explicitly set and cleared by the 60x bus. 0 PCI bridge accepts accesses to the PCI configuration space or the internal memory-mapped configuration space.
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PCI Bridge Table 9-42. describes the PCI bus arbiter configuration register fields. Table 9-42. PCI Bus Arbiter Configuration Register Field Description Bit 15 Name Description PCI_ARB_DIS Determines if the PCI bridge is the PCI arbiter on the PCI bus. Set or cleared by (PCI_CFG[1] pin value) the PIC_CFG[1] pin value after hard reset. 0 PCI bridge is the PCI arbiter. 1 PCI bridge is not the PCI arbiter. The PCI bridge presents its request on REQ0 to the external arbiter and receives its grant on GNT0.
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PCI Bridge Table 9-43. Hot Swap Register Block Field Descriptions Bits Name Description 31–24 — 23–16 HS_CSR Hot Swap control status register; see Section 9.11.2.25, “PCI Hot Swap Control Status Register.” 15–8 NXT_PTR Next pointer—an offset into the device’s PCI configuration space for the location of the next item in the capabilities linked list. A value of 0x00 indicates that this is the last item in the list. 7–0 CAP_ID Reserved. Should be cleared.
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PCI Bridge 9.11.2.26 PCI Configuration Register Access from the Core The 60x bus master cannot directly access the PCI configuration registers because they are not in the internal memory-mapped configuration register’s space. The 60x bus master must first load CFG_ADDR (at offset 0x10900 in the memory-mapped configuration registers block) with a 32-bit register address in the form ‘0x8000_0nnn,’ where nnn is the address offset of the desired PCI configuration register.
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PCI Bridge 9.11.2.27.1 Additional Information on Endianess The endianess of both the MPC826x's peripheral logic (GPCR[LE_MODE]—see the following section) and the MPC826x's 603e CPU core (MSR[LE]) must be set to the same endianess configuration—that is both must be set for little or big endian operation.
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PCI Bridge Therefore, to set CTM in PCI DMA0 mode register, 0x00000004 is written to 0x04710504. 9.11.2.28 Initializing the PCI Configuration Registers The configuration registers are initialized to the reset values shown in the register descriptions. However, they can also be initialized to user-defined values loaded directly from the EEPROM used to configure the PowerQUICC II by setting the ALD_EN (auto-load enable) bit in the hard reset configuration word; refer to Section 5.4.
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PCI Bridge • Accesses to PCI configuration registers are indirect (through PCI CFG_ADDR and PCI CFG_DATA). A pointer located at address 0x4 of the EEPROM (right after the hard reset configuration word) defines the beginning of the initialization table. The table should be placed beyond the reset configuration data to avoid the EEPROM bytes dedicated to the eight possible hard reset configuration words (refer to Section 5.4.1, “Hard Reset Configuration Word,” and Figure 9-59).
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PCI Bridge turn causes an interrupt to the local processor that implements the PowerPC architecture because the register indirectly drives an interrupt line to the local processor. The outbound register allows the local processor to write an outbound message which, in turn, causes the outbound interrupt signal INTA to assert. The interrupt to the local processor is cleared by setting the appropriate bit in the inbound message interrupt status register.
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PCI Bridge 31 16 Field OMSGx Reset Undefined R/W R/W Addr 0x1045A (OMR0); 0x1045E (OMR1) 15 0 Field OMSGx Reset Undefined R/W R/W Addr 0x10458 (OMR0); 0x1045C (OMR1) Figure 9-61. Outbound Message Registers (OMRx) Table 9-47. OMRx Field Descriptions Bits Name 31–0 OMSGx 9.12.2 Description Outbound message x. Contains generic data to be passed between the local processor and external hosts. Door Bell Registers The PCI bridge contains an inbound and an outbound door bell register.
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PCI Bridge 31 29 Field 28 16 ODRx — Reset 0000_0000_0000_0000 R/W Refer to Table 9-48. Addr 0x10462 15 0 Field ODRx Reset 0000_0000_0000_0000 R/W Refer to Table 9-48. Addr 0x10460 Figure 9-62. Outbound Doorbell Register (ODR) Table 9-48. ODR Field Descriptions Bits Name 31–29 — 28–0 ODRx 9.12.2.2 Access R Description Reserved, should be cleared. Write 1 to set from local processor. Outbound door bell x, where x is each bit. Writing a bit in Write 1 to clear from PCI.
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PCI Bridge Table 9-49. IDR Field Descriptions Bits Name Access Description 31 IMC Write 1 to set from PCI. Machine check. Writing to this bit will generate a machine Write 1 to clear from local processor. check interrupt to the local processor. 30–0 IDRx Write 1 to set from PCI. Inbound door bell x, where x is each bit. Writing a bit in this Write 1 to clear from local processor. register from the PCI bus causes an interrupt to be generated through the PCI bridge to the local processor. 9.12.
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PCI Bridge Local memory Inbound free list FIFO Local processor write Head pointer MFA MFA MFA Inbound post list FIFO Tail pointer PCI master read PCI master write Inbound queue port Local processor read Head pointer MFA MFA MFA MFA Tail pointer MFA Outbound free list FIFO Local processor read Head pointer PCI master write PCI master read MFA MFA MFA Outbound post list FIFO Tail pointer Outbound queue port Head pointer Local processor write Tail pointer MFA MFA MFA MFA MFA Message frame Messa
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PCI Bridge The following registers should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus have undefined results. 9.12.3.2.1 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound Free_FIFO Tail Pointer Register (IFTPR) The inbound free list FIFO holds the list of empty inbound MFAs. The external PCI master reads IFQPR (refer to Section 9.12.3.4.
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PCI Bridge 31 20 Field 19 16 QBA Reset IFTP 0000_0000_0000_0000 R/W R R/W Addr 0x104AA 15 2 Field IFTP Reset 1 0 — 0000_0000_0000_0000 R/W R R/W Addr 0x104A8 Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTPR) Table 9-51. IFTPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20. 19–2 IFTP Inbound free_FIFO tail pointer. Local memory offset of the tail pointer of the inbound free list FIFO.
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PCI Bridge 31 Field 20 19 16 QBA Reset IPHP 0000_0000_0000_0000 R/W R R/W Addr 0x104B2 15 2 Field 1 IPHP Reset 0 — 0000_0000_0000_0000 R/W R R/W Addr 0x104B0 Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHPR) Table 9-52. IPHPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20. 19–2 IPHP Inbound post_FIFO head pointer. Local memory offset of the head pointer of the inbound post list FIFO.
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PCI Bridge Table 9-53. IPTPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20. 19–2 IPTP Inbound post_FIFO tail pointer. Local memory offset of the tail pointer of the inbound post list FIFO. 1–0 — Reserved, should be cleared. 9.12.3.3 Outbound FIFOs The outbound queues are used to send messages from the local processor to a remote host processor.
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PCI Bridge Table 9-54. OFHPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR. 19–2 OFHP Outbound free_FIFO head pointer. Local memory offset of the head pointer of the outbound free list FIFO. 1–0 — Reserved, should be cleared. Free MFAs are picked up by the local processor pointed to by the outbound free_FIFO tail pointer register, described in Figure 9-70 and Table 9-55. This register is updated by the local processor.
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PCI Bridge An external PCI master reads the outbound queue port register. This causes the PCI bridge’s I2O unit to read the MFA from local memory pointed to by the OPTPR+QBAR. The unit then advances the OPTPR. When the FIFO is empty (head and tail pointers are equal), the unit returns 0xFFFF_FFFF. The local processor posts MFAs to the outbound post list FIFO that is pointed to by the outbound post_FIFO head pointer register, described in Figure 9-71 and Table 9-56.
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PCI Bridge 31 20 Field 19 QBA Reset 16 OPTP 0000_0000_0000_0000 R/W R R/W Addr 0x104DA 15 2 Field OPTP Reset 1 0 — 0000_0000_0000_0000 R/W R R/W Addr 0x104D8 Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPTPR) Table 9-57. OPTPR Field Descriptions Bits Name Description 31–20 QBA Queue base address. When read returns the contents of QBAR bits 31-20. 19–2 OPTP Outbound post_FIFO tail pointer. Local memory offset of the tail pointer of the outbound post list FIFO.
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PCI Bridge Table 9-58. IFQPR Field Descriptions Bits 31–0 Name IFQP 9.12.3.4.2 Description Inbound FIFO queue port. Reading this register will return the MFA from inbound free list FIFO. Writing to this register will post the MFA to the inbound post list FIFO. Outbound FIFO Queue Port Register (OFQPR) OFQPR is used by PCI masters to access outbound messages in local memory. Local processor does not have access to this port. OFQPR should be accessed only from the PCI bus.
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PCI Bridge 31 16 Field — Reset 0000_0000_0000_0000 R/W Refer to Table 9-60. Addr 0x10432 15 6 Field — Reset 5 4 3 2 OPQI — ODI — 1 0 OM1I OM0I 0000_0000_0000_0000 R/W Refer to Table 9-60. Addr 0x10430 Figure 9-75. Outbound Message Interrupt Status Register (OMISR) Table 9-60 describes OMISR fields. Table 9-60. OMISR Field Descriptions Bits 31–6 1 Name R/W Description — R Reserved, should be cleared. 5 OPQI R Outbound post queue interrupt.
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PCI Bridge 31 16 Field — Reset 0000_0000_0000_0000 R/W Refer to Table 9-61. Addr 0x10436 15 6 Field — Reset 5 4 3 2 OPQIM — ODIM — 1 0 OM1IM OM0IM 0000_0000_0000_0000 R/W Refer to Table 9-61. Addr 0x10434 Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR) Table 9-61 describes OMIMR fields. Table 9-61. OMIMR Field Descriptions Bits 31–6 Name — R/W R Reserved, should be cleared.
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PCI Bridge 31 16 Field — Reset 0000_0000_0000_0000 R/W Refer to Table 9-62. Addr 0x10482 15 9 Field — 8 7 OFOI IPOI Reset 6 5 4 3 2 1 0 — IPQI MCI IDI — IM1I IM0I 0000_0000_0000_0000 R/W Refer to Table 9-62. Addr 0x10480 Figure 9-77. Inbound Message Interrupt Status Register (IMISR) Table 9-62 describes IMISR fields. Table 9-62. IMISR Field Descriptions Bits 31–9 Name — Access R Description Reserved, should be cleared.
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PCI Bridge 9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR) This register contains the interrupt mask of the I2O, door bell, and message register events generated by the PCI master. IMIMR should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus have undefined results.
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PCI Bridge Table 9-63. IMIMR Field Descriptions (continued) Bits Name Description 1 IM1IM Inbound message 1 interrupt mask 0 Inbound doorbell interrupt is allowed. 1 Inbound doorbell interrupt is masked. 0 IM0IM Inbound message 0 interrupt mask 0 Inbound message 0 interrupt is allowed. 1 Inbound message 0 interrupt is masked. 9.12.3.4.7 Messaging Unit Control Register (MUCR) This register allows software to enable and setup the size of the inbound and outbound FIFOs.
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PCI Bridge Table 9-64. MUCR Field Descriptions Bits Name Access Description 5–1 CQS RW Circular queue size. CQS refers to each individual queue, not the total size of all four queues together. 00001 4K entries (16 Kbytes) 00010 8K entries (32 Kbytes) 00100 16K entries (64 Kbytes) 01000 32K entries (128 Kbytes) 10000 64K entries (256 Kbytes) All others reserved. 0 CQE RW Circular queue enable. When set will allow PCI masters to access the inbound and outbound queue ports.
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PCI Bridge 9.13 DMA Controller The PCI bridge’s DMA controller transfers blocks of data independent of the local core or PCI hosts. Data movement occurs on the PCI and/or 60x bus. The PCI Bridge’s DMA module has four high-speed DMA channels with an aggregate bandwidth conservatively estimated at 210 Mbytes per second, for 60x to PCI transfer. The channels share 144 bytes of DMA-dedicated buffer space to facilitate the gathering and sending of data.
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PCI Bridge address. The DMA controller assumes that the source and destination addresses are valid PCI or 60x memory addresses. All 60x memory read operations are cache line reads (32 bytes); the DMA controller selects the appropriate/valid data bytes within the cache line when loading its internal queue. Writing to 60x memory depends on the alignment of the destination address and the size of the transfer. The DMA controller writes a full cache line whenever possible.
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PCI Bridge • First clear then set the CS (channel start) bit in the mode register to start the DMA transfer. 9.13.1.3 DMA Coherency The four DMA channels are allocated 4 cache lines (128 bytes) of buffer space in the I/O sequencer module in addition to 16 bytes of local buffer space. Because no address snooping occurs in these internal queues, data posted in these queues is not visible to the rest of the system while a DMA transfer is in progress.
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PCI Bridge • • 60x bus, or when no data is left to transfer. Reading from PCI memory and writing to 60x memory can occur concurrently. 60x-memory-to-PCI-memory transfers—The DMA controller initially fetches data from 60x memory into the DMA queue. As soon as the first data arrives into the queue, the DMA engine initiates write transactions to PCI memory. The DMA controller stops the transfer either when there is an error on the PCI bus or 60x bus, or there is no more data left to transfer.
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PCI Bridge Table 9-66. DMAMRx Field Descriptions Bits Name Description 31–24 — Reserved, should be cleared. 23–21 BWC Bandwidth control. This field only applies when multiple channels are executing transfers concurrently. The field determines how many cache lines a given Channel is allowed to transfer after it is granted access to the IOS interface and before it releases the interface to the next channel. This allows the user to prioritize DMA Channels.
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PCI Bridge Table 9-66. DMAMR x Field Descriptions (continued) Bits Name 7 Description EOTIE End-of-transfer interrupt enable. When set will generate an interrupt at the completion of a DMA transfer. No EOT interrupt is generated if this bit is cleared. End of transfer is defined as the end of a direct mode transfer or in chaining mode, as the end of the transfer of the last segment of a chain. — Reserved, should be cleared. 3 TEM Transfer error mask.
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PCI Bridge Table 9-67. DMASRx Field Descriptions Bits Name Access Description 31–8 — RW Reserved, should be cleared. 7 TE Read/ Write 1 to clear 6–3 — R 2 CB Read Only Channel busy. When set indicates that a DMA transfer is currently in progress. This bit will be cleared as a result of any of the three following conditions: (1) an error, (2) a halt, or (3) completion of the DMA transfer. 1 EOSI Read/ Write 1 to clear End-of-segment interrupt.
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PCI Bridge Table 9-68. DMACDAR x Field Descriptions Bits 31–5 Name Description CDA Current descriptor address. Contains the current descriptor address of the segment descriptor in memory. It must be aligned on an 8-word boundary. 4 SNEN Snoop enable. When set will allow snooping on DMA transactions. 3 EOSIE End-of-segment interrupt enable. When set will generate an interrupt if the current DMA transfer for the current descriptor is finished. — Reserved, should be cleared.
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PCI Bridge The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI outbound windows, then the destination data is written to the PCI memory. Otherwise, it is written to the 60x memory. Refer to Figure 9-13.
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PCI Bridge Table 9-71. DMABCRx Field Descriptions Bit Name Description 31–26 — Reserved, should be cleared. 25–0 BC Byte count. Contains the number of bytes to transfer. The value in this register is decremented after each DMA read operation. DMA Next Descriptor Address Register [0–3] (DMANDARx) 9.13.1.6.7 The next descriptor address register (NDAR) contains the address for the next segment descriptor in the chain.
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PCI Bridge 9.13.2 DMA Segment Descriptors DMA segment descriptors contain the source and destination addresses of the data segment, the segment byte count, and a link to the next descriptor. Segment descriptors are built on cache-line (32-byte) boundaries in either 60x or PCI memory and are linked together into chains using the next-descriptor-address field. Table 9-73. DMA Segment Descriptor Fields Descriptor Field Description Source address Contains the source address of the DMA transfer.
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PCI Bridge Current descriptor address register 31 0 Next descriptor address register 31 0 Local memory or PCI memory Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Source address Reserved Destination address Reserved Next descriptor Reserved Byte count Reserved 31 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Descriptor 0 0 Source address Reserved Destination address Reserved Next descriptor Reserved Byte count Reserved 31 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Descriptor 1 0 Source addr
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PCI Bridge Byte Count = 0x67452301 9.13.2.2 Descriptor in Little Endian Mode In little endian mode, the descriptor in PCI memory should be programmed such that data appears in descending significant byte order. If segment descriptors are written to memory located in the PCI bus, they are obeying the rules for little endian mode. Example: Little Endian mode descriptor’s data structure. Note that the descriptor structure must be aligned on an 8-word boundary.
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PCI Bridge 9.14.1.1.1 System Error (SERR) The SERR signal is used to report PCI address parity errors. It is driven for a single PCI clock cycle by the agent that is reporting the error. The agent responsible for driving AD[31–0] on a given PCI bus phase is responsible for driving even parity one PCI clock later on the PAR signal. (That is, the number of 1’s on AD[31–0], PCI_C/BE[3–0], and PAR equals an even number.
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PCI Bridge 9.14.1.3.1 Address Parity Error If the PCI bridge is acting as a PCI master and the target detects and reports (by asserting SERR) a PCI address parity error, the PCI bridge sets bit 5 of the ESR and sets the detected parity error bit (bit 15) in the PCI status register. This setting of bit 15 is independent of the settings in the PCI command register.
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PCI Bridge 9.14.1.3.4 Target-Abort Error If a PCI transaction initiated by the PCI bridge is terminated by target-abort, the PCI bridge sets the received target-abort flag (bit 12) of the PCI status register and bit 4 of the error status register (refer to Section 9.11.1.9, “Error Status Register (ESR)”). Note that data transferred in a target-aborted transaction may be corrupt. 9.14.1.3.5 NMI This signal is captured in bit 11 of the ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”).
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Chapter 10 Clocks and Power Control The PowerQUICC II’s clocking architecture includes two PLLs—the main PLL and the core PLL. The clock block, which contains the main PLL, provides the following: • Internal clocks for all blocks in the chip except core blocks • Internal 60x bus clock in the chip • PCI clock (MPC8250, MPC8265, and MPC8266 only) The core input clock has the 60x bus frequency, which the core PLL multiplies by a configurable factor and provides to all core blocks.
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Clocks and Power Control 10.4 Main PLL The main PLL performs frequency multiplication and skew elimination. It allows the processor to operate at a high internal clock frequency using a low-frequency clock input, which has two immediate benefits: A lower clock input frequency reduces overall electromagnetic interference generated by the system, and oscillating at different frequencies eliminates the need for another oscillator to the system. 10.4.
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Clocks and Power Control output frequency is twice the CPM frequency. This double frequency is required to generate the CPM_CLK and CPM_CLK_90 clocks. See the block diagram in Figure 10-1. for details. On initial system power-up, power-on reset (PORESET) should be asserted by external logic for 16 input clocks after a valid level is reached on the power supply. Whenever power-on reset is asserted, SCMR[PLLMF, PLLDF] are programmed by the configuration pins.
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Clocks and Power Control cpm_clk PowerQUICC II PCI Interface pci_clk % Divider % bus_clk PCI Circuit dllout 60x Circuit PLL DLL bus_clk clkin2 clkin1 PCI Clock Bus Clock Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock 10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock In a system where the PowerQUICC II is the host that generates the PCI clock, the 60x bus clock should be driven to the CLKIN1 pin.
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Clocks and Power Control NOTE If a clock buffer is used in the feedback path from DLLOUT to CLKIN2, designers should ensure that the clock buffer does not include an internal PLL as this may cause an unacceptable jitter on the clock signals. 10.4.3.2.1 CPM CLOCK and PCI Frequency Equations The relation between CPM CLOCK frequency and PCI frequency is as follows.
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Clocks and Power Control 10.7 PLL Pins Table 10-1 shows dedicated PLL pins. Table 10-1. Dedicated PLL Pins Signal Description VCCSYN Drain voltage—Analog VDD dedicated to core analog PLL circuits. To ensure core clock stability, filter the 1 power to the VCCSYN1 input with a circuit similar to the one in Figure 10-4. To filter as much noise as possible, place the circuit as close as possible to VCCSYN1. The 0.
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Clocks and Power Control Table 10-1. Dedicated PLL Pins (continued) Signal Description XFC External filter capacitor—Connects to the off-chip capacitor for the main PLL filter. One terminal of the capacitor is connected to XFC while the other terminal is connected to VCCSYN. 30 MΩ is the minimum parasitic resistance value that ensures proper PLL operation when connected in parallel with the XFC capacitor.
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Clocks and Power Control 10.8 System Clock Control Register (SCCR) The system clock control register (SCCR), shown in Figure 10-5, is memory-mapped into the PowerQUICC II’s internal space. 0 15 Field — Reset — R/W R/W Addr 0x0x10C80 16 22 Field — Reset — 23 24 25 PCI_MODE1 PCI_MODCK1 — 0 R/W 29 30 31 CLPD DFBRG — 0 01 R R/W Addr 28 PCIDF1 R/W 0x10C82 Figure 10-5. System Clock Control Register (SCCR) 1 MPC8250, MPC8265, and MPC8266 only.
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Clocks and Power Control Table 10-2. SCCR Field Descriptions (continued) Defaults Bits Name Description POR 29 CLPD 30–31 DFBRG 1 Hard Reset 0 Unaffected CPM low power disable. 0 Default. CPM does not enter low power mode when the core enters low power mode. 1 CPM and SIU enter low power mode when the core does. This may be useful for debug tools that use the assertion of QREQ as an indication of breakpoint in the core. Note: When the core is disabled, CLPD must be cleared.
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Clocks and Power Control Table 10-3. SCMR Field Descriptions Defaults Bits Name Description POR Hard Reset — 0–2 — — 3–7 CORECNF Config pins Unaffected Core configuration. PLL configuration of the core. These values are reflect the values of PLL_CFG[0:5], described in Table 10-4. 8–11 BUSDF Config pins Unaffected 60x bus division factor 12–15 CPMDF Config pins Unaffected CPM division factor. This value is always 1. 16–18 — — 19 PLLDF Config pins Unaffected PLL pre-divider factor.
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Clocks and Power Control Table 10-4. 60x Bus-to-Core Frequency SCMR[CORECNF] Bus-to-Core Multiplier VCO Divider 0x02 1x 8 0x01 1x 4 0x0C 1.5x 8 0x00 1.5x 4 0x05, 0x15 2x 4 0x04 2x 2 0x11 2.5x 4 0x06 2.5x 2 0x10 3x 4 0x08 3x 2 0x0E,0x1E 3.5x 2 0x0A, 0x1A 4x 2 0x07, 0x17 4.5x 2 0x0B, 0x1B 5x 2 0x09, 0x19 5.5x 2 0x0D, 0x1D 6x 2 0x12, 6.5x 2 0x14 7x 2 0x16 7.
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Clocks and Power Control The PowerQUICC II supports the two following power modes: • Full mode—Both the chip PLL and core PLL work. • Stop mode—Main PLL is working, core PLL is stopped, and internal clocks are disabled. — When stop mode is entered, software sets the sleep bit in the core (HID0[10] = 1) and the clock block freezes all clocks to the chip (the core clock and all other clocks) the main PLL remains active.
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Chapter 11 Memory Controller The memory controller is responsible for controlling a maximum of twelve memory banks sharing a high performance SDRAM machine, a general-purpose chip-select machine (GPCM), and three user-programmable machines (UPMs). It supports a glueless interface to synchronous DRAM (SDRAM), SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals.
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Memory Controller • • • 18-bit address and 32-bit local data bus memory controller. The local bus memory controller supports the following: — 8-, 16-, and 32-bit port sizes — Parity checking and generation — Ability to work in parallel with the 60x bus memory controller Flexible chip-select assignment—The 60x bus and local bus share twelve chip-select lines (controlled by a memory controller bank). The user can allocate the twelve banks as needed between the 60x bus and the local bus.
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Memory Controller 11.
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Memory Controller — User-specified control-signal patterns run when an internal or external master requests a single-beat or burst read or write access.
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Memory Controller MxMR[BS] Bank 0 MS 60x Bank 1 MS Bank 2 MS User-Programmable Machine (A/B/C) Local 60x SDRAM Machine Bank 3 60x MS Local SDRAM Machine 60x General-Purpose Chip-Select Machine Bank 10 MS Bank11 MS Local General-Purpose Chip-Select Machine Local 60x Local Figure 11-2. Memory Controller Machine Selection Some features are common to all machines.
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Memory Controller EPROM PowerQUICC II Address GPCM CS0 GPL2/OE BS/WE[0–7] Data Address CE OE WE Data DRAM Address CS1 UPMA GPLx RAS CAS[0–7] W Data Figure 11-3. Simple System Configuration Implementation differences between the supported machines are described in the following: • The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM devices, and using SDRAM pipelining, page mode, and bank interleaving delivers very high performance.
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Memory Controller Internal/External Memory Access Request Select Address (A), Address Type (AT) Address Comparator Bank Select SDRAM Machine UPMx GPCM Signals Timing Generator MS/BS Fields MUX External Signals Figure 11-4. Basic Memory Controller Operation The SDRAM mode registers (LSDMR and PSDMR) define the global parameters for the 60x and local SDRAM devices. Machine A/B/C mode registers (MxMR) define most of the global features for each UPM.
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Memory Controller register each time a bus-cycle access is requested. If a match is found together with bank match, the bus cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus becomes idle, unless ORx[PMS] is set. 11.2.3 Error Checking and Correction (ECC) ECC can be configured for any bank as long as it is assigned to the 60x bus and is connected to a 64-bit port size memory.
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Memory Controller • • An ECC double-bit error An ECC single bit error when the maximum number of ECC errors has been reached 11.2.7 Data Buffer Controls (BCTLx and LWR) The memory controller provides two data buffer controls for the 60x bus (BCTL0 and BCTL1) and one for the local bus (LWR). These controls are activated when a GPCM- or UPM-controlled bank is accessed and can be disabled by setting ORx[BCTLD]. An access to an SDRAM-machine controlled bank does not activate the BCTLx controls.
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Memory Controller Note that this feature cannot be used with L2 cacheable banks and that in systems that involve both PowerQUICC II-type masters and 60x compatible master, this feature can still be used on the 60x bus under the following restrictions: 1. The arbiter and the memory controller are in the same PowerQUICC II. 2. The register field BCR[NPQM] is setup correctly. See “Section 11.9, “External Master Support (60x-Compatible Mode)” and “Section 4.3.2.1, “Bus Configuration Register (BCR).” 11.2.
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Memory Controller 11.2.13 Partial Data Valid Indication (PSDVAL) The 60x and local buses have an internal 64-bit data bus. According to the 60x bus specification, TA is asserted when up to a double word of data is transferred. Because the PowerQUICC II supports memories with port sizes smaller than 64 bits, there is a need for partial data valid indication. The memory controller uses PSDVAL to indicate that data is latched by the memory on write accesses or valid data is present on read accesses.
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Memory Controller 11.2.14 BADDR[27:31] Signal Connections The memory controller uses BADDR[27:31] to interface memory and peripheral devices on the 60x bus in 60x-compatible mode. Not all the BADDR line are necessarily used. Use Table 11-2 to determine which BADDR lines are needed for the device connection. Table 11-2. BADDR Connections Non-SDRAM 32-Bit Port Size Device Any 16-Bit Port Size Device BADDR[x] Non-SDRAM 64/72-Bit Port 64-/72-Bit Port Size SDRAM Size Device BADDR[27] N.C. Connected N.C.
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Memory Controller Base Registers (BRx) 11.3.1 The base registers (BR0–BR11) contain the base address and address types that the memory controller uses to compare the address bus value with the current address accessed. Each register also includes a memory attribute and selects the machine for memory operation handling. Figure 11-7 shows the BRx register format.
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Memory Controller Table 11-4. BRx Field Descriptions (continued) Bits Name Description 23 WP Write protect. Can restrict write accesses within the address range of a BR. An attempt to write to this address range while WP = 1 can cause TEA to be asserted by the bus monitor logic (if enabled) which terminates the cycle. 0 Read and write accesses are allowed. 1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on write cycles to this memory bank.
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Memory Controller 11.3.2 Option Registers (ORx) The ORx registers define the sizes of memory banks and access attributes. The ORx attributes bits support the following three modes of operation as defined by BR[MS]. • SDRAM mode • GPCM mode • UPM mode Figure 11-7 shows the ORx as it is formatted for SDRAM mode. 0 11 Field 12 SDAM 15 LSDAM...
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Memory Controller Table 11-5. OR x Field Descriptions (SDRAM Mode) Bits Name Description 0–11 SDAM SDRAM address mask. Provides masking for corresponding BRx bits. By masking address bits independently, SDRAM devices of different size address ranges can be used. Clearing bits masks the corresponding address bit. Setting bits causes the corresponding address bit to be compared with the address pins.
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Memory Controller Table 11-5. ORx Field Descriptions (SDRAM Mode) (continued) Bits Name Description 26 PMSEL Page mode select. Selects page mode for the SDRAM connected to the memory controller bank. 0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle. 1 Page is kept open until a page miss or refresh occurs. 27 IBID Internal bank interleaving within same device disable.
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Memory Controller Table 11-6. OR x—GPCM Mode Field Descriptions (continued) Bits Name Description 19 BCTLD Data buffer control disable. Disables the assertion of BCTLx (60x bus) and LWR (local bus) during an access to the current memory bank. See Section 11.2.7, “Data Buffer Controls (BCTLx and LWR).” 0 BCTLx and LWR are asserted upon an access to the current memory bank. 1 BCTLx and LWR are not asserted upon an access to the current memory bank. 20 CSNT Chip-select negation time.
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Memory Controller NOTE GPCM produces a glitch on the BSx lines when the following memory controller settings are used: SETA = 1, CSNT = 1, ACS = 01, TRLX = 1, and SCY = 0000. During a write operation, the BSx are asserted for 3/4 of a cycle, negated for 1/4 of a cycle, and asserted again until the end of the cycle. Therefore, when the other conditions occur, it is necessary that SCY ≠ 0000. Figure 11-9 shows ORx as it is formatted for UPM mode. 0 15 Field AM...
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Memory Controller Table 11-7. Option Register (ORx)—UPM Mode Bits Name 23 BI Burst inhibit. Indicates if this memory bank supports burst accesses. 0 The bank supports burst accesses 1 The bank does not support burst accesses. The UPMx executes burst accesses as series of single accesses. 24–28 — Reserved, should be cleared. 29–30 31 11.3.3 Description EHTR Extended hold time on read accesses. Indicates how many cycles are inserted between a read access from the current bank and the next access.
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Memory Controller Table 11-8. PSDMR Field Descriptions Bits Name Description 0 PBI Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction with PSDMR[SDA10]. See Section 11.4.5, “Bank Interleaving.” 0 Bank-based interleaving (default at reset) 1 Page-based interleaving (recommended operation) 1 RFEN Refresh enable. Indicates that the SDRAM needs refresh services.
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Memory Controller Table 11-8. PSDMR Field Descriptions (continued) Bits Name Description SDRAM Device–Specific Parameters: 14–16 RFRC Refresh recovery. Defines the earliest timing for an activate command after a REFRESH command. Sets the refresh recovery interval in clock cycles. See Section 11.4.6.6, “Refresh Recovery Interval (RFRC),” for how to set this field.
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Memory Controller Table 11-8. PSDMR Field Descriptions (continued) Bits Name Description 28 EAMUX External address multiplexing enable/disable. 0 No external address multiplexing. Fastest timing. 1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE command to the SDRAM. This is useful when external address multiplexing can cause a delay on the address lines. Note that if this bit is set, ACTTORW should be a minimum of 2.
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Memory Controller Table 11-9. LSDMR Field Descriptions (continued) Bits Name Description 2–4 OP SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed. 000 Normal operation 001 CBR refresh, used in SDRAM initialization. 010 Self refresh (for debug purpose). 011 Mode Register write, used in SDRAM initialization. 100 Precharge bank (for debug purpose). 101 Precharge all banks, used in SDRAM initialization. 110 Activate bank (for debug purpose).
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Memory Controller Table 11-9. LSDMR Field Descriptions (continued) Bits Name Description SDRAM Device–Specific Parameters: 14–16 RFRC Refresh recovery. Defines the earliest timing for an activate command after a REFRESH command. Sets the refresh recovery interval in clock cycles. See Section 11.4.6.6, “Refresh Recovery Interval (RFRC),” for how to set this field.
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Memory Controller Table 11-9. LSDMR Field Descriptions (continued) Bits Name Description 28 EAMUX External address multiplexing enable/disable. 0 No external address multiplexing. Fastest timing. 1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE command to the SDRAM. This is useful when external address multiplexing can cause a delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least 2.
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Memory Controller Table 11-10. Machine x Mode Registers (MxMR) Bits Name Description 0 BSEL Bus select. Assigns banks that select UPMx to the 60x or local bus. 0 Banks that select UPMx are assigned to the 60x bus. 1 Banks that select UPMx are assigned to the local bus. Note: If refresh is required, the UPM’s should be assigned as follows: UPMA: 60x bus (if 60x bus refresh needed) UPMB: Local bus (if local bus refresh required) UPMC: Any bus, as long as UPMA or UPMB is used on the relevant bus.
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Memory Controller Table 11-10. Machine x Mode Registers (MxMR) (continued) Bits Name Description 10–12 G0CLx General line 0 control. Determines which address line can be output to the GPL0 pin when the UPMx is selected to control the memory access. 000 A12 001 A11 010 A10 011 A9 100 A8 101 A7 110 A6 111 A5 13 GPL_x4DIS GPL_A4 output line disable. Determines if the UPMWAIT/GTA/GPL_4 pin behaves as an output line controlled by the corresponding bits in the UPMx array (GPL4x).
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Memory Controller 0 15 Field MD Reset xxxx_xxxx_xxxx_xxxx1 R/W R/W Addr 0x0x10188 16 31 Field MD Reset xxxx_xxxx_xxxx_xxxx1 R/W R/W Addr 0x1018A 1 Undefined at reset. Figure 11-12. Memory Data Register (MDR) Table 11-11 describes MDR fields. Table 11-11. MDR Field Descriptions Bits Name 0–31 MD 11.3.7 Description Memory data. The data to be read or written into the RAM array when a WRITE or READ command is supplied to the UPM.
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Memory Controller Table 11-12. MAR Field Description Bits Name Description 0–31 A Memory address. The memory address register can be output to the address lines under control of the AMX bits in the UPM 11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT) The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 11-14. 0 7 Field PURT Reset 0000_0000 R/W R/W Addr 0x0x10198 Figure 11-14. 60x Bus-Assigned UPM Refresh Timer (PURT) Table 11-13 describes PURT fields. Table 11-13.
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Memory Controller Table 11-14. Local Bus-Assigned UPM Refresh Timer (LURT) Bits Name 0–7 LURT Description Refresh timer period.
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Memory Controller 0 7 Field LSRT Reset 0000_0000 R/W R/W Addr 0x0x101A4 Figure 11-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT) Table 11-16 describes LSRT fields. Table 11-16. LSRT Field Descriptions Bits Name 0–7 LSRT Description Refresh timer period.
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Memory Controller 11.3.13 60x Bus Error Status and Control Registers (TESCRx) These registers indicate the source of an error that caused TEA or MCP to be asserted on the 60x bus. See Section 4.3.2.10, “60x Bus Transfer Error Status and Control Register 1 (TESCR1),” and Section 4.3.2.11, “60x Bus Transfer Error Status and Control Register 2 (TESCR2).” 11.3.
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Memory Controller y PowerQUICC II DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 A[17] DQM1 DQM0 PSDDQM[0–7] PSDA10 12-bit A[19–28] D[0–63] CS[0–7] PSDRAS PSDWE PSDCAS CS7 FM CLK SOURCE CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0–11] DQ[0–7] CS7 x8 DATA[0–7] DATA[56–63] x8 CS0 CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0–11] DQ[0–7] CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0–11] DQ[0–7] x8 CS0 x8 DATA[0–7] CAS CS RAS WE 2x1M x8 CKE SDRAM CLK DQM ADDR[0–11] DQ[0–7] DATA[56–63] Figure 11-1
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Memory Controller 11.4.1 Supported SDRAM Configurations The PowerQUICC II memory controller supports any SDRAM configuration under the restrictions that all SDRAM devices that reside on the same bus (60x or local) should have the same port size and timing parameters. For more information, refer to Application Note 2165, “MPC8260 SDRAM Support” (order number AN2165/D). 11.4.
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Memory Controller Table 11-19. SDRAM Interface Commands Command Description BANK-ACTIVATE Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM sense amplifiers and must be restored with a PRECHARGE command before another BANK-ACTIVATE is issued. MODE-SET Allows setting of SDRAM options—CAS latency, burst type, and burst length.
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Memory Controller 11.4.5 Bank Interleaving The SDRAM interface supports bank interleaving. This means that if a missed page is in a different SDRAM bank than the currently open page, the SDRAM machine first issues an ACTIVATE command to the new page and later issues a DEACTIVATE command to the old page, thus eliminating the DEACTIVATE time overhead. This procedure can be done if both pages reside on different SDRAM devices or on different internal SDRAM banks.
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Memory Controller Note that in 60x-compatible mode, the 60x address must be latched and multiplexed by glue logic that is controlled by ALE and SDAMUX, however, the user still has to configure PSDMR[SDAM]. On the local bus, only the lower 18 bits of the address are output. Table 11-20 shows SDRAM address multiplexing for A0–A15. Table 11-20.
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Memory Controller • • • • • Last data out to precharge (P/LSDMR[LDOTOPRE]). Section 11.4.6.4, “Last Data Out to Precharge.” Write recovery, last data in to precharge (P/LSDMR[WRC]). See Section 11.4.6.5, “Last Data In to Precharge—Write Recovery.” Refresh recovery interval (P/LSDMR[RFRC]). See Section 11.4.6.6, “Refresh Recovery Interval (RFRC).” External address multiplexing present (P/LSDMR[EAMUX]). See Section 11.4.6.7, “External Address Multiplexing Signal.
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Memory Controller CLK ALE CS SDRAS SDCAS MA[0–11] Cbz Rbz WE DQM DATA D0 D1 D2 D3 ACTTORW = 2 ACTIVATE WRITE Command Command Figure 11-21. ACTTORW = 2 (2 Clock Cycles) 11.4.6.3 Column Address to First Data Out—CAS Latency As seen in Figure 11-22, this parameter, controlled by P/LSDMR[CL], defines the timing for first read data after a column address is sampled by the SDRAM.
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Memory Controller 11.4.6.4 Last Data Out to Precharge As shown in Figure 11-23, this parameter, controlled by P/LSDMR[LDOTOPRE], defines the earliest timing for the PRECHARGE command after the last data was read from the SDRAM. It is always related to the CL parameter. Activate Read Deactivate Last Data Out CLK LDOTOPRE = 2 ALE CS SDRAS SDCAS WE MA[0–11] Row Column DQM D0 Data D1 D2 D3 Figure 11-23. LDOTOPRE = 2 (-2 Clock Cycles) 11.4.6.
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Memory Controller 11.4.6.6 Refresh Recovery Interval (RFRC) As represented in Figure 11-25, this parameter, controlled by P/LSDMR[RFRC], defines the earliest timing for an ACTIVATE command after a REFRESH command. CLK ALE CS SDRAS SDCAS MA[0–11] A8 = 1 RAx WE DQM PRETOACT Precharge if needed RFRC = 4 (6 clocks) =3 Activate command Bank A Auto refresh Figure 11-25. RFRC = 4 (6 Clock Cycles) 11.4.6.
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Memory Controller P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory controller to add one cycle for each SDRAM command. Figure 11-27 illustrates the timing when BUFCMD equals 1. CLK ALE SDAMUX CMD strobes (without cs) Activate MA[0–11] NOP Row Read NOP Column CS Command setup cycle Command setup cycle Figure 11-27. BUFCMD = 1 11.4.7 SDRAM Interface Timing Figure 11-28 through Figure 11-36 show SDRAM timing for various types of accesses.
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Memory Controller CLK ALE CS SDRAS SDCAS Column Z MA[0–11] WE DQM D0 Data Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3 CLK ALE CS SDRAS SDCAS MA[0–11] Row Column WE DQM Data D1 D0 Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 Deactivate Activate CLK ALE CS SDRAS SDCAS MA[0–11] Z * BS A10 = 1 Row Col WE DQM Data D0 D1 D2 D4 * BS—Bank select according to SDRAM organization. A10 = 1 means all banks are precharged. CAS Latency = 3 Figure 11-31.
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Memory Controller CLK ALE CS SDRAS SDCAS Column MA[0–11] WE DQM D0 Data Figure 11-32. SDRAM Single-Beat Write, Page Hit CLK ALE CS SDRAS SDCAS MA[0–11] Row Column WE DQM Data D0 D1 D2 Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed CLK ALE CS SDRAS SDCAS MA[0–11] Column1 Z Column2 WE DQM D0 Data D1 D0 D1 DQM latency (affects negation only) = 2 Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Memory Controller CLK ALE CS SDRAS SDCAS Column1 MA[0–11] Column2 WE DQM D0 Data D1 D2 D3 D0 D1 D2 D3 Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit CLK ALE CS SDRAS SDCAS MA[0–11] Column1 Z Column2 WE DQM Data D0 D1 D2 D3 D0 D1 D2 D3 Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit 11.4.
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Memory Controller 11.4.9 SDRAM MODE-SET Command Timing The PowerQUICC II transfers mode register data (CAS latency, burst length, burst type) stored in P/LSDMR to the SDRAM array by issuing the MODE-SET command. Figure 11-37 shows timing for the MODE-SET command. Mode Set Page Activate Write (Burst) CLK ALE CS SDRAS SDCAS *Mode Data MA[0–11] Row Column WE DQM Z Data D0 D3 D2 D1 Z *The mode data is the address value during a mode-set cycle.
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Memory Controller There are two levels of refresh request priority—low and high. The low priority request is generated as soon as the refresh timer expires, this request is granted only if no other requests to the memory controller are pending. If the request is not granted (memory controller is busy) and the refresh timer expires two more times, the request becomes high priority and is served when the current memory controller operation finishes.
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Memory Controller 11.4.12.1 SDRAM Configuration Example (Page-Based Interleaving) Consider the following SDRAM organization: • 64-bit port size, organized as eight 64-Mbit devices, each organized as 8M x 8bits. • Each device has 4 internal banks, 12 rows, and 9 columns For page-based interleaving, the address bus should be partitioned as shown in Table 11-22. Table 11-22.
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Memory Controller Because AP alternates with A[7] of the row lines, set PSDMR[SDA10] = 011. This outputs A[7] on the SDA10 line during the ACTIVATE command and AP during READ/WRITE and CBR commands. Table 11-25 shows the register configuration. Not shown are PSRT and MPTPR, which should be programmed according to the device refresh requirements: Table 11-25.
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Memory Controller Now, from the SDRAM device point of view, during an ACTIVATE command, its address port should look like Table 11-27. Table 11-27. SDRAM Device Address Port during ACTIVATE Command “A[0–14]” A[15–16] A[17–28] A[29–31] — Internal bank select (A[6–7]) Row (A[8–19]) n.c. Table 11-20.
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Memory Controller The GPCM allows a glueless and flexible interface between the PowerQUICC II, SRAM, EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains two basic configuration register groups—BRx and ORx. Although GPCM does not support bursting, the internal logic will split a burst into individual beats that the GPCM can support. Therefore, the flash can be cached. Note that if the PowerQUICC II is in 60x-bus compatible mode, baddr[27–31] should be used instead of a[27–31].
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Memory Controller 11.5.1 Timing Configuration If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0–1], SCY[0–3], TRLX, EHTR, and SETA fields. Table 11-31 shows signal behavior and system response. Table 11-31.
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Memory Controller • • One quarter of a clock cycle later One half of a clock cycle later Note the GPCM does not negate CS in back-to-back reads to the same device when in single PowerQUICC II bus mode or in 60x-compatible bus mode with extended transfers enabled. When in strict 60x bus mode, however, the GPCM does negate CS in back-to-back reads. See Section 4.3.2.1, “Bus Configuration Register (BCR).” Figure 11-41 shows a basic connection between the PowerQUICC II and an external peripheral device.
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Memory Controller MEMORY PowerQUICC II Address Address CS CE OE OE WE W Data Data Figure 11-43. GPCM Memory Device Interface As Figure 11-45 shows, the timing for CS is the same as for the address lines. The strobes for the transaction are supplied by OE or WE, depending on the transaction direction (read or write). ORx[CSNT] controls the timing for the appropriate strobe negation in write cycles.
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Memory Controller Clock Address PSDVAL ACS = 11 ACS = 10 CS CSNT = 1 WE Data Figure 11-45. GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0) 11.5.1.3 Relaxed Timing ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When TRLX = 1 and ACS ≠ 00, an additional cycle between the address and strobes is inserted by the PowerQUICC II memory controller. See Figure 11-46 and Figure 11-47.
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Memory Controller Clock Address PSDVAL ACS = 10 ACS = 11 CS BCTLx WE OE Data Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1) When TRLX and CSNT are set in a write-memory access, the strobe lines, WE[0–7] are negated one clock earlier than in the normal case. If ACS ≠ 0, CS is also negated one clock earlier, as shown in Figure 11-48 and Figure 11-49.
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Memory Controller Clock Address PSDVAL CS BCTLx WE OE Data Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) 11.5.1.4 Output Enable (OE) Timing The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS) by programming TRLX = 1.
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Memory Controller 11.5.1.6 Extended Hold Time on Read Accesses Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose some combination of ORx[29–30] (TRLX and EHTR). Any access following a read access to the slower memory bank is delayed by the number of clock cycles specified by Table 11-32. Table 11-32.
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Memory Controller Clock Address PSDVAL CSx CSy BCTLx OE Data Hold Time 1-cycle hold time allowed Figure 11-51. GPCM Read Followed by Read (ORx[29–30] = 01) Clock Address PSDVAL CSx CSy BCTLx OE Data Hold Time Long hold time allowed Figure 11-52. GPCM Read Followed by Write (ORx[29–30] = 01) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Memory Controller Clock Address PSDVAL CSx CSy BCTLx OE Data Hold Time Figure 11-53. GPCM Read Followed by Write (ORx[29–30] = 10) 11.5.2 External Access Termination External access termination is supported by the GPCM using GTA, which is synchronized and sampled internally by the PowerQUICC II. If, during a GPCM data phase (second cycle or later), the sampled signal is asserted, it is converted to PSDVAL, which terminates the current GPCM access. GTA should be asserted for one cycle.
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Memory Controller Clock Address BCTLx CS OE D GTA PSDVAL Figure 11-54. External Termination of GPCM Access 11.5.3 Boot Chip-Select Operation Boot chip-select operation allows address decoding for a boot ROM before system initialization. The CS0 signal is the boot chip-select output; its operation differs from the other external chip-select outputs on system reset.
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Memory Controller Table 11-33. . Boot Bank Field Values after Reset (continued) Register OR0 11.5.4 Setting AM1111_1110_0000_0000_0 (32 MByte) BCTLD0 CSNT1 ACS11 SCY1111 SETA0 TRLX1 EHTR0 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM Users familiar with the MPC8xx GPCM should read this section first: • External termination—In the MPC8xx the external termination connects to the external bus TA and so must be asserted in sync with the system clock.
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Memory Controller value driven on the external memory controller pins for a given clock cycle. Each word in the RAM array provides bits that allow a memory access to be controlled with a resolution of up to one quarter of the external bus clock period on the byte-select and chip-select lines. Figure 11-55 shows the basic operation of each UPM.
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Memory Controller • • • Read burst cycle pattern (RBS) Write single-beat pattern (WSS) Write burst cycle pattern (WBS) These patterns are described in Section 11.6.1.1, “Memory Access Requests.” A UPM refresh timer request pattern initiates a refresh timer pattern (PTS), as described in Section 11.6.1.2, “UPM Refresh Timer Requests.” An exception (caused by a soft reset or the assertion of TEA) occurring while another UPM pattern is running initiates an exception condition pattern (EXS).
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Memory Controller 11.6.1.1 Memory Access Requests When an internal device requests a new access to external memory, the address of transfer is compared to each valid bank defined in BRx. The value in BRx[MS] selects the UPM to handle the memory access. The user must ensure that the UPM is appropriately initialized before a request. The UPM supports two types of memory reads and writes: • A single-beat transfer transfers one operand consisting of up to double word.
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Memory Controller 11.6.1.3 Software Requests—RUN Command Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices have their own signal handshaking protocol to put them into special modes, such as self-refresh mode. Other memory devices require special commands to be issued on their control signals, such as for SDRAM initialization. For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in the UPM RAM.
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Memory Controller NOTE For integer clock ratios, the widths of T1/2/3/4 are equal, for a 1:2.5 clock ratio, T1 = 4/3*T2 and T3 = 4/3*T4, and for a 1:3.5 clock ratio, the ticks widths are T1 = 3/2*T2 and T3 = 3/2*T4. CLKIN T1 T2 T3 T4 Figure 11-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios CLKIN T1 T2 T3 T4 Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.
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Memory Controller Figure 11-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the RAM that specifies on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1, G1T3, G2T1, and G2T3. These bits indicate the electrical value for the corresponding output pins at the appropriate timing. CLKIN T1 T2 T3 T4 CSx CST1 CST2 CST3 CST4 CST1 CST2 CST3 CST4 GPL1 G1T1 G1T3 G1T1 G1T3 GPL2 G2T1 G2T3 G2T1 G2T3 Word 1 Word 2 Figure 11-60.
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Memory Controller 32 Bits RAM Array 64 T1, T2, T3, T4 External Signals Timing Generator (60x or Local) TSIZ, PS, A[30,31] Current Bank CS Line Selector Byte Select Packaging CS[0–11] BS GPL0 GPL1 GPL2 GPL3 GPL4 GPL5 Figure 11-61. RAM Array and Signal Generation 11.6.4.1 RAM Words The RAM word, shown in Figure 11-62, is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies timing for external signals controlled by the UPM.
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Memory Controller Table 11-36 describes RAM word fields. Table 11-36. RAM Word Bit Settings Bit Name Description 0 CST1 Chip-select timing 1. Defines the state of CS during clock phase 1. 0 The value of the CS line at the rising edge of T1 will be 0 1 The value of the CS line at the rising edge of T1 will be 1 See Section 11.6.4.1.1, “Chip-Select Signals (CxTx).” 1 CST2 Chip-select timing 2. Defines the state of CS during clock phase 2.
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Memory Controller Table 11-36. RAM Word Bit Settings (continued) Bit Name 12 G1T1 General-purpose line 1 timing 1. Defines the state of GPL1 during phase 1–2. 0 The value of the GPL1 line at the rising edge of T1 will be 0 1 The value of the GPL1 line at the rising edge of T1 will be 1 See Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx).” 13 G1T3 General-purpose line 1 timing 3. Defines the state of GPL1 during phase 3–4.
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Memory Controller Table 11-36. RAM Word Bit Settings (continued) Bit Name 20 G5T1 General-purpose line 5 timing 1. Defines the state of GPL5 during phase 1–2. 0 The value of the GPL5 line at the rising edge of T1 will be 0 1 The value of the GPL5 line at the rising edge of T1 will be 1 21 G5T3 General-purpose line 5 timing 3. Defines the state of GPL5 during phase 3–4.
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Memory Controller Table 11-36. RAM Word Bit Settings (continued) Bit Name Description 28 NA Next address. Determines when the address is incremented during a burst access. 0 The address increment function is disabled 1 The address is incremented in the next cycle. In conjunction with the BR x[PS], the increment value of A[27–31] and/or BADDR[27–31] at the rising edge of T1 is as follows If the accessed bank has a 64-bit port size, the value is incremented by 8.
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Memory Controller Bank Selected CS0 Switch UPMA/B/C CS1 BRx[MS] CS2 CS3 CS4 SDRAM CS5 MUX CS6 CS7 CS8 CS9 GPCM CS10 CS11 Figure 11-63. CS Signal Selection 11.6.4.1.2 Byte-Select Signals (BxTx) BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle. The selected UPM affects only the assertion and negation of the appropriate BS signal; its timing as specified in the RAM word.
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Memory Controller 11.6.4.1.3 General-Purpose Signals (GxTx, GOx) The general-purpose signals (GPL[1–5]) each have two bits in the RAM word that define the logical value of the signal to be changed at the rising edge of T1 and/or at the rising edge of T3. GPL0 offer enhancements beyond the other GPLx lines. GPL0 can be controlled by an address line specified in MxMR[G0CLx]. To use this feature, set G0H and G0L in the RAM word.
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Memory Controller 11.6.4.2 Address Multiplexing The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex bits can choose between outputting an address requested by the internal master as is and outputting it according to the multiplexing specified by the MxMR[AMx]. The last option is to output the contents of the MAR on the address pins. Note that in 60x-compatible mode, MAR cannot be output on the 60x bus external address line.
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Memory Controller M U L T I P L E X E R To internal data bus UPMx selected to handle the transfer AND (GPL4xDIS = 1) and RD/WR and DLT2x Data Bus CLKIN Figure 11-65. UPM Read Access Data Sampling 11.6.4.4 Signals Negation When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the next cycle all the UPM signals are negated unconditionally (driven to logic ‘1’). This negation will not occur only if there is a back-to-back UPM request pending.
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Memory Controller CLKIN T1 T2 T3 T4 CSx c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 GPL1 A B c12 c13 c14 C D PSDVAL WAEN UPMWAIT Word n Word n+1 Word n+2 Wait Wait Word n+3 Figure 11-66. Wait Mechanism Timing for Internal and External Synchronous Masters 11.6.4.6 Extended Hold Time on Read Accesses Slow memory devices that take a long time to turn off their data bus drivers on read accesses should chose some combination of ORx[EHTR].
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Memory Controller This means that the address bus should be partitioned as shown in Table 11-39. Table 11-39. 60x Address Bus Partition A[0–7] A[8–19] A[20–28] A[29–31] msb of start address Row Column lsb From the device perspective, during RAS assertion, its address port should look like Table 11-40: Table 11-40. DRAM Device Address Port during an ACTIVATE command “A[0–16]” A[17–28] A[29–31] — Row (A[8–19]) n.c. Table 11-38 indicates that to multiplex A[8–19] over A[17–28], choose AMx = 001.
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Memory Controller • • • • • • • • 11.7 to logic 0) at the end of that cycle, unless there is a back-to-back UPM cycle pending. In many cases this allows the UPM routine to finish one cycle earlier because it is now possible and desired to assert both UTA and LAST. MCR is eliminated—In the PowerQUICC II, MCR is eliminated. The function of RAM read/write and RUN is done via the MxMR. UTA polarity is reversed—In the PowerQUICC II, UTA is active-high.
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Memory Controller After timings are created, programming the UPM continues with translating these timings into tables representing the RAM array contents for each possible cycle. When a table is completed, the global parameters of the UPM must be defined for handling the disable timer (precharge) and the refresh timer relative to Figure 11-67. Table 11-42 shows settings of different fields. Table 11-42.
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 RSS 0 0 0 0 0 0 0 0 RSS+1 0 0 0 0 0 1 1 1 RSS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 WSS 0 0 0 0 0 0 0 0 WSS+1 0 0 0 0 0 1 1 1 WSS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 RBS 0 0 0 0 0 0 0 0 RBS+1 0 1 0 0 1 1 0 0 RBS+2 0 0 0 0 0 0 0 0 RBS+3 0 1 0 0 1 1 0 0 RBS+4 0 0 0 0 0 0 0 0 RBS+5 0 1 0 0 1 1 0 0 RBS+6 0 0 0 0 0 0 0 0 R
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 RBS 1 0 0 0 0 0 0 0 RBS+1 1 1 0 0 1 1 1 1 RBS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 WBS 0 0 0 0 0 0 0 0 WBS+1 0 1 0 0 1 1 0 0 WBS+2 0 0 0 0 0 0 0 0 WBS+3 0 1 0 0 1 1 0 0 WBS+4 0 0 0 0 0 0 0 0 WBS+5 0 1 0 0 1 1 0 0 WBS+6 0 0 0 0 0 0 0 0 W
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 PTS 0 0 0 0 0 0 0 0 PTS+1 0 0 0 0 0 0 1 1 PTS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit
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Memory Controller cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 1 1 1 1 1 1 1 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 0 0 0 1 1 EXS Figure 11-74.
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Memory Controller The timing diagram in Figure 11-75 shows how the burst-read access shown in Figure 11-70 can be reduced. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Memory Controller CLKIN A row col 1 col 2 col 3 col 4 D1 D2 D3 D4 RD/WR D PSDVAL CS1 (RAS) BS (CAS) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 -> DLT3 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 RBS 0 0 0 0 1 1 0 0 RBS+1 0 0 0 0 1 1 0 0 RBS+2 0 0 0 0 1 1 0 0 RBS+3 0 0 0 0 0 1 1 1 RBS+4 Bi
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Memory Controller 11.7.0.1 EDO Interface Example Figure 11-76 shows a memory connection to extended data-out type devices. For this connection, GPL1 is connected to the memory device’s OE pins. PowerQUICC II BS[0–7] CS1 R/W RAS RAS CASl/h CASl/h 1M x 16 OE MCM516165 1M x 16 OE MCM516165 W W A[0–9] A[19–28] A[0–9] D[0–15] D[0–15] 16 16 16 16 D[0–63] RAS RAS D[0–15] CASl/h GPL1 OE W D[0–15] CASl/h 1M x 16 MCM516165 OE W A[0–9] 1M x 16 MCM516165 A[0–9] Figure 11-76.
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Memory Controller Table 11-44. EDO Connection Field Value Example (continued) Explanation Field Value Disable timer period MxMR[DSx] 0b10 Burst inhibit device ORx[BI] 0b0 MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Memory Controller CLKIN A Row Column 1 RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 RSS 0 0 0 0 0 0 0 0 RSS+1 0 0 0 0 0 0 0 0 RSS+2 0 0 0 0 0 0 0 0 RSS+3 0 0 0 0 0 1 1 1 RSS+4 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit
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Memory Controller CLKIN A Row Column 1 RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 WSS 0 0 0 0 0 0 0 0 WSS+1 0 0 0 0 0 0 0 0 WSS+2 0 0 0 0 0 1 1 1 WSS+3 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 1
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Memory Controller CLKIN A Row Column 1 RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 WSS 0 0 0 0 0 0 0 0 0 0 WSS+1 1 1 0 0 0 0 0 0 0 0 WSS+2 0 0 0 0 0 0 0 1 1 1 WSS+3 REDO1 REDO2 REDO3 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
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Memory Controller CLKIN A Row Column 1 Column 2 Column 3 Column 4 RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory Controller CLKIN A Row Column 1 Column 2 Column 3 Column 4 RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0
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Memory Controller CLKIN A RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PTS 0 0 0 0 0 0 0 0 PTS+1 0 0 0 0 0 0 0 0 PTS+2 0 0 0 0 0 0 0 0 PTS+3 0 0 0 0 0 0 1 1 PTS+4 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 B
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Memory Controller CLKIN A RD/WR D PSDVAL CS1 (RAS) BS (CAS) GPL1 (OE) cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l0 g0l1 g0h0 g0h1 g1t1 g1t3 g2t1 g2t3 g3t1 g3t3 g4t1 g4t3 g5t1 g5t3 redo[0] redo[1] loop exen amx0 amx1 na uta todt last 1 1 1 1 1 1 1 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 1 1 0 0 0 0 0 0 1 1 EXS Figure 11-83.
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Memory Controller 11.8 Handling Devices with Slow or Variable Access Times The memory controller provides two ways to interface with slave devices that are very slow (access time is greater than the maximum allowed by the user programming model) or cannot guarantee a predefined access time (for example some FIFO, hierarchical bus interface, or dual-port memory devices). These mechanisms are as follows: • The wait mechanism—Used only in accesses controlled by the UPM.
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Memory Controller There are two types of external bus masters: • Any 60x-compatible device with a 64-bit data bus, such as an MPC603e, MPC604e, MPC750, or an MPC2605 (L2 cache) in copy-back mode • PowerQUICC II Both of these external bus master types can access a slave PowerQUICC II’s internal registers and dual-port RAM. They can also use the slave’s memory controller to access memory devices on the 60x bus. An external master has access to the slave’s local bus via the slave’s 60x-to-local bus bridge.
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Memory Controller is sampled in the GPCM or after each READ/WRITE command in the SDRAM machine (the SDRAM machine uses BADDR only for port sizes of 16 or 8 bits). 11.9.5 External Masters Timing External and internal masters have similar memory access timings. However, because it takes more time to decode the addresses of external masters, memory accesses by external masters start one cycle later than those of internal masters.
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Memory Controller CLKIN ADDR + ATTR TS AACK DBG PSDVAL TA D ALE MA CS WE OE BADDR[27–28] 00 01 02 03 Figure 11-84. Pipelined Bus Operation and Memory Access in 60x-Compatible Mode Figure 11-85 shows the 1-cycle delay for external master access. For systems that use the 60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be eliminated by setting BCR[EXDD]. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Memory Controller CLKIN A[0–28] A[27–31] TT TBST TSIZ TS TA CS WE OE Data Address Match and Compare Memory Device Access Figure 11-85. External Master Access (GPCM) 11.9.5.1 Example of External Master Using the SDRAM Machine Figure 11-86 shows an interconnection in which a 60x-compatible external master and the PowerQUICC II can share access to a SDRAM bank. Note that the address multiplexer is controlled by SDAMUX, while the address latch is controlled by ALE.
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Memory Controller BNKSEL,SDWE,SDRAS,SDCAS CS1 SDRAM 64-Bit Port Size DQM[0–7] SDAMUX Multiplexer MA PowerQUICC II ALE Latch External Master A[0–31] D[0–63] TT[0–4] TS TBST TA TSIZ[1–3] TSIZ[0] PSDVAL TSIZ[0–2] (pull down) (pull up) Arbitration signals Figure 11-86. External Master Configuration with SDRAM Device MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 12 Secondary (L2) Cache Support The PowerQUICC II has features to support an externally controlled secondary (L2) cache such as the Freescale MPC2605 integrated secondary cache for microprocessors that implement the PowerPC architecture. This chapter describes the PowerQUICC II’s L2 cache interface—configurations, operation, programmable parameters, system requirements, and timing. 12.
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Secondary (L2) Cache Support (pull up) PowerQUICC II MPC2605 BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0–4], TBST, TSIZ[1–3] TS, TT[0–4], TBST, TSIZ[0–2]] CI, WT, GBL, TA, DBB, TEA CI, WT, GBL, TA, DBB, TEA AACK, ARTRY TSIZ[0] AACK, ARTRY (pull down) L2_HIT L2_CLAIM A[0–31] A[0–31] D[0–63] D[0–63] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 12-1. L2 Cache in Copy-Back Mode 12.1.
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Secondary (L2) Cache Support mode sacrifices some of the write performance of copy-back mode, but guarantees L2 cache coherency with main memory. Since write-through mode keeps memory coherent with the contents of the L2 cache, there is never any need to perform an L2 copy-back. This removes the need for the L2 cache to maintain a dirty bit in the tag RAM (all cache blocks are unmodified) and it also removes the need for bus arbitration signals.
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Secondary (L2) Cache Support PowerQUICC II MPC2605 (pull up) (pull up) BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0:4], TBST, TSIZ[1–3] TS, TT[0–4], TBST, TSIZ[0–2] CI, GBL, TA, DBB, TEA CI, GBL, TA, DBB, TEA AACK, ARTRY TSIZ[0] AACK, ARTRY (pull down) (pull down) WT L2_HIT L2_CLAIM A[0–31] A[0–31] D[0–63] D[0–63] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 12-2. External L2 Cache in Write-Through Mode 12.1.
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Secondary (L2) Cache Support In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the following restrictions: • All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed must use either ECC (BRx[DECC] = 0b11) or read-modify-write parity (BRx[DECC] = 0b10). See Section 11.3.1, “Base Registers (BRx),” for more information about the PowerQUICC II base register parameters. • Only PowerQUICC II-type masters are supported in systems that use ECC/parity L2 cache mode.
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Secondary (L2) Cache Support MPC2605 PowerQUICC II (pull up) (pull up) BR L2BR BG L2BG DBG L2DBG CPU_BR, CPU_BG, CPU_DBG CPU_BR,CPU_BG,CPU_DBG TS, TT[0–4], TBST TS, TT[0–4], TBST (pull downs) CI, GBL, TA, DBB, TEA TSIZ[0–2] CI, GBL, TA, DBB, TEA AACK, ARTRY AACK, ARTRY TSIZE[0] WT (pull down) (pull down) L2_HIT L2_CLAIM (pull downs) A[0–31] A[29–31] A[0–28] D[0–63], DP[0–7] D[0–63],DP[0–7] Latch Memory Controller MUX SDRAM Main Memory I/O Devices Figure 12-3.
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Secondary (L2) Cache Support • • BCR[L2D] = 0—L2 response time. In this case, the L2 will claim a bus transaction one clock cycle after TS assertion. BCR[APD] = 1: This parameter is not L2 specific, but should consider the L2 ARTRY assertion timing. See Section 4.3.2.1, “Bus Configuration Register (BCR),” for more details about these parameters. 12.
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Secondary (L2) Cache Support CLK BR BG ABB Addr A1 & TBST A0 & TBST& CI TS Memc controls disabled active L2 AACK PowerQUICC II DBG DBB DATA D00 D01 D02 D03 TA L2D = 0 0 0 L2 HIT Figure 12-4. Read Access with L2 Cache MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 13 IEEE 1149.1 Test Access Port The PowerQUICC II provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).
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IEEE 1149.1 Test Access Port Boundary Scan Register M U X TDI Bypass Instruction Apply & Decode Register 8 0 8–Bit Instruction Register M U X TDO TRST TMS TAP Controller TCK Figure 13-1. Test Logic Block Diagram The TAP consists of the signals in Table 13-1. . Table 13-1. TAP Signals Signal Description TCK A test clock input to synchronize the test logic.
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IEEE 1149.1 Test Access Port Test Logic Reset 1 0 Run—Test/Idle 1 Select—DR_SCAN 0 1 Select—IR_SCAN 0 0 Capture—DR Capture—IR 0 0 Shift—DR Shift—IR 1 1 Exit1—DR Exit1—IR 0 0 Pause—DR Pause—IR 1 1 Exit2—DR Exit2—IR 1 1 Update—DR 1 0 1 Update—IR 1 0 Figure 13-2. TAP Controller State Machine 13.
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IEEE 1149.1 Test Access Port Shift DR 1 — EXTEST | Clamp 0 — Otherwise To Next Cell G1 Data from System Logic 1 To Output Buffer MUX 1 G1 1 D MUX From Last Cell D C C 1 Clock DR Update DR Figure 13-3. Output Pin Cell (O.Pin) To Next Cell Data to System Logic Input Pin G1 D C 1 MUX 1 Clock DR Shift DR From Last Cell Figure 13-4. Observe-Only Input Pin Cell (I.Obs) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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IEEE 1149.1 Test Access Port Shift DR 1 — EXTEST | Clamp 0 — Otherwise To Next Cell G1 Output Control from System Logic 1 To Output Buffer MUX 1 G1 1 D MUX 1 From Last Cell D C C Clock DR Update DR Figure 13-5. Output Control Cell (IO.CTL) From Last Cell Output Enable from System Logic I/O.CTL Output Data O.PIN Input Data I.OBS EN I/O Pin To Next Pin Pair To Next Cell Figure 13-6.
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IEEE 1149.1 Test Access Port from the shift register to the parallel outputs during the update-IR controller state. The four bits are used to decode the five unique instructions listed in Table 13-2. Table 13-2. Instruction Decoding Code1 Instruction Description B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 EXTEST External test. Selects the 475-bit boundary scan register.
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IEEE 1149.1 Test Access Port Table 13-2. Instruction Decoding (continued) Code1 Instruction Description B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 1 1 0 0 0 0 HI–Z Provided as a manufacturer’s optional public instruction to avoid back driving the output pins during circuit-board testing. When HI-Z is invoked all output drivers, including the two-state drivers, are turned off (high impedance). The instruction selects the bypass register.
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IEEE 1149.1 Test Access Port MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Part IV Communications Processor Module Intended Audience Part IV is intended for system designers who need to implement various communications protocols on the PowerQUICC II. It assumes a basic understanding of the PowerPC exception model, the PowerQUICC II interrupt structure, as well as a working knowledge of the communications protocols to be used. A complete discussion of these protocols is beyond the scope of this book.
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• • • • • • • • • • • • • • • • • Chapter 23, “SCC BISYNC Mode,” describes the PowerQUICC II implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. Chapter 24, “SCC Transparent Mode,” describes the PowerQUICC II implementation of transparent mode (also called totally transparent mode), which provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation.
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• Chapter 40, “Parallel I/O Ports,” describes the four general-purpose I/O ports A–D. Each signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated to supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture.
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x n ¬ & | In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Table IV-1. Acronyms and Abbreviated Terms Term Meaning AAL ATM adaptation layer ABR Availabe bit rate ACR Allowed cell rate ALU Arithmetic logic unit APC ATM pace control ATM Asynchronous transfer mode BD Buffer descriptor BIST Built-in self test BT Burst tolerance CBR Constant bit rate CEPT Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations).
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Table IV-1.
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Table IV-1.
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MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 14 Communications Processor Module Overview The PowerQUICC II’s communications processor module (CPM) is a superset of the MPC860 PowerQUICC CPM, with enhancements in performance. The support for multiple HDLC channels is enhanced to support up to 256 HDLC channels. 14.1 Features The CPM includes various blocks to provide the system with an efficient way to handle data communication tasks. The following is a list of the CPM’s important features.
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Communications Processor Module Overview • • • • • • • • — Synchronous UART (1x clock mode) — Binary synchronous communication (BISYNC) — Totally transparent operation Two full-duplex serial management controllers (SMCs) support the following protocols: — GCI (ISDN interface) monitor and C/I channels — UART — Transparent operation Serial peripheral interface (SPI) support for master or slave I2C bus controller Time-slot assigner supports multiplexing of data from any of the SCCs, FCCs, SMCs, and MCCs on
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Communications Processor Module Overview Figure 14-1 shows the PowerQUICC II’s CPM block diagram. Local Bus 60x Bus To SIU Interrupt Controller Bus Interface SDMA Internal Bus 4 Timers Communications Processor Dual-Port RAM Parallel I/O Ports ROM Baud Rate Generators Peripheral Bus 2 MCCs1 3 FCCs2 4 SCCs 2 SMCs SPI I 2C Serial Interface (SI), TC layer3, and Time-Slot Assigner (TSA) Note 1 One MCC on the MPC8250 and MPC8255 2 Two FCCs on the MPC8255 3 MPC8264 and MPC8266 only Figure 14-1.
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Communications Processor Module Overview Table 14-1. Possible PowerQUICC II Applications Application ISDN router MCC11 MCC2 4 E1 FCC2 FCC3 2 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 UART UART FEnet or ATM FEnet UART ATM switch ATM FEnet UART ATM access ATM FEnet E3 or E1’s GSM mobile switching center 1 2 E1’s 4 E1 FCC1 FEnet E3 or ATM E1’s FEnet or ATM Backbone UART UART 10 M 10 M HDLC HDLC Not on the MPC8250 and the MPC8255. Not on the MPC8255. 14.
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Communications Processor Module Overview • • • 64-bit dual-port RAM access Optimized for communications processing Performs DMA bursting of serial data from/to dual-port RAM to/from external memory. Note that IDMA cannot burst to dual-port RAM. 14.3.
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Communications Processor Module Overview Communications Processor (CP) Timer Data Peripheral Bus Special Registers Source Buses Destination Bus Block Transfer Module (BTM) Data Address Data Decoder Address Instruction Sequencer Address Load/Store Unit Instruction Data Scheduler Microcode ROM GeneralPurpose Registers Execution Unit To all units Address Data Dual-Port RAM Address DMA Address Data Data Bus Interface 60x Bus Local Bus Figure 14-2.
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Communications Processor Module Overview • • • • Many parameters are exchanged through the dual-port RAM. The CP can execute special commands issued by the core. These commands should only be issued in special situations like exceptions or error recovery. The CP generates interrupts through the SIU interrupt controller. The G2 core can read the CPM status/event registers at any time. 14.3.5 Peripheral Interface The CP uses the peripheral bus to communicate with all of its peripherals.
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Communications Processor Module Overview Table 14-2.
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Communications Processor Module Overview 0 1 2 Field TIME MCCPR 7 1 TIMEP Reset 8 9 10 11 DR1M DR2M DR1QP 12 EIE 13 SCD 14 2 15 DR2QP 0000_0000_0000_0000 R/W R/W Addr 0x0x119C4 16 19 Field ERAM 3 20 21 22 23 24 25 26 27 28 29 30 31 EDM1 EDM2 EDM3 EDM4 DR3M DR4M DR3QP DEM12 DEM34 DR4QP Reset 0000_0000_0000_0000 R/W R/W Addr 0X119C6 1 Reserved on .29µm (HiP3) Rev A.1 and B.3 devices. See Table 14-3. Reserved on .29µm devices. See Table 14-3.
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Communications Processor Module Overview Table 14-3. RISC Controller Configuration Register Field Descriptions (continued) Bits Name Description 12 EIE External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP. Configure as instructed in the download process of a Freescale-supplied RAM microcode package. 0 DREQ1 cannot interrupt the CP. 1 DREQ1 will interrupt the CP. 13 — .29µm (HiP3) devices: Reserved SCD .25µm (HiP4) devices: Scheduler configuration.
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Communications Processor Module Overview Table 14-3. RISC Controller Configuration Register Field Descriptions (continued) Bits Name 28 DEM12 Edge detect mode for DONE[1, 2] for IDMA[1, 2]. See Section 19.7.2, “DONEx.” DONE[1, 2] asserts as follows: 0 High-to-low change 1 Low-to-high change 29 DEM34 Edge detect mode for DONE[3, 4] for IDMA[3, 4]. See Section 19.7.2, “DONEx.” DONE[3, 4] asserts as follows: 0 High-to-low change 1 Low-to-high change 14.3.
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Communications Processor Module Overview 0 15 Field Time Stamp Reset — R/W R Addr 0x0x119E0 16 31 Field Time Stamp Reset — R/W R Addr 0X119E2 Figure 14-5. RISC Time-Stamp Register (RTSR) After reset, setting RTSCR[RTE] causes the time stamp to start counting microseconds from zero. 14.3.10 RISC Microcode Revision Number Associated with each version of CPM microcode, is a number (REV_NUM) that uniquely identifies that specific microcode.
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Communications Processor Module Overview 14.4.1 CP Command Register (CPCR) The core should set CPCR[FLG], shown in Figure 14-6, when it issues a command and the CP clears FLG after completing the command, thus indicating to the core that it is ready for the next command. Subsequent commands to the CPCR can be given only after FLG is clear. However, the software reset command issued by setting RST does not depend on the state of FLG, but the core should still set FLG when setting RST.
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Communications Processor Module Overview Table 14-6. CP Command Register Field Descriptions (continued) Bit Name Description 6–10 SBC Sub-block code. Set by the core to specify the sub-block on which the command is to operate. Set according to OPCODE[28-31]. Refer to Table 13-7.
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Communications Processor Module Overview Table 14-7.
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Communications Processor Module Overview 2 See FCC1 and FCC2 in SBC[6-10] in Table 13-6. Not available on the MPC8250. NOTE If a reserved command is issued, the CPM enters an unknown state that requires an external reset to recover. The commands in Table 14-7 are described in Table 14-8. Table 14-8. Command Descriptions Command INIT TX AND RX PARAMS INIT MCC RX AND TX PARAMS — ONE CHANNEL1 Description Initialize transmit and receive parameters.
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Communications Processor Module Overview Table 14-8. Command Descriptions (continued) Command Description ADDRESS Set group address. Sets a bit in the hash table for the Ethernet logical group address recognition function. GCI ABORT GCI abort request. The GCI receiver sends an abort request on the E-bit. SET GROUP REQUEST GCI TIMEOUT GCI time-out. The GCI performs the timeout function. RESET BCS Reset block check sequence. Used in BISYNC mode to reset the block check sequence calculation.
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Communications Processor Module Overview Slave Address CP Instruction Address Slave Data Dual-Port RAM CP Data Address DMA (60x) Address DMA (Local) Address CP Instruction CP Data 24 KBytes (HiP3) 32 KBytes (HiP4) (BDs, Buffers and Microcode) BTM Address DMA (60x) Data DMA (Local) Data BTM Data Figure 14-7.
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Communications Processor Module Overview 0x0000 0x4000 Bank #1 Bank #13 BD/Data/µCode Microcode 2 KBytes 2 KBytes1 0x0800 0x4800 Bank #2 Bank #14 BD/Data/µCode Microcode 2 KBytes 2 KBytes1 0x1000 0x5000 Bank #3 Bank #15 0x8000 Parameter RAM 2 KBytes 0x8800 0x9000 Bank #10 Parameter RAM 2 KBytes (Partially Reserved) Bank #11 BD/Data/µCode Microcode BD/Data/µCode 2 KBytes 2 KBytes1 2 KBytes 0x1800 0x5800 Bank #16 Bank #1 BD/Data/µCode Bank #4 Microcode BD/Data/µCode 2 KB
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Communications Processor Module Overview unused parameter RAM, such as, in the area made available when a peripheral controller or sub-block is not being used. Microcode can be executed from the first 12 Kbytes. To ensure an uninterrupted instruction stream (one per cycle), no other agent is allowed to use a RAM bank used by the microcode. Since the first 12 Kbytes are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4, 6, 8, 10, or 12 Kbytes of RAM, depending on RCCR[ERAM]; see Section 14.3.
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Communications Processor Module Overview Table 14-10.
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Communications Processor Module Overview 14.6 RISC Timer Tables The CP can control up to 16 software timers that are separate from the four general-purpose timers and the BRGs in the CPM. These timers are best used in protocols that do not require extreme precision, but in which it is preferable to free the core from scanning the software’s timer tables. These timers are clocked from an internal timer that only the CP uses. The following is a list of the RISC timer tables important features.
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Communications Processor Module Overview 16 RISC Timer Table Entries (Up to 64 Bytes) Timer Table Base Pointer 0x8AE0 TM_BASE RISC Timer Table Parameter RAM Figure 14-9. RISC Timer Table RAM Usage The RISC timer table parameter RAM area begins at the RISC timer base address and is used for the general timer parameters; see Table 14-11. Table 14-11. RISC Timer Table Parameter RAM Offset1 0x00 1 Name Description TM_BASE RISC timer table base address.
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Communications Processor Module Overview 14.6.2 RISC Timer Command Register (TM_CMD) Figure 14-10 shows the RISC timer command register (TM_CMD). Field 0 1 V R 2 11 — 12 15 TN 16 31 Field TIMER PERIOD (TP) Figure 14-10. RISC Timer Command Register (TM_CMD) TM_CMD fields are described in Table 14-12. Table 14-12. TM_CMD Field Descriptions Bits Name 0 V Valid. This bit should be set to enable the timer and cleared to disable it. 1 R Restart.
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Communications Processor Module Overview 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x119D6 (RTER)/0x0x119DA (RTMR) Figure 14-11. RISC Timer Event Register (RTER)/Mask Register (RTMR) 14.6.5 SET TIMER Command The SET TIMER command is used to enable, disable, and configure the 16 timers in the RISC timer table and is issued to the CPCR.
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Communications Processor Module Overview 14.6.7 RISC Timer Initialization Example The following sequence initializes RISC timer 0 to generate an interrupt approximately every second using a 133-MHz general system clock: 1. Write 111111 to RCCR[TIMEP] to generate the slowest clock. This value generates a tick every 65,536 clocks, which is every 485 µs at 133 MHz. 2. Configure the TM_BASE in the RISC timer table parameter RAM to point to a location in the dual-port RAM with 4 bytes available.
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Communications Processor Module Overview If a SET TIMER command is issued, the CP makes the appropriate modifications to the timer table and parameter RAM, but does not scan the timer table until the next tick of the internal timer. It is important to use the SET TIMER command to properly synchronize timer table modifications to the execution of the CP. 14.6.10 Using the RISC Timers to Track CP Loading The RISC timers can be used to track CP loading.
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Communications Processor Module Overview MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 15 Serial Interface with Time-Slot Assigner Figure 15-1 shows a block diagram of the time-slot assigner (TSA). Two SI blocks in the PowerQUICC II (SI1 and SI2), can be programmed to handle eight TDM lines concurrently with the same flexibility described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Serial Interface with Time-Slot Assigner Tx/Rx RAM Control Route SI RAM Mode Register Command Register Status Register Shadow Address Register Peripheral Bus Channel # Multi-Channel Controllers (MCCs) CPM Mux Clock Route RAM To: SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3 Tx Rx TX Rx R clocks T clocks MUX MUX MUX MUX MUX MUX MUX MUX MUX Time-Slot R clocks T clocks R sync T sync Assigner (TSA) SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 MII1/ MII2/ MII3 UTOPIA UTOPIA 81 161 Nonmultiplexe
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Serial Interface with Time-Slot Assigner 15.1 Features Each SI has the following features: • Can connect to four independent TDM channels.
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Serial Interface with Time-Slot Assigner • • • 15.2 Independent mapping for receive/transmit Individual channel echo or loop mode Global echo or loop mode through the SI Overview The TSA implements both internal route selection and time-division multiplexing (TDM) for multiplexed serial channels. The TSA supports the serial bus rate and format for most standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM) highway, and the ISDN buses in both basic and primary rates.
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Serial Interface with Time-Slot Assigner 1 TDM Sync 1 TDM Clock TSA SCC2 TDM SMC1 TDM Tx Slot 3 Slot N TDM Rx Slot 3 Slot N SCC2 More complex TDM example—unique routing 1 TDM Sync PowerQUICC II SMC1 1 TDM Clock TSA SCC2 TDM TDM Tx Slot SMC1 1 Slot Slot TDM Rx PowerQUICC II 2 3 SCC2 Even more complex TDM example—multiple time slot per channel with varying sizes of time slots Slot N SMC1 1 TDM Sync 1 TDM Clock TSA SCC2 TDM SMC1 SCC2 TDM Tx TDM Rx SCC2 SMC1 SCC2 NOTE: The t
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Serial Interface with Time-Slot Assigner At its most flexible, the TSA can provide four separate TDM channels, each with independent receive and transmit routing assignments and independent sync pulse and clock inputs. Thus, the TSA can support eight, independent, half-duplex TDM sources, four in reception and four in transmission, using eight sync inputs and eight clock inputs. Figure 15-3 shows a dual-channel example.
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Serial Interface with Time-Slot Assigner to program the receive routing. SIx RAMs can be used to define the number of bits/bytes to be routed to the MCC, FCC, SCC, or SMC and determine when external strobes are to be asserted and negated. The size of the SIx RAM available for time-slot programming depends on the user’s configuration. The user defines how many of the 256 entries are related to each TDM. The resolution of the division is by fractions of 32.
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Serial Interface with Time-Slot Assigner MCCx TDM a channels TDM b channels TDM c channels TDM d channels TDM a,b,c,d Enable = 1 FCC1 FCC2 FCC3 SCC1 SCC2 Time-Slot Assigner TDM a Pins En TDM b Pins En TDM c Pins En TDM d Pins FC1 = 0 MII1/UTOPIA 16 FC2 = 00 MII2/UTOPIA 8 FC3 = 0 MII3 SC1 = 0 SCC1 pins SC2 = 0 SCC2 pins SC3 = 0 SCC3 SC4 = 0 SCC4 SMC1 SMC2 SCC3 pins NMSI Mode SIx RAM En SCC4 pins SMC1 = 0 SMC1 pins SMC2 = 0 SMC2 pins In the CPM mux Figure 15-4.
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Serial Interface with Time-Slot Assigner 15.4.1 One Multiplexed Channel with Static Frames The example in Figure 15-5. shows one of many possible settings. With this configuration, the SIx RAM has 256 entries for transmit data and strobe routing and 256 entries for receive data and strobe routing. This configuration should be chosen only when one TDM is required and the routing on that TDM does not need to be dynamically changed. The number of entries available in the SIx RAM is determined by the user.
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Serial Interface with Time-Slot Assigner Framing Signals 256 SIx RAM Address: 0 (each entry is 16 Bits Wide) L1TCLKax L1TSYNCax 128 Entries TXa Route 255 511 1024 1280 L1RCLKax L1RSYNCax 128 Entries RXa Route 1279 1535 Figure 15-6. One TDM Channel with Shadow RAM for Dynamic Route Change This configuration should be chosen when only one TDM is needed, but dynamic rerouting may be needed on that TDM.
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Serial Interface with Time-Slot Assigner Table 15-1. SIx RAM Entry (MCC = 0) Bits Name 0 MCC Description The entry controls the functionality of the other bits in the SIx RAM entry. 0 The entry refers to other serial controllers (FCCs, SCCs, SMC, according to the CSEL field). 1 The entry refers to the MCC. 1 SWTR Switch Tx and Rx. Valid only in the receive route RAM and ignored in the transmit route RAM. SWTR affects the operation of both L1RXD and L1TXD.
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Serial Interface with Time-Slot Assigner Table 15-1. SIx RAM Entry (MCC = 0) (continued) Bits Name Description 14 BYT Byte resolution 0 Bit resolution. The CNT value indicates the number of bits in this group. 1 Byte resolution. The CNT value indicates the number of bytes in this group. 15 LST Last entry in the RAM. Whenever SIx RAM is used, LST must be set in one of the Tx or Rx entries of each group. Even if all entries of a group are used, this bit must still be set in the last entry.
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Serial Interface with Time-Slot Assigner Table 15-2. SIx RAM Entry (MCC = 1) Bits Name 0 MCC Description If MCC =1, the other SIx RAM entries in this table are valid: 1 LOOP/ Channel loopback or echo. ECHO 0 Normal mode of operation. 1 Operation depends on the following configurations: In the receive SIx RAM, this bit selects loopback mode for this MCC channel. The channel’s transmit data is sent to both the receiver’s input and to the data output line.
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Serial Interface with Time-Slot Assigner SIx RAM Programming Example 15.4.4 This example shows how to program the RAM to support the 10-bit IDL bus. Figure 15-23. shows the 10-bit IDL bus format. In this example, the TSA supports the B1 channel with SCC2, the D channel with SCC1, the first 4 bits of the B2 channel with an external device (using a strobe to enable the external device), and the last 4 bits of B2 with SMC1. Additionally, the TSA marks the D channel with another strobe signal.
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Serial Interface with Time-Slot Assigner • • Static routing. The number of SIx RAM entries is determined by the banks the user relates to the corresponding TDM and is divided into two parts (Rx and Tx). The following sequence must be followed to program the routing entries. — All serial devices connected to the TDM must be disabled. — SI routing can be modified. — All appropriate serial devices connected to the TDM must be reenabled. Dynamic routing.
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Serial Interface with Time-Slot Assigner 1) RAM Address: Initial State 0 1024 2) RAM Address: Programming 0 RAM Address: 127 128 1024 RAM Address: RAM Address: 1024 Framing Signals: 1407 1408 1535 64 RXb Shadow L1RCLKb L1RSYNCb 255 256 64 TXa Route 1151 1152 64 RXa Shadow 511 64 TXb Shadow 64 RXb Route 383 384 64 TXb Shadow 1279 1280 64 RXa Route 511 64 TXb Route L1TCLKb L1TSYNCb L1TCLKa L1TSYNCa Framing Signals: CSRRa=0 CSRTa=0 CSRRb=0 CSRTb=0 1279 1280 64 RXa Shadow 1
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Serial Interface with Time-Slot Assigner 15.5 Serial Interface Registers The serial interface registers are described in the following sections. The MCC configuration registers, which define the TDM mapping of the MCC channels, are described in Section 28.6, “MCC Configuration Registers (MCCFx).” NOTE The programming of SI registers and SIx RAM must be coherent with the MCCF programming. 15.5.1 SI Global Mode Registers (SIxGMR) The SI global mode registers (SIxGMR), shown in Figure 15-10.
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Serial Interface with Time-Slot Assigner 0 Field — 1 3 4 SADx 5 SDMx Reset 6 7 RFSDx 8 9 10 DSCx CRTx SLx 11 12 13 CEx FEx GMx 14 15 TFSDx 0000_0000_0000_0000 R/W R/W Addr 0x0x11B20 (SI1AMR), 0x0x11B22 (SI1BMR), 0x0x11B24 (SI1CMR), 0x0x11B26 (SI1DMR)/ 0x0x11B40 (SI2AMR), 0x0x11B42 (SI2BMR), 0x0x11B44 (SI2CMR), 0x0x11B46 (SI2DMR) Figure 15-11. SI Mode Registers (SIxMR) Table 15-5 describes SIxMR fields. Table 15-5.
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Serial Interface with Time-Slot Assigner Table 15-5. SIxMR Field Descriptions (continued) Bits Name Description 6–7 RFSDx Receive frame sync delay for TDM a, b, c, or d. Determines the number of clock delays between the receive sync and the first bit of the receive frame. Even if CRTx is set, these bits do not control the delay for the transmit frame. 00 No bit delay. The first bit of the frame is transmitted/received on the same clock as the sync; use for GCI.
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Serial Interface with Time-Slot Assigner Table 15-5. SIxMR Field Descriptions (continued) Bits Name Description 13 GMx Grant mode for TDM a, b, c, or d 0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is internally supported. The grant is one bit from the receive channel. This bit is marked by programming the channel select bits of the SIx RAM with 0111 to assert an internal strobe on it. See Section 15.7.2.2, “SCIT Programming.” 1 IDL mode.
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Serial Interface with Time-Slot Assigner CE=1 xFSD=01 L1CLK L1SYNC (FE=0) L1SYNC (FE=1) L1TxD (Bit-0) L1ST (On Bit-0) L1ST Driven from Clock High for Both FE Settings Rx Sampled Here Figure 15-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01 Figure 15-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.
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Serial Interface with Time-Slot Assigner CE=1 xFSD=00 L1CLK (FE=0) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) The L1ST is Driven from Sync. Data is Driven from Clock Low. Rx Sampled Here (FE=0) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) L1ST is Driven from Clock High. L1SYNC (FE=1) L1TXD (Bit-0) L1ST (On Bit-0) Both Data Bit-0 and L1ST are Driven from Sync. Rx Sampled Here (FE=1) L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) L1ST and Data Bit-0 is Driven from Clock Low. Figure 15-16.
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Serial Interface with Time-Slot Assigner CE=0 xFSD=00 L1CLK (FE=1) L1SYNC L1TXD (Bit-0) The L1ST is Driven from Sync. Data is Driven From Clock High. L1ST (On Bit-0) Rx Sampled Here (FE=1) L1SYNC L1TXD (Bit-0) L1ST is Driven from Clock Low. L1ST (On Bit-0) L1SYNC (FE=0) L1TXD (Bit-0) Both the Data and L1ST from Sync when Asserted during Clock High. L1ST (On Bit-0) (FE=0) L1SYNC L1TXD (Bit-0) Both the Data and L1ST from the Clock when Asserted during Clock Low. L1ST (On Bit-0) Figure 15-17.
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Serial Interface with Time-Slot Assigner 0 Field 1 — 3 SSADA 4 5 — 7 8 SSADB Reset 9 — 11 SSADC 12 13 — 15 SSADD 0000_0000_0000_0000 R/W R/W Addr 0x0x11B2E (SI1RSR), 0x0x11B4E (SI2RSR) Figure 15-18. SIx RAM Shadow Address Registers (SIxRSR) Table 15-6. describes SIxRSR fields. Table 15-6. SIxRSR Field Descriptions Bits Name 0, 4, 8, 12 — 1–3, 5–7, 9–11, 13–15 15.5.4 Description Reserved. Should be cleared.
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Serial Interface with Time-Slot Assigner Table 15-7. SIxCMDR Field Description Bits Name Description 0, 2, 4, CSRRx Change shadow RAM for TDM a, b, c, or d receiver. Set CSRRx causes the SI receiver to replace 6 the current route RAM with the shadow RAM. Set by the user and cleared by the SI. 0 The receiver shadow RAM is not valid. The user can write into the shadow RAM to program a new routing. 1 The receiver shadow RAM is valid.
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Serial Interface with Time-Slot Assigner (physical layer device) and has separate receive and transmit sections. Although the PowerQUICC II has eight TDMs, it can support only four independent IDL buses (limited by the number of serials that support IDL) using separate clocks and sync pulses. Figure 15-21 shows an application with two IDL buses. ISDN TE NT IDL1 S/T PowerQUICC II S/T U S/T U Interfaces Interfaces IDL2 S/T S/T U Figure 15-21. Dual IDL Bus Application Example 15.6.
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Serial Interface with Time-Slot Assigner System Bus (ROM and RAM) PCM CODEC/Filter Monocircuit B1 POTS ASYNC SMC1 SPI PowerQUICC II SMC2 SCC2 SCC3 SCC1 TSA IDL (Data) B2+D ICL (Control) S/T Transceiver Ethernet 4 wire B1+B2+D Ethernet PHY LAN Figure 15-22. IDL Terminal Adaptor The PowerQUICC II can identify and support each IDL channel or can output strobe lines for interfacing devices that do not support the IDL bus.
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Serial Interface with Time-Slot Assigner The basic rate IDL bus has the three following channels: • B1 is a 64-Kbps bearer channel • B2 is a 64-Kbps bearer channel • D is a 16-Kbps signaling channel There are two definitions of the IDL bus frame structure—8 and 10 bits. The only difference between them is the channel order within the frame. See Figure 15-23. L1CLK L1SYNC 10-Bit IDL L1RXD B1 D1 B2 D2 L1TXD B1 D1 B2 D2 8-Bit IDL L1RXD B1 B2 D1 D2 L1TXD B1 B2 D1 D2 Notes: 1.
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Serial Interface with Time-Slot Assigner device negates L1GRx. The PowerQUICC II then stops sending and retransmits the frame when L1GRx is reasserted. This procedure is handled automatically for the first two buffers of a frame. For the primary rate IDL, the PowerQUICC II supports up to four 8-bit channels in the frame, determined by the SIx RAM programming.
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Serial Interface with Time-Slot Assigner Table 15-10. SIx RAM Entries for an IDL Interface (continued) Entry Number SIx RAM Entry MCC SWTR SSEL CSEL CNT BYT LST Description 4 0 0 0000 0101 011 0 0 4-bit SMC1 5 0 0 1000 0001 000 0 1 1-bit SCC1 strobe1 2. CMXSI1CR = 0x00. TDMA receive clock is CLK1. 3. CMXSMR = 0x80. SMC1 is connected to the TSA. 4. CMXSCR = 0xC040_0000. SCC1 and SCC2 are connected to the TSA. SCC1 supports the grant mechanism because it handles the D channel. 5.
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Serial Interface with Time-Slot Assigner The GCI bus consists of four lines—two data lines, a clock, and a frame synchronization line. Usually, an 8-kHz frame structure defines the various channels within the 256-kbps data rate. The PowerQUICC II supports two (limited by the number of SMCs) independent GCI buses, each with independent receive and transmit sections. The interface can also be used in a multiplexed frame structure on which up to eight physical layer devices multiplex their GCI channels.
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Serial Interface with Time-Slot Assigner • • • M is a 64-Kbps monitor channel D is a 16-Kbps signaling channel C/I is a 48-Kbps C/I channel (includes A and E bits) The M channel is used to transfer data between layer 1 devices and the control unit (the CPU); the C/I channel is used to control activation/deactivation procedures or to switch test loops by the control unit. The M and C/I channels of the GCI bus should be routed to SMC1 or SMC2, which have modes to support the channel protocols.
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Serial Interface with Time-Slot Assigner signals to the SIx RAM transmit section, using the CRTx bits. The user should then define the GCI frame routing and strobe select using the SIx RAM. When the receive and transmit section uses the same clock and sync signals, these sections should be programmed to the same configuration. Also, the L1TXDx pin in the I/O register should be programmed to be an open-drain output.
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Serial Interface with Time-Slot Assigner NOTE If SCIT mode is not used, delete the last three entries of the SIx RAM, divide one entry into two and set the LST bit in the new last entry. 3. CMXSMR = 0x88. SMC1 and SMC2 are connected to the TSA. 4. CMXSCR = 0xC040_0000. SCC2 and SCC1 are connected to the TSA. SCC1 supports the grant mechanism since it is on the D channel. 5. CMXSI1CR = 0x00. TDMa uses CLK1. 6. Set PPARA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa and L1RSYNCa. 7. Set PSORA[6–9].
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Chapter 16 CPM Multiplexing The CPM multiplexing logic (CMX) connects the physical layer—UTOPIA, MII, modem lines, TDM lines and proprietary serial lines to the FCCs, SCCs and SMCs. The CMX features the following two modes: • In NMSI mode, the CMX allows all serial devices to be connected to their own set of individual pins. Each serial device that connects to the external world in this way is said to connect to a nonmultiplexed serial interface (NMSI).
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CPM Multiplexing Register Bus CPM MUX SIx Clock Registers (CMXSIxCR) BRGs UTOPIA Address 2 Register (CMXUAR) SMC Clock Register (CMXSMR) SCC Clock Register (CMXSCR) FCC Clock Register (CMXFCR) To Serials: SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3 MCCs MUX MUX MUX MUX MUX MUX MUX MUX MUX SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 Rx Tx R clocks T clocks MUX Time-Slot Assigner SIx TDM Ax, Bx, Cx, Dx Strobes Rx Tx R sync T sync TC Layer1 (Option for FCC2 Only) Clocks TDM A x, Bx, C x, Dx
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CPM Multiplexing • • • Each SCC can have its own set of modem control pins. Each SMC can have its own set of four pins. Each FCC, SCC, and SMC can be driven from a bank of twenty clock pins or a bank of eight BRGs. The multiple-PHY addressing selection supports the following options for FCC1 and FCC2: • In master mode: — FCC1 connect up to 31 PHYs and FCC2 connect up to 7 PHYs. — FCC1 connect up to 15 PHYs and FCC2 connect up to 15 PHYs. — FCC1 connect up to 7 PHYs and FCC2 connect up to 31 PHYs.
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CPM Multiplexing MCCs TDM a channels TDM b channels TDM c channels TDM d channels TDM a,b,c,d Enable = 1 FCC1 FCC2 FCC3 SCC1 SCC2 Time-Slot Assigners TDM a Pins En TDM b Pins En TDM c Pins En TDM d Pins FC1 = 0 MII1/UTOPIA 8/16/M-phy FC2 = 00 MII2/UTOPIA 8/M-phy FC3 = 0 MII3 SC1 = 0 SCC1 Pins SC2 = 0 SCC2 Pins SC3 = 0 SCC3 SC4 = 0 SCC4 SMC1 SMC2 SCC3 Pins SCC4 Pins SMC1 = 0 SMC1 Pins SMC2 = 0 SMC2 Pins NMSI Mode SI RAMs En Figure 16-2. Enabling Connections to the TSA 16.
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CPM Multiplexing BRG5 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 Rx BRG1 BRG6 BRG2 BRG7 BRG3 BRG8 BRG4 BRGO5 BRGO6 BRGO7 BRGO8 BRGO1 BRGO2 BRGO3 BRGO4 Tx Rx Tx Rx Tx Rx Tx Rx Tx Bank of Clocks Selection Logic Rx Tx (Partially filled cross-switch logic programmed in the CMX registers.
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CPM Multiplexing Table 16-1.
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CPM Multiplexing NOTE After a clock source is selected, the clock is given an internal name. For the FCCs and SCCs, the names are RCLKx and TCLKx; for SMCs, the name is simply SMCLKx. These internal names are used only in NMSI mode to specify the clocks sent to the FCCs, SCCs or SMCs. These names do not correspond to any PowerQUICC II pins. 16.4 CMX Registers The following sections describe the CMX registers. 16.4.1 CMX UTOPIA Address Register (CMXUAR) NOTE This section does not apply to the MPC8250.
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CPM Multiplexing Table 16-2. CMXUAR Field Descriptions (continued) Bits Name Description 8–9 F1IRB FCC1 internal rate BRG selection. Selects the BRG to be connected to FCC 1 for internal rate operation. Used by the ATM controller; see Section 30.2.1.5, “Transmit External Rate and Internal Rate Modes.” 00 FCC1 internal rate clock is BRG5. 01 FCC1 internal rate clock is BRG6. 10 FCC1 internal rate clock is BRG7. 11 FCC1 internal rate clock is BRG8. 10–11 F12IRB FCC2 internal rate BRG selection.
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CPM Multiplexing Pins FCC1 5 These three bits always relate to an FCC1 master. 8 5 M S 5 5 M These two address bits relate to the master of FCC1 or FCC2 according to the programming. Bit 4 is the msb. 0 1 2 43 34 2 1 0 5 S FCC2 5 These three bits always relate to FCC2 master 8 M 5 S 5 5 M 5 S Figure 16-5. Connection of the Master Address • For slave mode—The user has two groups of five address pins each. The user decides which FCC uses each pin by programming CMXUAR[SADx].
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CPM Multiplexing NOTE The user must program the addresses of the PHYs to be consecutive for each FCC; that is, the address lines connected to each FCC must be consecutive. Figure 16-7 describes the interconnection between the receive external multi-PHY bus and the internal FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to the transmit multi-PHY bus using different dedicated parallel I/O pins. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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CPM Multiplexing MAD4 1 0 FCC1-RxAddr[4] PIO FCC2-RxAddr[3] (master) FCC2-RxAddr[0] (slave) MAD3 1 0 FCC1-RxAddr[3] PIO FCC2-RxAddr[4] (master) FCC2-RxAddr[1] (slave) FCC1-RxAddr[2] PIO FCC2-RxAddr[2] (slave) GND FCC1-RxAddr[1] PIO FCC2-RxAddr[3] (slave) 1 0 lsb FCC1 Rx Slave Address msb SAD4 GND FCC1-RxAddr[0] PIO FCC2-RxAddr[4] (slave) FCC1 Rx Master Address msb 1 0 SAD3 GND lsb 1 0 FCC1 SAD2 GND 1 0 SAD1 FCC2-RxAddr[2] (master) PIO FCC2-RxAddr[1] (master) PIO GND 1 0 SAD0 FCC2-RxA
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CPM Multiplexing 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR) The CMX SI1 clock route register (CMXSI1CR), displayed in Figure 16-8, defines the connection of SI1 to the clock sources that can be input from the bank of clocks. Field 0 1 2 3 4 5 6 7 RTA1CS RTB1CS RTC1CS RTD1CS TTA1CS TTB1CS TTC1CS TTD1CS Reset 0000_0000 R/W R/W Addr 0x0x11B00 Figure 16-8. CMX SI1 Clock Route Register (CMXSI1CR) Table 16-3 describes CMXSI1CR fields. Table 16-3.
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CPM Multiplexing Field 0 1 2 3 4 5 6 7 RTA2CS RTB2CS RTC2CS RTD2CS TTA2CS TTB2CS TTC2CS TTD2CS Reset 0000_0000 R/W R/W Addr 0x0x11B02 Figure 16-9. CMX SI2 Clock Route Register (CMXSI2CR) Table 16-4 describes CMXSI2CR fields. Table 16-4. CMXSI2CR Field Descriptions Bits Name 0 RTA2CS Receive TDM A2 clock source 0 TDM A2 receive clock is CLK13. 1 TDM A2 receive clock is CLK5. 1 RTB2CS Receive TDM B2 clock source 0 TDM B2 receive clock is CLK15. 1 TDM B2 receive clock is CLK17.
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CPM Multiplexing Field 0 1 — FC1 2 4 5 RF1CS 7 8 TF1CS Reset 9 FC2 12 RF2CS 13 15 TF2CS 0000_0000_0000_0000 R/W R/W Addr 0x0x11B04 Field 10 16 17 — FC3 18 20 21 RF3CS Reset 23 24 TF3CS 31 — 0000_0000_0000_0000 R/W R/W Addr 0x11B06 Figure 16-10. CMX FCC Clock Route Register (CMXFCR) Table 16-5 describes CMXFCR fields. Table 16-5.
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CPM Multiplexing Table 16-5. CMXFCR Field Descriptions (continued) Bits Name Description 8-9 FC2 10–12 RF2CS Receive FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 01). 000 FCC2 receive clock is BRG5. 001 FCC2 receive clock is BRG6. 010 FCC2 receive clock is BRG7. 011 FCC2 receive clock is BRG8. 100 FCC2 receive clock is CLK13. 101 FCC2 receive clock is CLK14. 110 FCC2 receive clock is CLK15. 111 FCC2 receive clock is CLK16.
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CPM Multiplexing Table 16-5. CMXFCR Field Descriptions (continued) Bits 21–23 Name TF3CS Transmit FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1). 000 FCC3 transmit clock is BRG5. 001 FCC3 transmit clock is BRG6. 010 FCC3 transmit clock is BRG7. 011 FCC3 transmit clock is BRG8. 100 FCC3 transmit clock is CLK13. 101 FCC3 transmit clock is CLK14. 110 FCC3 transmit clock is CLK15. 111 FCC3 transmit clock is CLK16. 24–31 16.4.
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CPM Multiplexing Table 16-6. CMXSCR Field Descriptions (continued) Bits Name Description 2–4 RS1CS Receive SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1). 000 SCC1 receive clock is BRG1. 001 SCC1 receive clock is BRG2. 010 SCC1 receive clock is BRG3. 011 SCC1 receive clock is BRG4. 100 SCC1 receive clock is CLK11. 101 SCC1 receive clock is CLK12. 110 SCC1 receive clock is CLK3. 111 SCC1 receive clock is CLK4. 5–7 TS1CS Transmit SCC1 clock source (NMSI mode).
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CPM Multiplexing Table 16-6. CMXSCR Field Descriptions (continued) Bits Name Description 17 SC3 SCC3 connection 0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O control register. 1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes. 18–20 RS3CS Receive SCC3 clock source (NMSI mode).
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CPM Multiplexing Table 16-6. CMXSCR Field Descriptions (continued) Bits Name Description 26–28 RS4CS Receive SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1). 000 SCC4 receive clock is BRG1. 001 SCC4 receive clock is BRG2. 010 SCC4 receive clock is BRG3. 011 SCC4 receive clock is BRG4. 100 SCC4 receive clock is CLK5. 101 SCC4 receive clock is CLK6. 110 SCC4 receive clock is CLK7. 111 SCC4 receive clock is CLK8 29–31 TS4CS Transmit SCC4 clock source (NMSI mode).
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CPM Multiplexing Table 16-7. CMXSMR Field Descriptions Bit s Name Description 2–3 SMC1CS SMC1 clock source (NMSI mode). SMC1 can take its clocks from one of the two BRGs or one of two pins from the bank of clocks. However, the SMC1 transmit and receive clocks must be the same when it is connected to the NMSI. 00 SMC1 transmit and receive clocks are BRG1. 01 SMC1 transmit and receive clocks are BRG7. 10 SMC1 transmit and receive clocks are CLK7. 11 SMC1 transmit and receive clocks are CLK9.
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Chapter 17 Baud-Rate Generators (BRGs) The CPM contains eight independent, identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the output of a BRG can be routed to a pin to be used externally.
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Baud-Rate Generators (BRGs) source for multiple BRGs. The external source signals are not synchronized internally before being used by the BRG. The BRG provides a divide-by-16 option (BRGCx[DIV16]) and a 12-bit prescaler (BRGCx[CD]) to divide the source clock frequency. The combined source-clock divide factor can be changed on-the-fly; however, two changes should not occur within two source clock periods.
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Baud-Rate Generators (BRGs) Table 17-1. BRGCx Field Descriptions Bits Name 0–13 — 14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the corresponding parallel I/O pin. 0 Enable the BRG. 1 Reset the BRG (software reset). 15 EN Enable BRG count. Used to dynamically stop the BRG from counting—useful for low-power modes. 0 Stop all clocks to the BRG.
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Baud-Rate Generators (BRGs) Table 17-2. BRG External Clock Source Options CLK BRG 1 17.2 2 3 4 5 BRG1 V V BRG2 V V 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 BRG3 V V BRG4 V V BRG7 V V BRG8 V V BRG5 V V BRG6 V V 1 6 1 7 1 8 1 9 2 0 Autobaud Operation on a UART During the autobaud process, a UART deduces the baud rate of its received character stream by examining the received pattern and its timing.
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Baud-Rate Generators (BRGs) 17.3 UART Baud Rate Examples For synchronous communication using the internal BRG, the BRGO must not exceed the BRG input clock divided by 2. Therefore, with a BRG input clock of 66MHz (generated using an external clock source: refer to BRGCx[EXTC]), the maximum BRGO rate is 33MHz. Program the UART to 16× oversampling when using the SCC as a UART. Rates of 8× and 32× are also available. Assuming 16× oversampling is chosen in the UART, the maximum data rate is 66 MHz ÷ 16 = 4.
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Baud-Rate Generators (BRGs) BRGCx[EXTC] = -----------------------------------------------------------------------------------------------( BRGCx[DIV16] ) • ( BRGCx[CD] + 1 ) For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, BRGCx[DIV16] = 0, and BRGCx[CD] = 389. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 18 Timers The CPM includes four identical 16-bit general-purpose timers or two 32-bit timers. Each general-purpose timer consists of a timer mode register (TMR), a timer capture register (TCR), a timer counter (TCN), a timer reference register (TRR), a timer event register (TER), and a timer global configuration register (TGCR). The TMRs contain the prescaler values programmed by the user. Figure 18-1 shows the timer block diagram.
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Timers • • • • • • • 18.
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Timers The restart gate mode performs the same function as normal mode, except it also resets the counter on the falling edge of TGATEx. This mode has applications in pulse interval measurement and bus monitoring as follows: • Pulse measurement—The restart gate mode can measure a low TGATEx. The rising edge of TGATEx completes the measurement and if TGATEx is connected externally to TINx, it causes the timer to capture the count value and generate a rising-edge interrupt.
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Timers Field 0 1 2 3 4 5 6 7 CAS2 — STP2 RST2 GM1 — STP1 RST1 Reset 0000_0000 R/W R/W Addr 0x0x10D80 Figure 18-3. Timer Global Configuration Register 1 (TGCR1) Table 18-1 describes TGCR1 fields. Table 18-1. TGCR1 Field Descriptions Bits Name 0 CAS2 1 — Description Cascade timers. 0 Normal operation. 1 Timers 1 and 2 cascade to form a 32-bit timer. Reserved, should be cleared. 2 STP 2 Stop timer. 0 Normal operation. 1 Reduce power consumption of the timer.
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Timers Field 0 1 2 3 4 5 6 7 CAS4 — STP4 RST4 GM2 — STP3 RST3 Reset 0000_0000 R/W R/W Addr 0x0x10D84 Figure 18-4. Timer Global Configuration Register 2 (TGCR2) Table 18-2 describes TGCR2 fields. Table 18-2. TGCR2 Field Descriptions Bit Name 0 CAS4 1 — Description Cascade timers. 0 Normal operation. 1 Timers 3 and 4 cascades to form a 32-bit timer. Reserved, should be cleared. 2 STP 4 Stop timer. 0 Normal operation. 1 Reduce power consumption of the timer.
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Timers 0 Field 7 8 PS Reset 9 CE 10 11 12 OM ORI FRR 13 14 ICLK 15 GE 0000_0000_0000_0000 R/W R/W Addr 0x0x10D90 (TMR1); 0x0x10D92 (TMR2); 0x0x10DA0 (TMR3); 0x0x10DA2 (TMR4) Figure 18-5. Timer Mode Registers (TMR1–TMR4) Table 18-3 describes TMR1–TMR4 register fields. Table 18-3. TMR1–TMR4 Field Descriptions Bits Name Description 0–7 PS Prescaler value. The prescaler is programmed to divide the clock input by values from 1 to 256.
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Timers 0 15 Field Timeout reference value Reset 0xFFFF R/W R/W Addr 0x0x10D94 (TRR1), 0x0x10D96 (TRR2), 0x0x10DA4 (TRR3), 0x0x10DA6 (TRR4) Figure 18-6. Timer Reference Registers (TRR1–TRR4) 18.2.5 Timer Capture Registers (TCR1–TCR4) Each timer capture register (TCR1–TCR4), shown in Figure 18-7, is used to latch the value of the counter according to TMRx[CE].
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Timers Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared before the timer negates the interrupt. 0 13 Field — 14 15 REF CAP Reset 0x0000 Addr 0x0x10DB0 (TER1); 0x0x10DB2 (TER2); 0x0x10DB4 (TER3); 0x0x10DB6 (TER4) Figure 18-9. Timer Event Registers (TER1–TER4) Table 18-4 describes TER fields. Table 18-4. TER Field Descriptions Bits Name Description 0–13 – 14 REF Output reference event. The counter has reached the TRR value.
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Chapter 19 SDMA Channels and IDMA Emulation The PowerQUICC II has two physical serial DMA (SDMA) channels. The CP implements two dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I2C—one for each transmitter and receiver. An additional four virtual SDMA channels are assigned to the programmable independent DMA (IDMA) channels. Figure 19-1 shows data flow paths. Data from the peripheral controllers can be routed to external RAM using the 60x bus (path 1) or the local bus (path 2).
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SDMA Channels and IDMA Emulation The SDMA channel can be assigned big-endian (Freescale) or little-endian format for accessing buffer data. These features are programmed in the receive and transmit registers associated with the FCCs, MCCs, SCCs, SMCs, SPI, and I2C. If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a unique interrupt in the SDMA status register (SDSR).
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SDMA Channels and IDMA Emulation Other Transaction SDMA Transaction Other Transaction CLK TS TA SDMA Internally Requests the Bus Figure 19-2. SDMA Bus Arbitration (Transaction Steal) 19.2 SDMA Registers The only user-accessible registers associated with the SDMA are the SDMA address registers, read-only register used for diagnostics in case of an SDMA bus error, the SDMA status register and the SDMA mask register. 19.2.
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SDMA Channels and IDMA Emulation 19.2.2 SDMA Mask Register (SDMR) The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format as the SDMA status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is enabled. If the bit is zero, the corresponding interrupt in the status register is masked. SDMR is cleared at reset. SDMR can be accessed at 0x0x1101C. 19.2.
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SDMA Channels and IDMA Emulation 1 Bit ranges are for .29µm (HiP3) Rev B.3, C.2 and .25µm (HiP4) devices. For .29µm Rev A.1 devices, refer to notes 2–4. 2 On .29µm Rev A.1 devices, [6–7]. 3 On .29µm Rev A.1 devices, MSNUM[0–4]. 4 On .29µm Rev A.1 devices, MSNUM[5]. 19.3 IDMA Emulation The CPM can be configured to provide general-purpose DMA functionality through the SDMA channel. Four general-purpose independent DMA (IDMA) channels are supported.
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SDMA Channels and IDMA Emulation • • Programmable byte-order conversion is supported independently for each DMA channel Supports programmable 60x-bus bandwidth usage for system performance optimization Peripheral to/from memory features include the following: • External DREQ, DACK, and DONE signals for each channel simplifies the peripheral interface for memory-to/from-peripheral transfers • Supports 1-, 2-, 4-, and 8-byte peripheral port sizes • Supports standard 60x burst accesses (four consecutive 64-
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SDMA Channels and IDMA Emulation Table 19-3. IDMA Transfer Parameters (continued) Parameter Description SS_MAX Initialized to (IDMA_transfer_buffer_size - 32) bytes, which is the steady-state maximum transfer size of IDMA transfer. This condition ensures that the transfer buffer is either filled by one SS_MAX bytes transfer and emptied in one or several transfers, or filled by one or several transfers to be emptied in one SS_MAX bytes transfer.
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SDMA Channels and IDMA Emulation First Phase 128 EOB (source) 96 EOB (destination) Read size = EOB(source) + SS_MAX Write size = EOB(destination) + SS_MAX 64 32 Note: After phase 1, less than 32 bytes (a burst) will remain in the internal buffer.
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SDMA Channels and IDMA Emulation 19.5.1.2 Normal Mode When external request mode is not selected (DCM[ERM] = 0), the IDMA channel operates automatically, ignoring DREQ. 19.5.1.3 Working with a PCI Bus NOTE This section applies to the MPC8250, the MPC8265, and the MPC8266 only. When working to/from the PCI bus (multiplexed with the local bus), the data usually comes on the bus in one long burst. The alignment policy described above to support 60x/local bus bursts does not affect its efficiency. 19.5.
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SDMA Channels and IDMA Emulation Any IDMA access to a peripheral uses the highest arbitration priority allowed for the DMA, providing faster bus access by bypassing other pending DMA requests. 19.5.2.1 Dual-Address Transfers The following sections discuss various dual-address transfers. 19.5.2.1.1 Peripheral to Memory Dual-address peripheral-to-memory data transfers are similar to memory-to-memory transfers using the three-phase algorithm; see Section 19.5.1, “Memory-to-Memory Transfers.
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SDMA Channels and IDMA Emulation related to the dual-port RAM bus are not relevant in fly-by mode. Each DREQ assertion triggers a transfer the size of the peripheral port. All transfers are made in single memory accesses accompanied by DACK assertion. When DONE is asserted externally or a STOP_IDMA command is issued, the current transfer is stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see Section 19.8.4, “IDMA Event Register (IDSR) and Mask Register (IDMR).
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SDMA Channels and IDMA Emulation Conversely, if the transfer size is small, the DMA requests the 60x bus more often, DMA latency increases and microcode efficiency decreases. Example: A channel is configured for data transfer from PCI memory to 60x memory. The PCI bus is not overloaded and can stand large bursts. Thus, the dual-port RAM buffer size is set as follows: • 64*32 = 2048 bytes (DCM[DMA_WRAP] = 101), allowing maximum of 2016 (STS = 63*32 = 2016) bytes long bursts at the source (PCI) bus.
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SDMA Channels and IDMA Emulation 19.6 IDMA Priorities Each IDMA channel can be programmed to have a higher or lower priority relative to the serial controllers or to have the lowest overall priority when requesting service from the CP. The IDMA priorities are programmed in RCCR[DRxQP]; see Section 14.3.7, “RISC Controller Configuration Register (RCCR).” Take care to avoid overrun or underrun errors in the serial controllers when selecting high priorities for IDMA.
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SDMA Channels and IDMA Emulation DREQx may be configured as either edge- or level-sensitive by programming the RCCR[DRxM]. When DREQx is configured as edge-sensitive, RCCR[EDMx] controls whether the request is generated on the rising or falling edge; see Section 14.3.7, “RISC Controller Configuration Register (RCCR).” DREQx is sampled at each rising edge of the clock to determine when a valid request is asserted by the device. 19.7.1.
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SDMA Channels and IDMA Emulation The first rising edge of the bus clock after the negation of the CS for the peripheral. Tmax T = 2 x (CPM clock cycle) Figure 19-7. Timing Requirement for DREQ Negation when IMDA Read from a Peripheral 19.7.1.2 Edge-Sensitive Mode For external devices that generate a pulsed signal for each operand to be transferred, edge-sensitive mode should be used.
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SDMA Channels and IDMA Emulation NOTE When DREQ is level-sensitive and DONE is an input to the PowerQUICC II, the system design must ensure that DONE is not asserted while DREQ is also asserted. In other words, the system must not request IDMA service and termination at the same time. 19.8 IDMA Operation Every IDMA operation involves the following steps—IDMA channel initialization, data transfer, and block termination.
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SDMA Channels and IDMA Emulation IDMAx BD Base Address (IBASE) BD 0 Source Device or Buffer 0 BD 1 Source Device or Buffer 1 BD 2 • • • Source Device or Buffer 2 •• • Destination Device or Buffer 0 Destination Device or Buffer 1 Destination Device or Buffer 2 •• • BD n Source Device or Buffer n Destination Device or Buffer n Figure 19-8.
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SDMA Channels and IDMA Emulation Table 19-4. IDMAx Parameter RAM Offset 1 Name Width 0x00 IBASE Hword IDMA BD table base address. Defines the starting location in the dual-port RAM for the set of IDMA BDs. It is an offset from the beginning of the dual-port RAM. The user must initialize IBASE before enabling the IDMA channel and should not overlap BD tables of two enabled serial controllers or IDMA channels or erratic operation results. IBASE should be 16-byte aligned.
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SDMA Channels and IDMA Emulation Table 19-4. IDMAx Parameter RAM (continued) Offset 1 Name 0x16 DTS Width Description Hword Destination transfer size in bytes. All transfers to destination (except the start alignment and the tail) are written to the bus using this parameter. In peripheral-to-memory mode, DTS should equal SS_MAX. In memory-to-peripheral modes, initialize DTS to the peripheral port size if transfer’s destination is a peripheral.
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SDMA Channels and IDMA Emulation Table 19-5. DCM Field Descriptions Bits Name Description 0 FB Fly-by mode. See Table 19-6.. 0 Dual-address mode. 1 Fly-by (single-address) mode. The internal IDMA transfer buffer is not used. Valid only in peripheral-to-memory (S/D=10) or memory-to-peripheral (S/D=01) modes. 1 LP Low priority. Applies to memory-to-memory accesses only. See Section 4.3.2, “System Configuration and Protection Registers.
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SDMA Channels and IDMA Emulation Table 19-5. DCM Field Descriptions (continued) Bits Name Description 12 ERM External request mode. 0 The CP transfers continuously, as if an external level request is asserted, regardless of the DREQ signal assertion. The CP stops the transfer when there are no more valid BDs or after a STOP_IDMA command is issued. DONE assertion by a external device is ignored. 1 The CP responds to DREQ as configured (edge/level) by performing single- or dual-address transfers.
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SDMA Channels and IDMA Emulation Table 19-6. IDMA Channel Data Transfer Operation (continued) S/D FB 00 0 Read From Write To Memory (STS = SS_MAX or less) Description (Steady-State Operation) Read from memory: Filling internal buffer in one or more DMA transfers. On the bus: singles or bursts, depends on STS Memory (DTS = SS_MAX) Write to memory: in one DMA transfer, internal buffer empties.
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SDMA Channels and IDMA Emulation Table 19-7. Valid Memory-to-Memory STS/DTS Values Internal DMA_WRAP Buffer SS_MAX Size 101 2048 STS (in Bytes) DTS (in Bytes) Number of Transfers to Fill Internal Buffer STS Size DTS Size 63 * 32 63 * 32, 9 * 32, 7 * 32, 32 1 1, 7, 9, 63 63 * 32, 9 * 32, 7 * 32, 32 63 * 32 1, 7, 9, 63 1 63 * 32 Table 19-8 describes valid STS/DTS values for memory/peripheral operations. Table 19-8.
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SDMA Channels and IDMA Emulation transfer sizes allows longer transfers to memory devices, optimizes bus usage and thus reduces the overall load on the CP. For example, 2,016 bytes can be transferred by issuing one START_IDMA command using a 2-Kbyte internal transfer buffer, or by issuing 63 START_IDMA commands using a 64-byte buffer. The load on the CP in the second case is about 63 times more than the first. 19.8.
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SDMA Channels and IDMA Emulation Offset + 0 0 1 2 3 4 5 6 V — W I L — CM — SDTB Offset + 2 — SGBL SBO Offset + 4 7 8 — 9 10 11 SDN DDN DGBL 12 13 DBO 14 15 — DDTB — Data Length Offset + 6 Offset + 8 Source Data Buffer Pointer Offset + A Offset + C Destination Data Buffer Pointer Offset + E Figure 19-11. IDMA BD Structure Table 19-10 describes IDMA BD fields. Table 19-10.
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SDMA Channels and IDMA Emulation Table 19-10. IDMA BD Field Descriptions (continued) Offset 0x02 Bits Name Description 6 CM Continuous mode 0 Buffer chaining mode. The CP clears V after this BD is serviced. Buffer chaining mode is used to transfer large quantities of data into non-contiguous buffer areas. The user can initialize BDs ahead of time, if needed. The CP automatically loads the IDMA registers from the next BD values when the transfer is terminated. 1 Auto buffer mode (continuous mode).
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SDMA Channels and IDMA Emulation Table 19-10. IDMA BD Field Descriptions (continued) Offset Bits Name 6 SDTB 7-15 — 0x04 0–31 Data Length Number of bytes the IDMA transfers. Should be programmed to a value greater than zero. Note: When operating with a peripheral that accepts only single bus transactions (transfer size < 32), data length should be a multiple of the peripheral transfer size (STS for S/D = 10, or DTS for S/D = 01).
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SDMA Channels and IDMA Emulation In external request mode (ERM=1), the START_IDMA command initializes the channel, but the first data transfer is performed after external DREQx assertion. In internal request mode (ERM=0), the START_IDMA command starts the data transfer almost immediately, with a delay which depends on the CP load. 19.9.2 STOP_IDMA Command The STOP_IDMA command is issued to stop the transfer of an IDMA channel.
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SDMA Channels and IDMA Emulation 19.10.1 Externally Recognizing IDMA Operand Transfers The following ways can be used determine externally that the IDMA is executing a bus transaction: • The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be programmed to a unique code that identifies an IDMA transfer. • The DACK signal shows accesses to the peripheral device. DACK activates on either the source or destination bus transactions, depending on DCM[S/D]. 19.
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SDMA Channels and IDMA Emulation Table 19-13. Parallel I/O Register Programming—Port A Channel Signal Pin PPARA PDIRA PODRA PSORA Default IDMA3 DREQ3 (I) PA[0] 1 0 0 1 GND DACK3 (O) PA[2] 1 1 0 1 — DONE3 (I/O) PA[1] 1 0 1 1 VDD DREQ4 (I) PA[5] 1 0 0 1 GND DACK4 (O) PA[3] 1 1 0 1 — DONE4 (I/O) PA[4] 1 0 1 1 VDD IDMA4 Table 19-14 describes parallel I/O register programming for port D (optional). Table 19-14.
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SDMA Channels and IDMA Emulation Table 19-15. Example: Peripheral-to-Memory Mode—IDMA2 (continued) Important Init Values Description DCM(SINC) = 0 The peripheral address are not incremented after transfers, fixed location. DCM(DINC) = 1 The memory address is incremented after every transfer. DPR_BUF = 0x0DC0 Initiated to address aligned to 64 (bit[5–0]= 00000). IBASE = IBDPTR = 0x0030 The current BD pointer is set to the BD table base address (aligned 16 -bits[3–0] = 0).
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SDMA Channels and IDMA Emulation 19.12.2 Memory-to-Peripheral Fly-By Mode—IDMA3 In the example in Table 19-16, IDMA3 transfers data from a memory device to a 4-byte wide peripheral, both on the 60x bus. The transfers are made by issuing 4-byte read transactions to the memory and asserting DACK so the peripheral samples the data from the bus directly. No address is dedicated for the peripheral, and no internal buffer is defined in this mode.
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SDMA Channels and IDMA Emulation Table 19-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3 (continued) Important Init Values CPCR = 0x26C1_0009 Description START_IDMA command. IDMA3 page-01001 SBC-10110 op-1001 FLG=1.This write starts the channel operation. DMA operation: START_IDMA: Initialize all parameter RAM values, wait for DREQ to open the first BD. Steady state: Every DREQ triggers a 4-byte transfer in single address transaction.
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SDMA Channels and IDMA Emulation Table 19-17. Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1 (continued) Important Init Values DCM[DINC] = 1 Description The destination memory address is incremented after every transfer. IBASE=IBDPTR= 0x0030 The current BD pointer is set to the BD ring Base address (aligned 16 -bits[3–0]=0000). DPR_BUF = 0x0800 Initiated to address aligned to 2048 (bits[10–0] = 000_0000_0000).
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Chapter 20 Serial Communications Controllers (SCCs) The PowerQUICC II has four serial communications controllers (SCCs), which can be configured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks. An SCC has many physical interface options such as interfacing to TDM buses, ISDN buses, and standard modem interfaces.
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Serial Communications Controllers (SCCs) 60x Bus Control Registers DPLL and Clock Recovery Peripheral Bus Clock Generator TCLK RCLK Internal Clocks Modem Lines RXD Decoder Rx Control Unit Delimiter Rx Data FIFO Tx Data FIFO Shifter Shifter Tx Control Unit Delimiter Modem Lines Encoder TXD Figure 20-1. SCC Block Diagram 20.1 Features The following is a list of the main SCC features. (Performance figures assume a 25-MHz system clock.
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Serial Communications Controllers (SCCs) • • Fully transparent option for one half of an SCC (Rx/Tx) while another protocol executes on the other half (Tx/Rx) Echo and local loopback modes for testing 20.1.1 The General SCC Mode Registers (GSMR1–GSMR4) Each SCC contains a general SCC mode register (GSMR) that defines options common to most of the protocols. GSMR_L contains the low-order 32 bits; GSMR_H, shown in Figure 20-2, contains the high-order 32 bits.
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Serial Communications Controllers (SCCs) Table 20-1. GSMR_H Field Descriptions (continued) Bit Name Description 19–20 TRX, TTX Transparent receiver/transmitter. The receiver, transmitter, or both can use totally transparent operation, regardless of GSMR_L[MODE]. For example, to configure the transmitter as a UART and the receiver for totally transparent operations, set MODE = 0b0100 (UART), TTX = 0, and TRX = 1. 0 Normal operation.
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Serial Communications Controllers (SCCs) Table 20-1. GSMR_H Field Descriptions (continued) Bit Name Description 28–29 SYNL Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR) definition in Section 23.9, “Sending and Receiving the Synchronization Sequence,” (BISYNC) and Section 24.4.1.1, “In-Line Synchronization Pattern,” (transparent). 00 An external sync (CD) is used instead of the sync pattern in the DSR. 01 4-bit sync.
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Serial Communications Controllers (SCCs) Table 20-2. GSMR_L Field Descriptions (continued) Bit Name 1–2 EDGE Clock edge. Determines the clock edge the DPLL uses to adjust the receive sample point due to jitter in the received signal. Ignored in UART protocol or if the 1x clock mode is selected in RDCR. 00 Both the positive and negative edges are used for changing the sample point (default). 01 Positive edge. Only the positive edge of the received signal is used to change the sample point.
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Serial Communications Controllers (SCCs) Table 20-2. GSMR_L Field Descriptions (continued) Bit Name Description 11–12 TPP Tx preamble pattern. Determines what, if any, bit pattern should precede each Tx frame. The preamble pattern is sent before the first flag/sync of the frame. TPP is ignored in UART mode. The preamble length is programmed in TPL; the preamble pattern is typically sent to a receiving station that uses a DPLL for clock recovery.
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Serial Communications Controllers (SCCs) Table 20-2. GSMR_L Field Descriptions (continued) Bit Name Description 24–25 DIAG Diagnostic mode. 00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and transmitted through TXD. The SCC uses modem signals to enable or disable transmission and reception. These timings are shown in Section 20.3.5, “Controlling SCC Timing with RTS, CTS, and CD.” 01 Local loopback mode.
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Serial Communications Controllers (SCCs) Table 20-2. GSMR_L Field Descriptions (continued) Bit 28–31 20.1.2 Name Description MODE Channel protocol mode. See also GSMR_H[TTX, TRX].
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Serial Communications Controllers (SCCs) 20.1.4 Transmit-on-Demand Register (TODR) In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R bit of the next TxBD to see if a new frame/buffer is requested. Depending on the SCC configuration, this polling occurs every 8–32 serial Tx clocks.
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Serial Communications Controllers (SCCs) • — For an RxBD, this is the number of bytes the controller writes into the buffer. The CPM writes the length after received data is placed into the associated buffer and the buffer closed. In frame-based protocols (but not including SCC transparent operation), this field contains the total frame length, including CRC bytes.
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Serial Communications Controllers (SCCs) Dual-Port RAM External Memory Tx Buffer Descriptors Status and Control SCCx TxBD Table Buffer Length Buffer Pointer Tx Buffer Rx Buffer Descriptors SCCx RxBD Table Status and Control SCCx RxBD Table Pointer Buffer Length Buffer Pointer SCCx TxBD Table Pointer Rx Buffer Figure 20-7. SCC BD and Buffer Memory Structure In all protocols, BDs can point to buffers in the internal dual-port RAM.
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Serial Communications Controllers (SCCs) 20.3 SCC Parameter RAM Each SCC parameter RAM area begins at the same offset from each SCC base area. Section 20.3.1, “SCC Base Addresses,” describes the SCC’s base addresses. The protocol-specific portions of the SCC parameter RAM are discussed in the specific protocol descriptions and the part that is common to all SCC protocols is shown in Table 20-4. Some parameter RAM values must be initialized before the SCC can be enabled.
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Serial Communications Controllers (SCCs) Table 20-4. SCC Parameter RAM Map for All Protocols (continued) Offset 1 0x08 Name RSTATE 0x0C 0x10 RBPTR Width Description Word Rx internal state3 Word Rx internal buffer pointer2. The Rx and Tx internal buffer pointers are updated by the SDMA channels to show the next address in the buffer to be accessed. Hword Current RxBD pointer. Points to the current BD being processed or to the next BD the receiver uses when it is idling.
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Serial Communications Controllers (SCCs) Table 20-5. Parameter RAM—SCC Base Addresses 1 20.3.2 Page Address 1 Peripheral Size (Bytes) 1 0x8000 SCC1 256 2 0x8100 SCC2 256 3 0x8200 SCC3 256 4 0x8300 SCC4 256 Offset from RAM_Base Function Code Registers (RFCR and TFCR) There are eight separate function code registers for the four SCC channels, four for Rx buffers (RFCR1–RFCR4) and four for Tx buffers (TFCR1–TFCR4).
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Serial Communications Controllers (SCCs) 20.3.3 Handling SCC Interrupts To allow interrupt handling for SCC-specific events, event, mask, and status registers are provided within each SCC’s internal memory map area; see Table 20-7. Because interrupt events are protocol-dependent, event descriptions are found in the specific protocol chapters. Table 20-7.
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Serial Communications Controllers (SCCs) Additional information about interrupt handling can be found in Section 4.2, “Interrupt Controller.” 20.3.4 Initializing the SCCs The SCCs require that a number of registers and parameters be configured after a power-on reset. Regardless of the protocol used, follow these steps to initialize SCCs: 1. Write the parallel I/O ports to configure and connect the I/O pins to the SCCs. 2.
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Serial Communications Controllers (SCCs) TCLK TXD (Output) RTS (Output) First Bit of Frame Data Last Bit of Frame Data CTS (Input) NOTE: 1. A frame includes opening and closing flags and syncs, if present in the protocol. Figure 20-9. Output Delay from RTS Asserted for Synchronous Protocols When RTS is asserted, if CTS is not already asserted, delays to the first data bit depend on when CTS is asserted. Figure 20-10 shows that the delay between CTS and the data can be approximately 0.
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Serial Communications Controllers (SCCs) TCLK TXD (Output) Data Forced High First Bit of Frame Data RTS (Output) CTS (Input) RTS Forced High CTS Sampled Low Here CTS Sampled High Here CTS Lost Signaled in Frame B NOTE: 1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK TXD (Output) Data Forced High First Bit of Frame Data RTS (Output) RTS Forced High CTS (Input) CTS Lost Signaled in Frame B NOTE: 1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur. Figure 20-11.
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Serial Communications Controllers (SCCs) RCLK RXD (Input) CD (Input) First Bit of Frame Data Last Bit of Frame Data CD Sampled Low Here CD Sampled High Here NOTE: 1. GSMR_H[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
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Serial Communications Controllers (SCCs) 20.3.6 Digital Phase-Locked Loop (DPLL) Operation Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock information from a received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or NRZI encodings are available.
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Serial Communications Controllers (SCCs) TENC Divided Clock TDCR HSTCLK TEND HSTCLK 0 TCLK 1 DPLL Transmitter S 1x Mode D HSTCLK Q TXEN CLK Encoded SCCT Data 0 1 0 1 TINV D S HSTCLK S Q TXD CLK 1x Mode TENC = NRZI Figure 20-14. DPLL Transmitter Block Diagram The DPLL can be driven by one of the baud rate generator outputs or an external clock, CLKx. In the block diagrams, this clock is labeled HSRCLK/HSTCLK.
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Serial Communications Controllers (SCCs) Table 20-8. Preamble Requirements (continued) Decoding Method FM1 Manchester Differential Manchester Preamble Pattern Minimum Preamble Length Required All zeros 8-bit 101010...10 8-bit All ones 8-bit The DPLL can also be used to invert the data stream of a transfer. This feature is available in all encodings, including standard NRZ format. Also, when the transmitter is idling, the DPLL can either force TXD high or continue encoding the data supplied to it.
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Serial Communications Controllers (SCCs) If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC, TENC]. Coding definitions are shown in Table 20-9. Table 20-9. DPLL Codings Coding Description NRZ A one is represented by a high level for the duration of the bit and a zero is represented by a low level. NRZI Mark A one is represented by no transition at all. A zero is represented by a transition at the beginning of the bit (the level present in the preceding bit is reversed).
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Serial Communications Controllers (SCCs) 4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART TRANSMIT command. 5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming the R bit is set. 20.3.7.2 Reset Sequence for an SCC Transmitter The following steps reinitialize an SCC transmit parameters to the reset state: 1. Clear GSMR_L[ENT]. 2. Make any modifications then issue the INIT TX PARAMETERS command. 3. Set GSMR_L[ENT]. 20.3.7.
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Serial Communications Controllers (SCCs) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 21 SCC UART Mode The universal asynchronous receiver transmitter (UART) protocol is commonly used to send low-speed data between devices. The term asynchronous is used because it is not necessary to send clocking information along with the data being sent. UART links are typically 38400 baud or less and are character-based. Asynchronous links are used to connect terminals with other devices.
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SCC UART Mode In synchronous UART (isochronous operation), a separate clock signal is explicitly provided with the data. Start and stop bits are present in synchronous UART, but oversampling is not required because the clock is provided with each bit. The general SCC mode register (GSMR) is used to configure an SCC channel to function in UART mode, which provides standard serial I/O using asynchronous character-based (start-stop) protocols with RS-232C-type lines.
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SCC UART Mode 3. Address/data bit (optional) 4. Parity bit (optional) 5. Stop bits The receiver uses a clock 8×, 16×, or 32× faster than the baud rate and samples each bit of the incoming data three times around its center. The value of the bit is determined by the majority of those samples; if all do not agree, the noise indication counter (NOSEC) in parameter RAM is incremented.
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SCC UART Mode Table 21-1. UART-Specific SCC Parameter RAM Memory Map Offset 1 Name 0x30 — 0x38 MAX_IDL Hword Maximum idle characters. When a character is received, the receiver begins counting idle characters. If MAX_IDL idle characters are received before the next data character, an idle timeout occurs and the buffer is closed, generating a maskable interrupt request to the core to receive the data from the buffer. Thus, MAX_IDL offers a way to demarcate frames.
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SCC UART Mode Table 21-1. UART-Specific SCC Parameter RAM Memory Map (continued) Offset 1 Name 0x4C RTEMP Hword Temp storage 0x60 RCCM Hword Receive control character mask. Used to mask comparison of CHARACTER1–8 so classes of control characters can be defined. A one enables the comparison, and a zero masks it. 0x62 RCCR Hword Receive control character register. Used to hold the last rejected control character (not written to the Rx buffer). Generates a maskable interrupt.
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SCC UART Mode 21.7 SCC UART Commands The transmit commands in Table 21-2 are issued to the CP command register (CPCR). Table 21-2. Transmit Commands Command STOP TRANSMIT GRACEFUL STOP TRANSMIT RESTART TRANSMIT INIT TX PARAMETERS Description After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling the first BD in the TxBD table every 8 Tx clocks. STOP TRANSMIT disables character transmission.
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SCC UART Mode • • Automatic multidrop mode—The controller checks the incoming address character and accepts subsequent data only if the address matches one of two user-defined values. The two 16-bit address registers, UADDR1 and UADDR2, support address recognition. Only the lower 8 bits are used so the upper 8 bits should be cleared; for addresses less than 8 bits, unused high-order bits should also be cleared. The incoming address is checked against UADDR1 and UADDR2.
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SCC UART Mode Offset 1 0 1 0x50 E R — CHARACTER1 0x52 E R — CHARACTER2 • • • • • • • • • • • • • • • 0x5E E R — CHARACTER8 0x60 1 1 — RCCM 2 0x62 1 7 8 15 — RCCR From SCC x base address Figure 21-3. Control Character Table Table 21-4 describes the data structure used in control character recognition. Table 21-4. Control Character Table, RCCM, and RCCR Descriptions Offset Bits 0x50– 0x5E 0 E End of table. In tables with eight control characters, E is always 0.
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SCC UART Mode 21.10 Hunt Mode (Receiver) A UART receiver in hunt mode remains deactivated until an idle or address character is recognized, depending on PSMR[UM]. A receiver is forced into hunt mode by issuing an ENTER HUNT MODE command. The receiver aborts any message in progress when ENTER HUNT MODE is issued. When the message is finished, the receiver is reenabled by detecting the idle line (one idle character) or by the address bit of the next message, depending on PSMR[UM].
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SCC UART Mode Table 21-5. TOSEQ Field Descriptions (continued) Bit Name 7 A Description Address. Setting this bit indicates an address character for multidrop mode. 8–15 CHARSEND Character send. Contains the character to be sent. Any 5- to 8-bit character value can be sent in accordance with the UART configuration. The character should be placed in the lsbs of CHARSEND. This value can be changed only while REA = 0. 21.
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SCC UART Mode Table 21-6. DSR Fields Descriptions Bit Name Description 0 — 1–4 FSB 5–6 — 0b11 7–8 — 0b00 9–14 — 0b111111 15 — 0b0 0b0 Fractional stop bits. For 16× oversampling: 1111 Last transmitted stop bit 16/16. Default value after reset. 1110 Last transmitted stop bit 15/16. … 1000 Last transmitted stop bit 9/16. 0xxx Invalid. Do not use. For 32× oversampling: 1111 Last transmitted stop bit 32/32. Default value after reset. 1110 Last transmitted stop bit 31/32.
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SCC UART Mode Table 21-8. Reception Errors Error Description Overrun Occurs when the channel overwrites the previous character in the Rx FIFO with a new character, losing the previous character. The channel then writes the new character to the buffer, closes it, sets RxBD[OV], and generates an RX interrupt if not masked. In automatic multidrop mode, the receiver enters hunt mode immediately.
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SCC UART Mode 0 Field FLC 1 SL 2 3 CL 4 5 UM Reset 6 7 8 FRZ RZS 9 SYN DRT 10 11 — PEN 12 13 14 RPM 15 TPM 0 R/W R/W Addr 0x0x11A08 (PSMR1); 0x0x11A28 (PSMR2); 0x0x11A48 (PSMR3); 0x0x11A68 (PSMR4) Figure 21-6. Protocol-Specific Mode Register for UART (PSMR) Table 21-9 describes PSMR UART fields. Table 21-9. PSMR UART Field Descriptions Bit Name Description 0 FLC Flow control. 0 Normal operation. The GSMR and port C registers determine the mode of CTS.
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SCC UART Mode Table 21-9. PSMR UART Field Descriptions (continued) Bit Name Description 7 RZS Receive zero stop bits. 0 The receiver operates normally, but at least one stop bit is needed between characters. A framing error is issued if a stop bit is missing. Break status is set if an all-zero character is received with a zero stop bit. 1 Configures the receiver to receive data without stop bits. Useful in V.
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SCC UART Mode • • An ENTER HUNT MODE or CLOSE RXBD command is issued. An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 21-7 shows an example of how RxBDs are used in receiving. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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SCC UART Mode E Rx BD 0 ID MRBLR = 8 Bytes for this SCC Buffer 0 0 Byte 1 Length 0008 Byte 2 Pointer 32-Bit Buffer Pointer Status Buffer Full 8 Bytes etc.
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SCC UART Mode Offset + 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 E — W I C A CM ID AM — BR FR PR — OV CD Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 21-8. SCC UART Receive Buffer Descriptor (RxBD) Table 21-10 describes RxBD status and control fields. Table 21-10. SCC UART RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty. 0 The buffer is full or reception was aborted due to an error.
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SCC UART Mode Table 21-10. SCC UART RxBD Status and Control Field Descriptions (continued) Bits Name Description 10 BR Break received. Set when a break sequence is received as data is being received into this buffer. 11 FR Framing error. Set when a character with a framing error (a character without a stop bit) is received and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data. 12 PR Parity error.
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SCC UART Mode Table 21-11. SCC UART TxBD Status and Control Field Descriptions (continued) Bit Name Description 4 CR Clear-to-send report. 0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs, TxBD[CT] may not be set in the correct TxBD or may not be set at all. Asynchronous flow control, however, continues to function normally. 1 Normal CTS lost error reporting and three bits of idle are sent between consecutive buffers.
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SCC UART Mode Characters Received by UART 10 Characters Time Line Idle Line Idle RXD Break CD UART SCCE Events CD IDL RX CCR IDL RX IDL BRKS BRKE IDL CD Notes: 1. The first RX event assumes Rx buffers are 6 bytes each. 2. The second IDL event occurs after an all-ones character is received. 3. The second RX event position is programmable based on the MAX_IDL value. 4. The BRKS event occurs after the first break character is received. 5.
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SCC UART Mode Table 21-12. SCCE/SCCM Field Descriptions for UART Mode 1 Bit Name Description 0–5 — Reserved, should be cleared. Refer to note 1 below. 6 AB Autobaud. Set when an autobaud lock is detected. The core should rewrite the baud rate generator with the precise divider value. See Chapter 17, “Baud-Rate Generators (BRGs).” 7 IDL Idle sequence status changed. Set when the channel detects a change in the serial line. The line’s real-time status can be read in SCCS[ID].
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SCC UART Mode Table 21-13. UART SCCS Field Descriptions Bits Name Description 0–6 — Reserved, should be cleared. 7 ID Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle. 1 The line is idle. 21.21 SCC UART Programming Example The following initialization sequence is for the 9,600 baud, 8 data bits, no parity, and stop bit of an SCC in UART mode assuming a 66-MHz system frequency. BRG1 and SCC2 are used.
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SCC UART Mode 18. Initialize the TxBD. Assume the buffer is at 0x0000_2000 in main memory and contains sixteen 8-bit characters. Write 0xB000 to the TxBD[Status and Control], 0x0010 to TxBD[Data Length], and 0x00002000 to TxBD[Buffer Pointer]. 19. Write 0xFFFF to SCCE2 to clear any previous events. 20. Write 0x0003 to SCCM2 to allow the TX and RX interrupts. 21. Write 0x0040_0000 to the SIMR_L so SCC2 can generate a system interrupt. Initialize SIPNR_L by writing 0xFFFF_FFFF to it. 22.
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SCC UART Mode Table 21-14. UART Control Characters for S-Records Example (continued) Character Description XOFF E should be cleared; R should be set. Whenever the core receives a control-character-received (CCR) interrupt and the RCCR contains XOFF, the software should immediately stop transmitting by setting PSMR[FRZ]. This keeps the other station from losing data when it runs out of Rx buffers. XON XON should be received after XOFF. E should be cleared and R should be set.
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Chapter 22 SCC HDLC Mode High-level data link control (HDLC) is one of the most common protocols in the data link layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC, SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in particular. Figure 22-1 shows the HDLC framing structure. HDLC uses a zero insertion/deletion process (bit-stuffing) to ensure that a data bit pattern matching the delimiter flag does not occur in a field between flags.
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SCC HDLC Mode • • • • • • • • • 22.
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SCC HDLC Mode and an address mask. The SCC compares the received address field with the user-defined values after masking with the address mask. To detect broadcast (all ones) address frames, one address register must be written with all ones. If an address match is detected, the SCC fetches the next BD and SCC starts transferring the incoming frame to the buffer if it is empty. When the buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if RxBD[I] is set.
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SCC HDLC Mode Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map (continued) 1 Offset 1 Name Width Description 0x46 MFLR Hword Max frame length register. The HDLC compares the incoming HDLC frame’s length with the user-defined limit in MFLR. If the limit is exceeded, the rest of the frame is discarded and RxBD[LG] is set in the last BD of that frame. At the end of the frame the SCC reports frame status and frame length in the last RxBD.
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SCC HDLC Mode address comparisons. Receive errors are reported through the RxBD; transmit errors are reported through the TxBD. 22.6 SCC HDLC Commands The transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are described in Table 22-2. Table 22-2.
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SCC HDLC Mode Table 22-4. Transmit Errors Error Transmitter Underrun Description The channel stops transmitting, closes the buffer, sets TxBD[UN], and generates a TXE interrupt if not masked. Transmission resumes when a RESTART TRANSMIT command is issued. The SCC send and receive FIFOs are 32 bytes each. The channel stops transmitting, closes the buffer, sets TxBD[CT], and generates the TXE interrupt if CTS Lost during Frame not masked. Transmission resumes after a RESTART TRANSMIT command.
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SCC HDLC Mode 22.8 HDLC Mode Register (PSMR) The protocol-specific mode register (PSMR), shown in Figure 22-3, functions as the HDLC mode register. 0 Field 3 NOF 4 5 CRC Reset 6 7 8 RTE — FSE 9 10 11 12 DRT BUS BRM MFF 13 15 — 0 R/W R/W Addr 0x0x11A08 (PSMR1); 0x0x11A28 (PSMR2); 0x0x11A48 (PSMR3); 0x0x11A68 (PSMR4) Figure 22-3. HDLC Mode Register (PSMR) Table 22-6 describes PSMR HDLC fields. Table 22-6.
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SCC HDLC Mode Table 22-6. PSMR HDLC Field Descriptions (continued) Bits Name Description 11 BRM HDLC bus RTS mode. Valid only if BUS = 1. Otherwise, it is ignored. 0 Normal RTS operation during HDLC bus mode. RTS is asserted on the first bit of the Tx frame and negated after the first collision bit is received. 1 Special RTS operation during HDLC bus mode.
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SCC HDLC Mode Table 22-7. SCC HDLC RxBD Status and Control Field Descriptions (continued) Bits Name Description 4 L Last buffer in frame. 0 Not the last buffer in frame. 1 Last buffer in frame. Indicates reception of a closing flag or an error, in which case one or more of the CD, OV, AB, and LG bits are set. The SCC writes the number of frame octets to the data length field. 5 F First in frame. 0 Not the first buffer in a frame. 1 First buffer in a frame. 6 CM Continuous mode.
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SCC HDLC Mode E Status MRBLR = 8 Bytes for this SCC Buffer Receive BD 0 L F 0 0 1 Address 1 Length 0x0008 Address 2 Pointer 32-Bit Buffer Pointer Buffer Full 8 Bytes Control Byte 5 Information (I-Field) Bytes Receive BD 1 L F E Status 0 Buffer 1 0 Last I-Field Byte Length 0x000B Pointer 32-Bit Buffer Pointer CRC Byte 1 Buffer Closed When Closing Flag Received 8 Bytes CRC Byte 2 Empty Receive BD 2 L F AB E Status 0 1 1 Buffer 1 Length 0x0003 Pointer 32-Bit Buffer Pointer
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SCC HDLC Mode 22.10 SCC HDLC Transmit Buffer Descriptor (TxBD) The CP uses the TxBD, shown in Figure 22-6, to confirm transmissions and indicate error conditions. Offset + 0 0 1 2 3 4 5 6 7 R — W I L TC CM 13 — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer 14 15 UN CT Offset + 6 Figure 22-6. SCC HDLC Transmit Buffer Descriptor (TxBD) Table 22-8 describes HDLC TxBD status and control fields. Table 22-8.
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SCC HDLC Mode The data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” 22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) The SCC event register (SCCE) is used as the HDLC event register to report events recognized by the HDLC channel and to generate interrupts. When an event is recognized, the SCC sets the corresponding SCCE bit.
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SCC HDLC Mode Table 22-9. SCCE/SCCM Field Descriptions (continued)1 1 Bits Name Description 14 TXB Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For the last buffer in the frame, TXB is not set before the last bit of the closing flag begins its transmission; otherwise, it is set after the last byte of the buffer is written to the Tx FIFO. 15 RXB Receive buffer. Enabled by setting RxBD[I].
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SCC HDLC Mode 22.12 SCC HDLC Status Register (SCCS) The SCC status register (SCCS), shown in Figure 22-9, permits monitoring of real-time status conditions on RXD. The real-time status of CTS and CD are part of the port C parallel I/O. 0 Field 4 — Reset 5 6 7 FG CS ID 0000_0000 R/W R Addr 0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4) Figure 22-9. CC HDLC Status Register (SCCS) Table 22-10 describes HDLC SCCS fields. Table 22-10.
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SCC HDLC Mode 3. Configure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear PDIRC[29] and PSORC[29]. 4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and CMXSCR[T2CS]. 5. Connect the SCC2 to the NMSI (its own set of pins). clear CMXSCR[SC2]. 6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008. 7.
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SCC HDLC Mode 25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and prevent multiple frames in the FIFO. 26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write ensures that ENT and ENR are enabled last. NOTE After 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer is closed after a frame is received. Frames larger than 256 bytes cause a busy (out-of-buffers) condition because only one RxBD is prepared.
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SCC HDLC Mode transmission continues. If the echo bit is ever 0 when the transmit bit is 1, a collision occurs between terminals; the station(s) that sent a zero stops transmitting. The station that sent a 1 continues as normal. The I.430 and T1.605 standards provide a physical layer protocol that allows multiple terminals to share one physical connection.
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SCC HDLC Mode In single-master configuration, a master station transmits to any slave station without collisions. Slaves communicate only with the master, but can experience collisions in their access over the bus. In this configuration, a slave that communicates with another slave must first transmit its data to the master, where the data is buffered in RAM and then resent to the other slave. The benefit of this configuration, however, is that full-duplex operation can be obtained.
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SCC HDLC Mode While in the active condition (ready to transmit), the HDLC bus controller monitors the bus using CTS. It counts the one bits on CTS. When eight consecutive ones are counted, the HDLC bus controller starts transmitting on the line; if a zero is detected, the internal counter is cleared. During transmission, data is continuously compared with the external bus using CTS. CTS is sampled halfway through the bit time using the rising edge of the Tx clock.
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SCC HDLC Mode TCLK TXD (Output) CTS (Input) CTS sampled at three quarter point. Collision detected when TXD=1, but CTS=0. Figure 22-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance 22.15.4 Delayed RTS Mode Figure 22-14 shows local HDLC bus controllers using a standard transmission line and a local bus. The controllers do not communicate with each other but with a station on the transmission line; yet the HDLC bus protocol controls access to the transmission line. + 3.
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SCC HDLC Mode Collision TCLK TXD 1st Bit 2nd Bit 3rd Bit CTS RTS RTS active for only 2 bit times Figure 22-15. Delayed RTS Mode 22.15.5 Using the Time-Slot Assigner (TSA) HDLC bus controllers can be used with a time-division multiplexed transmission line and a local bus, as shown in Figure 22-16. Local stations use time slots to communicate over the TDM transmission line; stations that share a time slot use the HDLC bus protocol to control access to the local bus. + 3.
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SCC HDLC Mode 22.15.6 HDLC Bus Protocol Programming The HDLC bus on the PowerQUICC II is implemented using the SCC in HDLC mode with bus-specific options selected in the PSMR and GSMR, as outlined below. See also Section 22.5, “Programming the SCC in HDLC Mode.” 22.15.6.
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Chapter 23 SCC BISYNC Mode The byte-oriented BISYNC protocol was developed by IBM for use in networking products. There are three classes of BISYNC frames—transparent, nontransparent with header, and nontransparent without header, shown in Figure 23-1. The transparent frame type in BISYNC is not related to transparent mode, discussed in Chapter 24, “SCC Transparent Mode.” Transparent BISYNC mode allows full binary data to be sent with any possible character pattern.
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SCC BISYNC Mode 23.
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SCC BISYNC Mode 23.3 SCC BISYNC Channel Frame Reception Although the receiver is designed to work with almost no core intervention, the user can intervene on a per-byte basis if necessary. The receiver performs CRC16, longitudinal (LRC) or vertical redundancy (VRC) checking, sync stripping in normal mode, DLE-sync stripping, stripping of the first DLE in DLE-DLE pairs in transparent mode, and control character recognition. Control characters are discussed in Section 23.
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SCC BISYNC Mode Table 23-1. SCC BISYNC Parameter RAM Memory Map Offset 1 Name Width 0x40 BDLE Hword BISYNC DLE register. Contains the value to be sent as the first byte of a DLE–SYNC pair and stripped on receive. See Section 23.8, “SCC BISYNC DLE Register (BDLE).” 0x42 0x44 CHARACTER1 Hword Control character 1–8. These values represent control characters that the BISYNC controller recognizes. See Section 23.6, “SCC BISYNC Control CHARACTER2 Hword Character Recognition.
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SCC BISYNC Mode Table 23-2. Transmit Commands Command Description STOP TRANSMIT After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit enable mode and starts polling the first BD every 64 transmit clocks. This command stops transmission after a maximum of 64 additional bits without waiting for the end of the buffer and the transmit FIFO to be flushed. TBPTR is not advanced, no new BD is accessed, and no new buffers are sent for this channel.
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SCC BISYNC Mode The control character table lets the BISYNC controller recognize the end of the current block. Because the controller imposes no restrictions on the format of BISYNC blocks, software must respond to received characters and inform the controller of mode changes and of certain protocol events, such as resetting the BCS. Using the control character table correctly allows the remainder of the block to be received without interrupting software.
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SCC BISYNC Mode Table 23-4. Control Character Table and RCCM Field Descriptions Offset Bit Name Description 0x42– 0x50 0 E End of table. 0 This entry is valid. The lower eight bits are checked against the incoming character. In tables with eight control characters, E should be zero in all eight positions. 1 The entry is not valid. No other valid entries exist beyond this entry. 1 B BCS expected. A maskable interrupt is generated after the buffer is closed.
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SCC BISYNC Mode Table 23-5. BSYNC Field Descriptions Bits Name Description 0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1 DIS 2–7 — 8–15 23.8 Disable BSYNC stripping 0 Normal mode. 1 BSYNC stripping disabled (BISYNC transparent mode only). All zeros SYNC SYNC character SCC BISYNC DLE Register (BDLE) Seen in Figure 23-4, the BDLE register is used to define the BISYNC stripping and insertion of DLE characters.
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SCC BISYNC Mode Table 23-6. BDLE Field Descriptions Bits Name Description 0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1 DIS Disable DLE stripping 0 Normal mode. 1 DLE stripping disabled. When DIS is enabled in BDLE and on BSYNC the following cases occur: DLE-DLE sequence. Both characters are written to the memory. The BCS is calculated only on the second DLE. DLE-SYNC sequence.
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SCC BISYNC Mode Table 23-8. Transmit Errors Error Description Transmitter Underrun The channel stops sending the buffer, closes it, sets TxBD[UN], and generates aTXE interrupt if it is enabled. The channel resumes transmission after a RESTART TRANSMIT command is received. Underrun cannot occur between frames or during a DLE–XXX pair in transparent mode. CTS Lost during The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if not masked.
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SCC BISYNC Mode Table 23-10. PSMR Field Descriptions Bits Name Description 0–3 NOS Minimum number of SYN1–SYN2 pairs (defined in DSR) sent between or before messages.If NOS = 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless of how GSMR[SYNL) is set. NOS can be modified on-the-fly. 4–5 CRC CRC selection. x0 Reserved. 01 CRC16 (BISYNC). X16 + X15 + X2 + 1. PRCRC and PTCRC should be initialized to all zeros or all ones before the channel is enabled.
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SCC BISYNC Mode Table 23-10. PSMR Field Descriptions (continued) Bits Name Description 12–13 RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be modified on-the-fly and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled but can be ignored. 00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is set to ensure an odd number. An even sum indicates a transmission error. 01 Low parity.
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SCC BISYNC Mode Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions (continued) Bits Name Description 2 W Wrap (last BD in table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to. The number of BDs in this table is determined by the W bit and by overall space constraints of the dual-port RAM. 3 I Interrupt. 0 No interrupt is generated after this buffer is used.
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SCC BISYNC Mode 23.13 SCC BISYNC Transmit BD (TxBD) The CP arranges data to be sent on an SCC channel in buffers referenced by the channel TxBD table. The CP uses BDs to confirm transmission or indicate errors so the core knows buffers have been serviced. The user configures status and control bits before transmission, but the CP sets them after the buffer is sent.
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SCC BISYNC Mode Table 23-12. SCC BISYNC TxBD Status and Control Field Descriptions (continued) Bits Name Description 7 BR BCS reset. Determines whether transmitter BCS accumulation is reset before sending the data buffer. 0 BCS accumulation is not reset. 1 BCS accumulation is reset before sending the data buffer. 8 TD Transmit DLE. 0 No automatic DLE transmission can occur before the data buffer.
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SCC BISYNC Mode 0 2 Field 3 4 — 5 6 DCC Reset 7 8 — 9 GRA 10 11 — 12 13 TXE RCH BSY 14 15 TXB RXB 0000_0000_0000_0000 R/W R/W Addr 0x0x11A10 (SCCE1); 0x0x11A30 (SCCE2); 0x0x11A50 (SCCE3); 0x0x11A70 (SCCE4) 0x0x11A14 (SCCM1); 0x0x11A34 (SCCM2); 0x0x11A54 (SCCM3); 0x0x11A74 (SCCM4) Figure 23-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) Table 23-13 describes SCCE and SCCM fields. Table 23-13.
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SCC BISYNC Mode Table 23-14. SCCS Field Descriptions Bit Name Description 0–5 — Reserved, should be cleared. 6 CS Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL. 0 The DPLL does not sense a carrier. 1 The DPLL senses a carrier. 7 — Reserved, should be cleared. 23.16 Programming the SCC BISYNC Controller Software has two ways to handle data received by the BISYNC controller.
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SCC BISYNC Mode Table 23-15. Control Characters Control Characters E B H ETX 0 1 1 ITB 0 1 0 ETB 0 1 1 ENQ 0 0 0 Next entry 0 X X After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be entered when a line turnaround occurs. ENQ characters are used to stop sending a block and to designate the end of the block for a receiver, but no CRC is expected. After control character reception, set SCCM[RCH] to reenable interrupts for each byte of data received. 23.
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SCC BISYNC Mode 17. Write CHARACTER2–8 with 0x8000. They are not used. 18. Write RCCM with 0xE0FF. It is not used. 19. Initialize the RxBD and assume the data buffer is at 0x00001000 in main memory. Then write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x00001000 to RxBD[Buffer Pointer]. 20. Initialize the TxBD and assume the Tx data buffer is at 0x00002000 in main memory and contains five 8-bit characters.
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SCC BISYNC Mode MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 24 SCC Transparent Mode Transparent mode (also called totally transparent or promiscuous mode) provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. Software implements protocols run over transparent mode. An SCC in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter.
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SCC Transparent Mode 24.2 SCC Transparent Channel Frame Transmission Process The transparent transmitter is designed to work almost no intervention from the core. When the core enables the SCC transmitter in transparent mode, it starts sending idles, which are logic high or encoded ones, as programmed in GSMR_L[TEND]. The SCC polls the first BD in the TxBD table.
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SCC Transparent Mode 24.4 Achieving Synchronization in Transparent Mode Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and the transmit FIFO is preloaded by the SDMA channel, another process must occur before data can be sent. It is called transmit synchronization. Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and the RxBD is made empty for the SCC, receive synchronization must occur before data can be received.
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SCC Transparent Mode frame. Pulse operation allows an uninterrupted stream of data. However, use envelope mode to identify frames of transparent data. The sampling option determines the delay between CD and CTS being asserted and the resulting action by the SCC. Assume either that these signals are asynchronous to the data and internally synchronized by the SCC or that they are synchronous to the data with faster operation.
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SCC Transparent Mode 24.4.1.3 Transparent Mode without Explicit Synchronization If there is no need to synchronize the transparent controller at a specific point, the user can ‘fake’ synchronization in one of the following ways: • Tie a parallel I/O pin to the CTS and CD lines. Then, after enabling the receiver and transmitter, provide a falling edge by manipulating the I/O pin in software.
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SCC Transparent Mode 24.5 CRC Calculation in Transparent Mode The CRC calculations follow the ITU/IEEE standard. The CRC is calculated on the transmitted data stream; that is, from lsb to msb for non-bit-reversed (GSMR_H[REVD] = 0) and from msb to lsb for bit-reversed (GSMR_H[REVD] = 1) transmission. The appended CRC is sent msb to lsb. When receiving, the CRC is calculated as the incoming bits arrive.
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SCC Transparent Mode Table 24-3. Transmit Commands (continued) Command RESTART TRANSMIT INIT TX PARAMETERS Description Reenables transmission of characters on the transmit channel. The transparent controller expects it after a STOP TRANSMIT command is issued (at which point the channel is disabled in SCCM), after a GRACEFUL STOP TRANSMIT command is issued, or after a transmitter error. The transparent controller resumes transmission from the current TBPTR in the channel TxBD table.
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SCC Transparent Mode Table 24-6. Receive Errors Error Description Overrun The SCC maintains a receive FIFO. The CPM starts programming the SDMA channel if the buffer is in external memory and updating the CRC when 8 or 32 bits are received in the FIFO as determined by GSMR_H[RFW]. If a FIFO overrun occurs, the SCC writes the received byte over the previously received byte. The previous character and its status bits are lost.
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SCC Transparent Mode Table 24-7. SCC Transparent RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty. 0 The buffer is full or stopped receiving data because an error occurred. The core can read or write to any fields of this RxBD. The CPM does not use this BD when RxBD[E] is zero. 1 The buffer is not full. This RxBD and buffer are owned by the CPM. Once E is set, the core should not write any fields of this RxBD. 1 — Reserved, should be cleared.
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SCC Transparent Mode Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” The Rx buffer pointer must be divisible by four, unless GSMR_H[RFW] is set to 8 bits wide, in which case the pointer can be even or odd. The buffer can reside in internal or external memory. 24.11 SCC Transparent Transmit Buffer Descriptor (TxBD) Data is sent to the CPM for transmission on an SCC channel by arranging it in buffers referenced by the TxBD table.
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SCC Transparent Mode Table 24-8. SCC Transparent TxBD Status and Control Field Descriptions (continued) (continued) Bit Name Description 6 CM Continuous mode. 0 Normal operation. 1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent when the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during transmission, regardless of how CM is set. 7–13 — Reserved, should be cleared. 14 UN Underrun.
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SCC Transparent Mode Table 24-9. SCCE/SCCM Field Descriptions (continued)1 1 Bit Name Description 8 GRA Graceful stop complete. Set when a graceful stop initiated by completes as soon as the transmitter finishes any frame in progress when the GRACEFUL STOP TRANSMIT command was issued. Immediately if no frame was in progress when the command was issued. 9–10 — 11 TXE 12 — 13 BSY Busy condition. Set when a byte or word is received and discarded due to a lack of buffers.
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SCC Transparent Mode The transmit and receive clocks are externally provided to PowerQUICC II(B) using CLK3. SCC2 is used. The transparent controller is configured with the RTS2 and CD2 pins active and CTS2 is configured to be grounded internally. A 16-bit CRC-CCITT is sent with each transparent frame. The FIFOs are configured for fast operation. 1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2.
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SCC Transparent Mode NOTE After 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 25 SCC Ethernet Mode The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted. Figure 25-1 shows Ethernet and IEEE 802.3 frame structure.
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SCC Ethernet Mode Random No. 60x Bus Control Registers Peripheral Bus Slot Time and Defer Counter RCLK Clock Generator TCLK Internal Clocks REJECT Receiver Control Unit RSTRT CD = RENA Rx Data FIFO Tx Data FIFO RTS = TENA Transmitter Control Unit CD = RENA CTS = CLSN CTS = CLSN RXD Shifter Shifter TXD Figure 25-2. Ethernet Block Diagram The PowerQUICC II Ethernet controller requires an external serial interface adaptor (SIA) and transceiver function to complete the interface to the media.
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SCC Ethernet Mode • • • • • • • • • • • • • — Two nonaggressive backoff modes — Automatic frame retransmission (until the attempt limit is reached) — Automatic discard of incoming collided frames — Delay transmission of new frames for specified interframe gap Maximum 10 Mbps bit rate Optional full-duplex support Back-to-back frame reception Detection of receive frames that are too long Multibuffer data structure Supports 48-bit addresses in three modes — Physical: One 48-bit address recognized or 64-b
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SCC Ethernet Mode 25.3 Connecting the PowerQUICC II to Ethernet The basic interface to the external SIA chip consists of the following Ethernet signals: • Receive clock (RCLK)—a CLKx signal routed through the bank of clocks on the PowerQUICC II. • Transmit clock (TCLK)—a CLKx signal routed through the bank of clocks on the PowerQUICC II. Note that RCLK and TCLK should not be connected to the same CLKx since the SIA provides separate transmit and receive clock signals.
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SCC Ethernet Mode connect to AUI or twisted-pair media are external to the EEST. The MC68160 documentation describes EEST connection circuits. The PowerQUICC II uses SDMA channels to store bytes received after the start frame delimiter in system memory. When sending, provide the destination address, source address, type/length field, and the transmit data. To meet minimum frame requirements, the PowerQUICC II pads frames with fewer than 46 bytes in the data field and appends the FCS to the frame. 25.
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SCC Ethernet Mode 25.5 SCC Ethernet Channel Frame Reception The Ethernet receiver handles address recognition and performs CRC, short frame, maximum DMA transfer, and maximum frame length checking with almost no core intervention. When the core enables the Ethernet receiver, it enters hunt mode as soon as RENA is asserted while CLSN is negated.
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SCC Ethernet Mode generate writes to the CAM for address recognition. In addition, the RENA signal supplied from the SIA can be used to abort the comparison if a collision occurs on the receive frame. After the comparison, the CAM control logic asserts the receive reject signal (REJECT), if the current receive frame is rejected. The PowerQUICC II’s Ethernet controller then immediately stops writing data to system memory and reuses the buffer(s) for the next frame.
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SCC Ethernet Mode Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued) Offset 1 Name 0x4C MINFLR Hword Minimum frame length register. The Ethernet controller checks the incoming frame’s length against MINFLR (typically 64 decimal). If the received frame is smaller than MINFLR, it is discarded unless PSMR[RSH] is set, in which case, SH is set in the last BD for the frame.
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SCC Ethernet Mode Table 25-1. SCC Ethernet Parameter RAM Memory Map (continued) Offset 1 Name 0x7C TFBD_PTR Hword Tx first BD pointer. 0x7E TLBD_PTR Hword Tx last BD pointer. 0x80 TBUF1_DATA0 Word Save area 0—next frame. 0x84 TBUF1_DATA1 Word Save area 1—next frame. 0x88 TBUF1_RBA0 Word 0x8C TBUF1_CRC Word 0x90 TBUF1_BCNT Hword 0x92 TX_LEN Hword Tx frame length counter. 0x94 IADDR1 0x96 IADDR2 0x98 IADDR3 Hword Individual address filter 1–4.
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SCC Ethernet Mode Table 25-2. Transmit Commands Command STOP TRANSMIT GRACEFUL STOP TRANSMIT RESTART TRANSMIT INIT TX PARAMETERS Description When used with the Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE 802.3 station. It should not be used. Used to ensure that transmission stops smoothly after the current frame finishes or has a collision. SCCE[GRA] is set once transmission stops, at which point Ethernet transmit parameters and their BDs can be updated.
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SCC Ethernet Mode 25.10 SCC Ethernet Address Recognition The Ethernet controller can filter received frames based on different addressing types—physical (individual), group (multicast), broadcast (all-ones group address), and promiscuous. The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames is shown in Figure 25-4.
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SCC Ethernet Mode address, address recognition can be performed on multiple group addresses using the GADDRn hash table. In promiscuous mode, the controller receives all incoming frames regardless of their address, unless REJECT is asserted. If an external CAM is used for address recognition, select promiscuous mode; the frame can be rejected by asserting REJECT while the frame is being received.
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SCC Ethernet Mode If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits a random number of slot times (512 bit times or 52 µs). If a collision occurs after 64 byte times, no retransmission is performed and the buffer is closed with an LC error indication. If a collision occurs while a frame is being received, reception stops. This error is reported only in the BD if the length of the frame exceeds MINFLR or if PSMR[RSH] = 1. 25.
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SCC Ethernet Mode Table 25-4. Transmission Errors (continued) Error Description Late collision When this error occurs, the channel stops sending the buffer, closes it, sets SCCE[TXE] and the LC bit in the TxBD. The channel resumes transmission after it receives the RESTART TRANSMIT command. This error is discussed further in the definition of PSMR[LCW]. Heartbeat Some transceivers have a heartbeat (signal-quality error) self-test.
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SCC Ethernet Mode Table 25-6. PSMR Field Descriptions Bits Name Description 0 HBC Heartbeat checking. 0 No heartbeat checking is performed. Do not wait for a collision after transmission. 1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission. The HB bit in the TxBD is set if the heartbeat is not heard within 20 transmit clocks. 1 FC Force collision. 0 Normal operation. 1 The channel forces a collision when each frame is sent.
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SCC Ethernet Mode Table 25-6. PSMR Field Descriptions Bits Name Description 12–14 NIB Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should begin looking for the start frame delimiter. Typically NIB = 101 (22 bits). 000 Begin searching 13 bits after the assertion of RENA. 001 Begin searching 14 bits after the assertion of RENA. ... 111 Begin searching 24 bits after the assertion of RENA. 15 FDE Full duplex Ethernet. 0 Disable full-duplex Ethernet mode.
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SCC Ethernet Mode Table 25-7. SCC Ethernet RxBD Status and Control Field Descriptions (continued) Bits Name Description 4 L Last in frame. The Ethernet controller sets this bit when this buffer is the last one in a frame, which occurs when the end of a frame is reached or an error is received. In the case of error, one or more of the CL, OV, CR, SH, NO, and LG bits are set. The Ethernet controller writes the number of frame octets to the data length field. 0 The buffer is not the last one in a frame.
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SCC Ethernet Mode E Status 0 MRBLR = 64 Bytes for this SCC Buffer Receive BD 0 L F 0 1 Destination Address (6) Length 0x0040 Source Address (6) Pointer 32-Bit Buffer Pointer Buffer Full 64 Bytes Type/Length (2) Data Bytes (50) E Status 0 Receive BD 1 L F 1 Buffer 0 Length 0x0045 Pointer 32-Bit Buffer Pointer CRC Bytes (4) Buffer Closed after CRC Received.
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SCC Ethernet Mode Offset + 0 0 1 2 3 4 5 6 7 8 9 R PAD W I L TC DEF HB LC RL Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer 10 13 RC 14 15 UN CSL Offset + 6 Figure 25-8. SCC Ethernet TxBD Table 25-8 describes TxBD status and control fields. Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions Bits Name Description 0 R Ready. 0 The buffer is not ready for transmission. The user can update this BD or its data buffer.
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SCC Ethernet Mode Table 25-8. SCC Ethernet TxBD Status and Control Field Descriptions (continued) Bits Name Description 10–13 RC Retry count. Indicates the number of retries required before the frame was sent successfully. If RC = 0, the frame was sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15 retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then 15 or more retries were required.
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SCC Ethernet Mode Table 25-9. SCCE/SCCM Field Descriptions (continued) Bits Name Description 14 TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel. 15 RXB Rx buffer. Set when a buffer that was not a complete frame was received on the Ethernet channel. Figure 25-10 shows an example of interrupts that can be generated in Ethernet protocol.
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SCC Ethernet Mode 25.21 SCC Ethernet Programming Example The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin is used for the Ethernet receiver and CLK4 is used for the transmitter. 1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2. Configure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and RENA2 (CD2).
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SCC Ethernet Mode 23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing 0xFFFF_FFFF to it. 24. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes. 25. Write 0x1088_000C to the GSMR_L2 register to configure CTS (CLSN) and CD (RENA) to automatically control transmission and reception (DIAG bits) and the Ethernet mode.
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SCC Ethernet Mode MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 26 SCC AppleTalk Mode AppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers. Although AppleTalk can be implemented over a variety of physical and link layers, including Ethernet, AppleTalk protocols have been most closely associated with the LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps.
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SCC AppleTalk Mode RTS pin) is sent to request the network, a CTS frame is sent by the destination node, and the data frame is sent by the requesting node. These three frames comprise one possible type of dialog. After a dialog begins, other nodes cannot start sending until the dialog is complete. Frames within a dialog are sent with a maximum interframe gap (IFG) of 200 µs. Although the LocalTalk specification does not state it, there is also a minimum recommended IFG of 50 µs.
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SCC AppleTalk Mode PowerQUICC II RS-422 SCC TXD RTS RXD MINI-DIN 8 Connection Tx Data Tx Enable Rx Data Stored in Receive Buffer Stored in Transmit Buffer TXD 6-Bit Sync Two HDLC Destination Source Sequence Flags Address Address Control Byte Data CRC-16 Closing Flag 16 Ones (Abort) RTS Standard HDLC frame handling Figure 26-2. Connecting the PowerQUICC II to LocalTalk The 16× overspeed of a 3.
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SCC AppleTalk Mode 8. Clear TINV and RINV so data will not be inverted. 9. Set TSNC to 1.5 bit times (0b10). 10. Clear EDGE. Both the positive and negative edges are used to change the sample point (default). 11. Clear RTSM (default). 12. Set all other bits to zero or default. 13. Set ENT and ENR as the last step to begin operation. 26.4.2 Programming the PSMR Follow these steps to program the protocol-specific mode register: 1.
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Chapter 27 Serial Management Controllers (SMCs) The two serial management controllers (SMCs) are full-duplex ports that can be configured independently to support one of three protocols or modes—UART, transparent, or general-circuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in an application, which allows the SCCs to be free for other purposes. The SMC in UART mode is not as complex as that of the SCC in UART mode.
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Serial Management Controllers (SMCs) The receive data source can be L1RXD if the SMC is connected to a TDM channel of an SIx, or SMRXD if it is connected to the NMSI. The transmit data source can be L1TXD if the SMC is connected to a TDM or SMTXD if it is connected to the NMSI. If the SMC is connected to a TDM, the SMC receive and transmit clocks can be independent from each other, as defined in Chapter 15, “Serial Interface with Time-Slot Assigner.
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Serial Management Controllers (SMCs) Bit 0 Field: UART — 1 2 3 4 5 6 7 SL PEN PM Transparent — BS REVD GCI ME — C# CLEN Reset 8 9 — 10 11 SM 12 13 DM 14 15 TEN REN 0000_0000_0000_0000 R/W R/W Addr 0x0x11A82 (SMCMR1), 0x0x11A92 (SMCMR2) Figure 27-2. SMC Mode Registers (SMCMR1/SMCMR2) Table 27-1 describes SMCMR fields. Table 27-1. SMCMR1/SMCMR2 Field Descriptions Bits Name 0 — 1–4 CLEN Description Reserved, should be cleared Character length (UART).
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Serial Management Controllers (SMCs) Table 27-1. SMCMR1/SMCMR2 Field Descriptions (continued) Bits Name 6 PEN 7 Description Parity enable. (UART) 0 No parity. 1 Parity is enabled for the transmitter and receiver as determined by the PM bit. BS Byte sequence(transparent). Controls the byte transmission sequence if REVD is set for a character length greater than 8 bits. Clear BS to maintain behavior compatibility with MC68360 QUICC. 0 Normal mode.
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Serial Management Controllers (SMCs) Dual-Port RAM External Memory TxBD Table Status and Control Data Length SMC TxBD Table Buffer Pointer Tx Data Buffer RxBD Table Status and Control SMC RxBD Table Data Length Buffer Pointer Rx Data Buffer Pointer to SMCx RxBD Table Pointer to SMCx TxBD Table Figure 27-3. SMC Memory Structure The BD table allows buffers to be defined for transmission and reception. Each table forms a circular queue.
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Serial Management Controllers (SMCs) Table 27-2. SMC UART and Transparent Parameter RAM Memory Map Offset 1 Name Width Description 0x00 RBASE 0x02 TBASE 0x04 RFCR Byte 0x05 TFCR Byte 0x06 MRBLR Hword Maximum receive buffer length. The most bytes the PowerQUICC II writes to a receive buffer before moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error or end-of-frame occurs, but it cannot exceed MRBLR.
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Serial Management Controllers (SMCs) Table 27-2. SMC UART and Transparent Parameter RAM Memory Map (continued) Offset 1 2 1 Name Width 0x24 — Word 0x28 MAX_IDL Hword Maximum idle characters. (UART protocol-specific parameter) When a character is received on the line, the SMC starts counting idle characters received.
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Serial Management Controllers (SMCs) 27.2.3.1 SMC Function Code Registers (RFCR/TFCR) The function code registers contain the transaction specification associated with SDMA channel accesses to external memory. Figure 27-4 shows the register format. 0 1 2 Field 3 GBL 4 BO 5 6 7 TC2 DTB — R/W R/W Addr SMC base + 0x04 (RFCR)/SMC base + 0x05 (TFCR) Figure 27-4. SMC Function Code Registers (RFCR/TFCR) Table 27-3 describes FCR fields. Table 27-3.
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Serial Management Controllers (SMCs) 27.2.4.1 SMC Transmitter Full Sequence Follow these steps to fully enable or disable the SMC transmitter: 1. If the SMC is sending data, issue a STOP TRANSMIT command to stop transmission smoothly. If the SMC is not sending, if TBPTR is overwritten, or if an INIT TX PARAMETERS command is executed, this command is not required. 2. Clear SMCMR[TEN] to disable the SMC transmitter and put it in reset state. 3. Update SMC transmit parameters, including the parameter RAM.
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Serial Management Controllers (SMCs) 2. Issue an INIT TX AND RX PARAMETERS COMMAND to initialize transmit and receive parameters. Make any additional SMCMR changes. 3. Set SMCMR[REN, TEN]. The SMC is now enabled with the new protocol. 27.2.5 Saving Power When SMCMR[TEN, REN] are cleared, the SMC consumes little power. 27.2.6 Handling Interrupts in the SMC Follow these steps to handle an interrupt in the SMC: 1. Once an interrupt occurs, read SMCE to identify the interrupt source.
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Serial Management Controllers (SMCs) 27.3.1 Features The following list summarizes the main features of the SMC in UART mode: • Flexible message-oriented data structure • Programmable data length (5–14 bits) • Programmable 1 or 2 stop bits • Even/odd/no parity generation and checking • Frame error, break, and idle detection • Transmit preamble and break sequences • Received break character length indication • Continuous receive and transmit modes 27.3.
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Serial Management Controllers (SMCs) errors are reported via the BDs. At its simplest, the SMC UART controller functions in a character-oriented environment, whereas each character is sent with the selected stop bits and parity. They are received into separate 1-byte buffers. A maskable interrupt can be generated when each buffer is received. Many applications can take advantage of the message-oriented capabilities that the SMC UART supports through linked buffers for sending or receiving.
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Serial Management Controllers (SMCs) number of break characters according to BRKCR and then reverts to idle or sends data if a RESTART TRANSMIT is issued before completion. When the break completes, the transmitter sends at least one idle character before sending any data to guarantee recognition of a valid start bit. 27.3.7 Sending a Preamble A preamble sequence provides a way to ensure that the line is idle before a new message transfer begins.
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Serial Management Controllers (SMCs) • A programmable number of consecutive idle characters are received Figure 27-6 shows the format of the SMC UART RxBD. Offset + 0 0 1 2 3 E — W I 4 5 — 6 7 CM ID 8 9 — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer 10 11 12 13 14 15 BR FR PR — OV — Offset + 6 Figure 27-6. SMC UART RxBD Table 27-7 describes RxBD fields. Table 27-7. SMC UART RxBD Field Descriptions Bit Name Description 0 E Empty.
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Serial Management Controllers (SMCs) Table 27-7. SMC UART RxBD Field Descriptions (continued) Bit Name Description 12 PR Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new buffer is used for additional data. The CP writes PR after received data is in the buffer. 13 — Reserved, should be cleared. 14 OV Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received data is in the buffer.
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Serial Management Controllers (SMCs) E Receive BD 0 ID MRBLR = 8 Bytes for this SMC Buffer 0 0 Byte 1 Length 0008 Byte 2 Pointer 32-Bit Buffer Pointer Status Buffer Full 8 Bytes etc.
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Serial Management Controllers (SMCs) 27.3.10 SMC UART TxBD Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the channel TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. An SMC UART TxBD is displayed in Figure 27-8.
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Serial Management Controllers (SMCs) to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because the three 9-bit data fields occupy three half words in memory (the 9 least-significant bits of each half word). Tx data buffer pointer points to the first location of the buffer. It can be even or odd, unless the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer must be even.
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Serial Management Controllers (SMCs) Characters Received by SMC UART 10 Characters Time RXD Line Idle Break Line Idle SMC UART SMCE Events RX RX BRK BRKE NOTES: 1. The first RX event assumes receive buffers are 6 bytes each. 2. The second RX event position is programmable based on the MAX_IDL value. 3. The BRK event occurs after the first break character is received. Characters Transmitted by SMC UART TXD SMC UART SMCE Events 7 Characters Line Idle Line Idle TX NOTES: 1.
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Serial Management Controllers (SMCs) 12. Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (not required), and 0x0000_1000 to RxBD[Buffer Pointer]. 13. Assuming the Tx data buffer is at 0x0000_2000 in main memory and contains five 8-bit characters, write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 14.
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Serial Management Controllers (SMCs) • • • • • Transmits and receives transparently on its own set of signals using a sync signal to synchronize the beginning of transmission and reception to an external event Programmable character length (4–16) Reverse data mode Continuous transmission and reception modes Four commands 27.4.2 SMC Transparent Channel Transmission Process The transparent transmitter is designed to work with almost no core intervention.
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Serial Management Controllers (SMCs) SMC continues transferring data to this BD’s buffer. If the CM bit is set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the buffer on its next access. 27.4.4 Using SMSYN for Synchronization The SMSYN signal offers a way to externally synchronize the SMC channel. This method differs somewhat from the synchronization options available in the SCCs and should be studied carefully. See Figure 27-11 for an example.
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Serial Management Controllers (SMCs) SMCLK SMSYN SMTXD 1s are sent Five 1s are sent SMC1 Transmit Data TEN set here Five 1s SMSYN Tx FIFO assume loaded detected low here approximatelycharacter length here equals 5 First bit of first 5-bit transmit character (lsb) Transmission could begin here if Tx FIFO not loaded in time SMCLK SMSYN SMRXD SMC1 Receive Data REN set SMSYN First bit here or detected of receive data enter hunt low here (lsb) mode command issued NOTES: 1.
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Serial Management Controllers (SMCs) TDM Tx CLK TDM Tx SYNC SMC1 SMC1 TDM Tx After TEN is set, transmission begins here. If SMC runs out of Tx buffers and new ones are provided later, transmission begins at the beginning of either time slot. TDM Rx CLK TDM Rx SYNC TDM Rx After REN is set or after enter hunt mode command, reception begins here. SMC1 SMC1 Figure 27-12.
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Serial Management Controllers (SMCs) describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may not be enough. 27.4.6 SMC Transparent Commands Table 27-10 describes transmit commands issued to the CPCR. Table 27-10. SMC Transparent Transmit Commands Command STOP TRANSMIT RESTART TRANSMIT INIT TX PARAMETERS Description After hardware or software is reset and the channel is enabled in the SMCM, the channel is in transmit enable mode and polls the first BD.
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Serial Management Controllers (SMCs) Table 27-12. SMC Transparent Error Conditions Error Descriptions Underrun The channel stops sending the buffer, closes it, sets UN in the BD, and generates a TXE interrupt if it is enabled. The channel resumes sending after a RESTART TRANSMIT command. Underrun cannot occur between frames. Overrun The SMC maintains an internal FIFO for receiving data.
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Serial Management Controllers (SMCs) Table 27-13. SMC Transparent RxBD Field Descriptions (continued) Bits Name Description 3 I Interrupt. 0 No interrupt is generated after this buffer is filled. 1 SMCE[RXB] is set when the CP completely fills this buffer indicating that the core must process the buffer. The RXB bit can cause an interrupt if it is enabled. 4–5 — Reserved, should be cleared. 6 CM Continuous mode. 0 Normal operation.
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Serial Management Controllers (SMCs) Table 27-15. SMC Transparent TxBD Field Descriptions Bits Name Description 2 W Wrap (final BD in table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that TBASE points to. The number of TxBDs in this table is programmable and determined by theW bit and overall space constraints of the dual-port RAM. 3 I Interrupt. 0 No interrupt is generated after this buffer is serviced.
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Serial Management Controllers (SMCs) 0 1 Field 2 — Reset 3 4 5 6 7 TXE — BSY TXB RXB 0 R/W R/W Addr 0x0x11A86 (SMCE1), 0x0x11A96 (SMCE2)/ 0x0x11A8A (SMCM1), 0x0x11A9A (SMCM2) Figure 27-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM) Table 27-16 describes SMCE/SMCM fields. Table 27-16. SMCE/SMCM Field Descriptions Bits Name 0–2 — 3 TXE 4 — 5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers.
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Serial Management Controllers (SMCs) 8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes MRBLR = 0x0010. 9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 10. Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters.
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Serial Management Controllers (SMCs) Table 27-17. SMC GCI Parameter RAM Memory Map Offset 1 Name Width 0x00 M_RxBD Half word Monitor channel RxBD. See Section 27.5.5, “SMC GCI Monitor Channel RxBD.” 0x02 M_TxBD Half word Monitor channel TxBD. See Section 27.5.6, “SMC GCI Monitor Channel TxBD.” 0x04 CI_RxB D Half word C/I channel RxBD. See Section 27.5.7, “SMC GCI C/I Channel RxBD.” 0x06 CI_TxB D Half word C/I channel TxBD. See Section 27.5.8, “SMC GCI C/I Channel TxBD.
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Serial Management Controllers (SMCs) 27.5.3 Handling the GCI C/I Channel The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends commands and receives indication to or from the upstream layer 1 device through C/I channel 0. In the SCIT configuration, C/I channel 1 is used to convey real-time status information between the layer 2 device and nonlayer 1 peripheral devices (CODECs). 27.5.3.
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Serial Management Controllers (SMCs) Table 27-19. SMC Monitor Channel RxBD Field Descriptions Bits Name 0 E Empty. 0 The CP clears E when the byte associated with this BD is available to the core. 1 The core sets E when the byte associated with this BD has been read. 1 L Last (EOM). Valid only for monitor channel protocol and is set when the EOM indication is received on the E bit. Note that when this bit is set, the data byte is invalid. 2 ER Error condition.
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Serial Management Controllers (SMCs) 0 Offset + 0 1 7 E 8 13 — 14 C/I DATA 15 — Figure 27-17. SMC C/I Channel RxBD Table 27-21 describes SMC C/I channel RxBD fields. Table 27-21. SMC C/I Channel RxBD Field Descriptions Bits Name 0 E Empty. 0 Cleared by the CP to indicate that the byte associated with this BD is available to the core. 1 The core sets E to indicate that the byte associated with this BD has been read. Note that additional data received is discarded until E bit is set.
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Serial Management Controllers (SMCs) the internal interrupt request to the SIU interrupt controller. Figure 27-19 displays the SMCE/SMCM registers. 0 1 Field 2 3 — Reset 4 5 6 7 CTXB CRXB MTXB MRXB 0000_0000 R/W R/W Addr 0x0x11A86 (SMCE1), 0x0x11A96 (SMCE2)/ 0x0x11A8A (SMCM1), 0x0x11A9A (SMCM2) Figure 27-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM) Table 27-23 describes SMCE/SMCM fields. Table 27-23.
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Serial Management Controllers (SMCs) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 28 Multi-Channel Controllers (MCCs) NOTE The MPC8250 and the MPC8255 have only one MCC. The signalling system #7 (SS7) functionality described in this chapter is not available on rev A.1 .29µm (HiP3) silicon. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. A multi-channel controller (MCC) allows the PowerQUICC II to support up to 128 separate time-division serial channels on one peripheral. The PowerQUICC II has two MCCs.
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Multi-Channel Controllers (MCCs) • • • • • • • • Efficient control of the interrupts to the core Uses external BD tables.
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Multi-Channel Controllers (MCCs) • • • • • — Section 28.3.4, “Channel-Specific SS7 Parameters” Note that the DPRAM memory corresponding to the inactive channels can be used for other purposes. Channel extra parameters. Each channel use 8 bytes of extra parameters placed in the DPRAM at offset XTRABASE + 8*CH_NUM (relative to the DPRAM base address). XTRABASE is one of the global MCC parameters. Refer to Section 28.4, “Channel Extra Parameters.
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Multi-Channel Controllers (MCCs) 28.2 Global MCC Parameters The global MCC parameters are described in Table 28-1. Table 28-1. Global MCC Parameters Offset1 Name Width Word Description 0x00 MCCBASE MCC base pointer. User-initialized parameter points to the starting address of a 512-Kbyte BD segment in external memory. 0x04 MCCSTATE Hword MCC state. Used by the CP for global state definition. Should be cleared during initialization.
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Multi-Channel Controllers (MCCs) Table 28-1. Global MCC Parameters (continued) Offset1 Name Width 0x28 C_MASK32 0x2C XTRABASE Hword Pointer the beginning of the extra parameters information, offset from the DPRAM address 0x2E C_MASK16 Hword CRC constant (user initialized to 0xF0B8). Used for 16-bit CRC-CCITT calculation if HDLC mode is chosen for a selected channel. This option is programmable. For each HDLC channel, one of two CRC-CCITT can be selected through the CHAMR.
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Multi-Channel Controllers (MCCs) Table 28-2. Channel-Specific Parameters for HDLC Offset1 Name 0x00 TSTATE Word Tx internal state. To start a transmitter channel the user must write to TSTATE 0xHH80_0000. HH is the TSTATE high byte described in Section 28.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” 0x04 ZISTATE Word Zero-insertion machine state.
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Multi-Channel Controllers (MCCs) Table 28-2. Channel-Specific Parameters for HDLC (continued) Offset1 Name Width 0x38 MFLR Hword Maximum frame length register. Defines the longest expectable frame for this channel. (64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded and the LG flag is set in the last frame’s BD. An interrupt request might be generated (RXF and RXB) depending on the interrupt mask.
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Multi-Channel Controllers (MCCs) Table 28-3. TSTATE High-Byte Field Descriptions Bits Name 6 DTB Data bus indicator. Selects the bus that handles transfers to and from data buffers. 0 60x bus SDMA 1 Local bus SDMA 7 BDB BD bus. Selects the bus that handles transfers to/from BD and interrupt circular tables. 0 60x bus SDMA used for accessing BDs 1 Local bus SDMA used for accessing BDs 28.3.1.
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Multi-Channel Controllers (MCCs) Table 28-4. CHAMR Field Descriptions Bits 0 Name Description MODE This mode bit determines whether the HDLC or transparent mode is used. It also determines how other CHAMR bits are interpreted. 0 Transparent mode. See Section 28.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.” 1 HDLC mode 1 POL Enable polling. POL enables the transmitter to poll the TxBDs. 0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).
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Multi-Channel Controllers (MCCs) Table 28-4. CHAMR Field Descriptions (continued) Bits Name 11–12 RQN Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. 13–15 NOF Number of flags. NOF defines the minimum number of flags before frames: 000 At least 1 flag 001 At least 2 flags .... 111 At least 8 flags 28.3.1.
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Multi-Channel Controllers (MCCs) Table 28-5. RSTATE High-Byte Field Descriptions (continued) Bits Name 6 DTB Data bus indicator. The transfers to data buffers are handled by the: 0 60x bus SDMA 1 Local bus SDMA 7 BDB BD and interrupt circular tables bus indicator.
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Multi-Channel Controllers (MCCs) Table 28-6. Channel-Specific Parameters for Transparent Operation (continued) Offset1 Name 0x24 ZDSTATE Width Description Word Zero-deletion machine state.
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Multi-Channel Controllers (MCCs) 28.3.2.3 Channel Mode Register (CHAMR)—Transparent Mode Figure 28-6 shows the user-initialized channel mode register, CHAMR, for transparent mode. For channels that are used in conjunction with CES functionality, the user should refer to Section 28.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information. 0 1 Field MODE POL 2 3 4 5 1 1 EP RD Reset 6 7 8 SYNC 9 — 10 TS 11 12 RQN 13 15 — — R/W R/W Offset 0x1A Figure 28-6.
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Multi-Channel Controllers (MCCs) Table 28-7. CHAMR Field Descriptions—Transparent Mode (continued) Bits Name 6–7 SYNC Description Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode. SYNC Receive Transmit Description 00 None None Transmitter and receiver operate with no synchronization algorithm. RCVSYNC should be cleared or erroneous behavior may occur.
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Multi-Channel Controllers (MCCs) 28.3.3.1 Channel-Specific Parameters—AAL1 CES The following are changes that occur in the channel-specific parameter RAM when using AAL1 CES. Table 28-8 describes the additional global MCC parameters specific to CES operation. Table 28-8. CES-Specific Global MCC Parameters Offset1 Name Width Description 0x00 CATB Hword CES adaptive threshold tables base address.
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Multi-Channel Controllers (MCCs) 0 Field MODE 1 2 3 4 5 POL 1 1 EP RD Reset 6 7 8 SYNC 9 — 10 TS 11 12 RQN 13 14 15 CESM UDC UTM — R/W R/W Offset 0x1A Figure 28-8. Channel Mode Register (CHAMR)—CES Mode The CHAMR in CES mode fields are described in Table 28-7. Table 28-9. CHAMR Field Descriptions—CES Mode Bits Name Description 0 MODE Channel mode. Selects either HDLC or transparent mode. Must be cleared for CES operation. 0 Transparent mode.
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Multi-Channel Controllers (MCCs) Table 28-9. CHAMR Field Descriptions—CES Mode (continued) Bits Name 8–9 — Reserved, should be cleared during initialization. 10 TS Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is any number larger than 0). 11–12 RQN Description Receive queue number. Specifies the receive interrupt queue number.
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Multi-Channel Controllers (MCCs) • Flow control SS7 features are as follows: • Up to 128 independent communication channels (64 channels per MCC) • Independent mapping for receive and transmit • Standard HDLC features — Flag/Abort/Idle generation/detection — Zero insertion/deletion — 16-bit CRC-CCITT generation/checking — Detection of non-octet aligned signal units — Programmable number of flags between signal units • Maintenance of signal unit error monitor (SUERM) • Maintenance of alignment error rate
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Multi-Channel Controllers (MCCs) Table 28-10. Channel-Specific Parameters for SS7 Offset1 Name2 Width Description 0x00 TSTATE Word Tx internal state. The user must write to TSTATE 0xHH80_0000. HH is the TSTATE High Byte. Refer to Section 28.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” 0x04 ZISTATE Word Zero-insertion machine state.
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Multi-Channel Controllers (MCCs) Table 28-10. Channel-Specific Parameters for SS7 (continued) Offset1 Name2 Width Description 0x38 MFLR Hword Maximum frame length register. Defines the longest expected frame for this channel. (64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded and the LG flag is set in the last frame’s BD. An interrupt request might be generated (RXF and RXB) depending on the interrupt mask.
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Multi-Channel Controllers (MCCs) Table 28-10. Channel-Specific Parameters for SS7 (continued) Offset1 Name2 Width Description 0x68 EFSUC Word Error-free signal unit counter, user initialized to 0. The counter is incremented whenever an error-free (no CRC error, no non-octet aligned error, no short or long frame errors) signal unit is received. 0x6C SUEC Word Signal unit error counter, user initialized to 0. Incremented each time an SU is received that contains an error.
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Multi-Channel Controllers (MCCs) 0 Field MODE0 1 2 3 4 5 6 7 8 — OCT SUERM FISU — UN TXB — Reset 9 10 11 12 13 14 15 AERM NID IDL MRF RXF BSY RXB No reset value R/W R/W Offset 0x18 16 17 Field MODE1 POL 18 19 1 IDLM 20 Reset 25 — 26 27 TS 28 RQN 29 31 NOF No reset value R/W R/W Offset 0x1A Figure 28-9. Extended Channel Mode Register (ECHAMR) ECHAMR fields are described in Table 28-11. Table 28-11.
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Multi-Channel Controllers (MCCs) Table 28-11. ECHAMR Fields Description (continued) Bits Name Description 19 IDLM Idle mode. 0 No idle patterns are transmitted between frames. After transmitting NOF+1 flags, the transmitter starts sending the data of the frame. If the transmission is between frames and the frame buffers are not ready, the transmitter sends flags until it can start transmitting the data received for SS7 operation. 1 At least one idle pattern is sent between adjacent frames.
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Multi-Channel Controllers (MCCs) • • • • For every JTRDelay an error flag is checked. If there is no error, decrement the counter SUERM by 1 (not below zero). If there is an error, increment the counter SUERM by D. If SUERM reaches T, the counter SUERM is cleared and a “signal unit error rate monitor” interrupt is generated. Table 28-12. Parameter Values for SUERM in Japanese SS7 Paramete r Definition Value T Threshold 285 D Upcount 16 JTRDelay Length of interval (24ms) 28.3.4.
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Multi-Channel Controllers (MCCs) Table 28-13. SS7 Configuration Register Fields Description Bits Name Description 9 SEN_FIS Send FISU if first BD of frame is not ready. 0 Flags are sent if the current BD, which is the first BD of the frame, does not have its ready bit set. 1 FISUs are automatically sent if the current BD, which is the first BD of the frame, does not have its ready bit set. 10 O_ORN Enter octet counting mode (OCM) on overrun. Should be cleared if using the Japanese standard.
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Multi-Channel Controllers (MCCs) To disable AERM and enter SUERM, do the following: 1. Set SUERM_DIS bit in SS7_OPT. 2. Set parameters (T, D & SUERM) for Japanese SUERM. 3. Clear SUERM_DIS bit in SS7_OPT. 28.3.4.3.3 Disabling SUERM When SS7_OPT[SUERM_DIS] is set, the N_cnt and D_cnt parameters are not decremented by the microcode and no SUERM interrupt is generated. This allows these parameters to be updated, for example, at the end of the proving period in alignment error monitoring.
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Multi-Channel Controllers (MCCs) • • • State 0—The first 3-5 bytes (depending on the contents of the LI field) are masked and then compared with the first 3-5 bytes of the last SU. If there is a match, go to State 1, else remain in State 0. The current SU will be received into a buffer descriptor. State 1—The first 3-5 bytes (depending on the contents of the LI field) are masked and then compared with the first 3-5 bytes of the last SU. If there is a match, go to State 2, else go to State 0.
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Multi-Channel Controllers (MCCs) 28.3.4.5 Octet Counting Mode—SS7 Mode When entering the octet counting mode (OCM), the CP will load the user defined N register to its internal octet counter. While in the octet counting mode the CP will decrement its internal counter for every unstuffed octet received. When the internal counter is decremented to zero, the CP increment the SUERM register and reload the N register into the internal count register.
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Multi-Channel Controllers (MCCs) 28.5 Superchannels A TDM may not be programmed to contiguously transmit more than one byte of data from the same MCC channel. This is true whether the user wants to program more than one byte in the same SI entry or have back-to-back SI entries for the same channel. Instead, superchannelling is used to achieve sending multiple back-to-back bytes from the same MCC channel. Refer to Section 15.4.
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Multi-Channel Controllers (MCCs) 28.5.2 Superchannels and Receiving The restrictions stated in Section 28.5 regarding using back-to-back timeslots with the same channel do not apply to the receive side of the MCC. A user does not have to mark receive timeslots as superchannelled in SIRAM programming unless transparent slot synchronization is being used (see Section 28.5.3, “Transparent Slot Synchronization”).
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Multi-Channel Controllers (MCCs) SI RAM 0 MCC 1 2 LOOP SUPER Super Channel Table 3–10 11–13 14 15 MCSEL CNT BYT LST 0–1 1 10–15 CHANNEL NO SI RAM Address 2 2–9 DPRAM_Base + SCTPBASE + 1 0 0 0x0 0x0 1 0 0x0 — 1 0 1 0x1 0x01 1 0 0x2 0x1 1 0 1 0x2 0x01 1 0 0x4 0x2 1 0 1 0x3 0x72 0 0 0x6 0x2 1 0 1 0x4 0x72 0 0 0x8 0x2 1 0 0 0x5 0x0 1 0 0xA — 1 0 1 0x6 0x72 0 0 0xC 0x1 1 0 1 0x7 0x72 0 0 0xE 0x1 1 0 0 0x8 0x0 1 1
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Multi-Channel Controllers (MCCs) of the managing MCC channel for that superchannel (the same MCC channel number used in the superchannel table entries corresponding to the transmit FIFOs for that superchannel).
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Multi-Channel Controllers (MCCs) SI RAM 0 1 MCC 2 LOOP SUPER 3–10 11–13 14 15 MCSEL CNT BYT LST SI RAM Address 1 0 0 0x0 0x0 1 0 Regular Channel 1 0 0 0x1 0x0 1 0 Super Channel 1 1 0 0 0x2 0x0 1 0 Super Channel 2 1 0 0 0x2 0x0 1 0 Super Channel 2 1 0 0 0x2 0x0 1 0 Super Channel 2 1 0 0 0x5 0x0 1 0 Regular Channel 1 0 0 0x1 0x0 1 0 Super Channel 1 1 0 0 0x1 0x0 1 0 Super Channel 1 1 0 0 0x8 0x0 1 1 Regular Channel The super
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Multi-Channel Controllers (MCCs) Table 28-16 describes group assignments. Table 28-16. Group Channel Assignments Group 1 Channels Group1 in MCCF11 0–31 Group2 in MCCF11 32–63 Group3 in MCCF11 64–95 Group4 in MCCF11 96–127 Group1 in MCCF2 128–159 Group2 in MCCF2 160–191 Group3 in MCCF2 192–223 Group4 in MCCF2 224–255 Not on the MPC8250 nor the MPC8255.
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Multi-Channel Controllers (MCCs) Table 28-17. MCC Commands Command Description 1 INIT RX AND TX Performs both INIT RX and INIT TX commands contiguously, using the channel number supplied with the command. 1 INIT RX Initializes MCC receive FIFOs in groups of 32 channels, starting with the channel number programmed in the CPCR[MCN] field when the command is issued. This command should only be issued when the channels are disabled.
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Multi-Channel Controllers (MCCs) Event Register (MCCE)/Mask Register (MCCM)”) reports some global-level events and whether new activity has taken place in any of that MCC’s interrupt tables. These events can be masked by the MCCM.
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Multi-Channel Controllers (MCCs) desired interrupt handler latency or other factors. It is up to the user to determine an interrupt handling scheme that provides desired performance and functionality. 28.8.1 MCC Event Register (MCCE)/Mask Register (MCCM) The MCC event register (MCCE) is used to report events and generate interrupt requests. For each of its flags, a programmable mask/enable bit in MCCM determines whether an interrupt request is generated.
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Multi-Channel Controllers (MCCs) Table 28-18. MCCE/MCCM Register Field Descriptions (continued) Bits Name Description 13 TINT Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular table and starts processing a specific channel’s exception. The user returns from the interrupt handler when it reaches a table entry with V = 0.
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Multi-Channel Controllers (MCCs) Table 28-19. Interrupt Circular Table Entry Field Descriptions Bits Name Description 0 V Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt flags of the entry (before processing the interrupt). The V bits in the table are user-initialized. During initialization, the user must clear those bits in all table entries. 1 W Wrap bit.
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Multi-Channel Controllers (MCCs) Table 28-19. Interrupt Circular Table Entry Field Descriptions (continued) Bits Name Description 12 MRF Maximum receive frame length violation. This interrupt occurs when more bytes are received than the value specified in MFLR. This interrupt is generated as soon as the MFLR value is exceeded; the remainder of the frame is discarded 13 RXF Rx frame. A complete HDLC frame has been received. 14 BSY Busy.
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Multi-Channel Controllers (MCCs) To avoid these cases, pad out the SIRAM programming with “null entries,” entries with no CPM peripheral specified (MCC=0 and CSEL = 0000 in SIRAM entry) at the end of the SIRAM programming. Make the null SIRAM entries represent the appropriate amount of time so that the SI frame length matches the gap between sync pulses. 28.8.1.2.3 SIRAM Programming Failure to follow SIRAM programing guidelines can result in erratic behavior or possibly GUN errors.
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Multi-Channel Controllers (MCCs) 28.8.1.2.6 CPM Priority It is possible for the MCC to experience a GUN due to prioritization in the CPM. See Section 14.3.5, “Peripheral Interface,” for details on the CPM prioritization scheme. There are some options available for altering how the CPM peripheral prioritization works. These options provide the opportunity for the user to raise the priority of the MCC itself or lower the priority of other peripherals. In .29 µm (HiP3) Rev C.
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Multi-Channel Controllers (MCCs) Table 28-21. GUN Error Recovery—.29µm (HiP3) Rev B.3 and Subsequent Silicon Step Action 1 Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7]. 2 Issue the MCC RESET command. 3 Issue the INIT RX AND TX command to cover the channels in use. 4 Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated. 5 Enable TDM by setting appropriate bit. 28.8.1.
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Multi-Channel Controllers (MCCs) Table 28-22. RxBD Field Descriptions Bits Name Description 0 E Empty 0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition. The user is free to examine or write to any fields of this RxBD. The CP does not use this BD again while the empty bit remains zero. 1 The data buffer associated with this BD is empty, or reception is in progress.
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Multi-Channel Controllers (MCCs) Table 28-22. RxBD Field Descriptions (continued) Bits Name Description 11 NO Rx nonoctet-aligned frame. A frame of bits not divisible exactly by eight was received. NO = 1 for any type of nonalignment regardless of frame length. The shortest frame that can be detected is of type FLAG-BIT-FLAG, which causes the buffer to be closed with NO error indicated. The following shows how the nonoctet alignment is reported and where data can be found. msb lsb xxx ..............
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Multi-Channel Controllers (MCCs) 0 Offset + 0 R 1 RT 2 1 W 3 4 I L 5 TC 6 CM 7 8 — 9 UB 10 — Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer 11 SUD 12 1 15 PAD Offset + 6 1 SS7 mode only. Otherwise, reserved. Figure 28-22. MCC Transmit Buffer Descriptor (TxBD) Table 28-23 describes TxBD fields. Table 28-23. TxBD Field Descriptions Bits Name Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission.
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Multi-Channel Controllers (MCCs) Table 28-23. TxBD Field Descriptions (continued) Bits Name Description 8 UB User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this bit is used. 9–10 — Reserved, should be cleared. 11 — Reserved, should be cleared. SUD 12–15 PAD SS7 mode only: Signal unit delay 0 This buffer does not have a transmission delay. 1 A time delay of JTTDelay x 512 µs passes before this buffer is transmitted.
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Multi-Channel Controllers (MCCs) 3. Program the SI’s SIRAM and related registers. If the user wishes to enable the TDM at this time, the SIRAM programming cannot yet contain MCC-related timeslots. Those timeslots should be NULL entries and not programmed for MCC usage until after MCC-related initialization is complete. Refer to Chapter 15, “Serial Interface with Time-Slot Assigner,” for SI programming details. 4. Initialize buffer descriptors and data buffers as needed. 5.
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Multi-Channel Controllers (MCCs) The following sequence must be followed to stop a single channel in order to change the SI without using the shadow SI: 1. Issue a STOP command for the respective channel as described in Section 28.7, “MCC Commands.” 2. Change the SI. 3. Enable the MCC channel as described in Section 28.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode,” and Section 28.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.
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Multi-Channel Controllers (MCCs) If multiple synchronized TDMs are used (as an example 8 T1 with common clock/sync) it is recommended to start the TDMs out of phase relative to each other, in order to spread out CPM and bus utilization. This avoids CPM and bus activity peaks when all the channels would require CPM attention and possibly have to transfer data to/from the memory simultaneously.
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Chapter 29 Fast Communications Controllers (FCCs) NOTE The MPC8255 has only two FCCs—FCC1 and FCC2. The PowerQUICC II’s three fast communications controllers (FCCs) are serial communications controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the following: • Supports HDLC/SDLC and totally transparent protocols • FCC clocks can be derived from a baud-rate generator or an external signal.
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Fast Communications Controllers (FCCs) ATM interfaces (UTOPIA); see Chapter 15, “Serial Interface with Time-Slot Assigner,” Chapter 35, “Fast Ethernet Controller,” and Chapter 30, “ATM Controller and AAL0, AAL1, and AAL5.” The FCCs are independent from the physical interface, but FCC logic formats and manipulates data from the physical interface. That is why the interfaces are described separately. The FCC is described in terms of the protocol that it is chosen to run.
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Fast Communications Controllers (FCCs) 60x Bus Control Registers TCLK Clock Generator Peripheral Bus RCLK Internal Clocks RXD Modem Lines Receive Control Unit Decoder Delimiter Receive Data FIFO Transmit Data FIFO Shifter Shifter Transmit Control Unit Modem Lines Delimiter Encoder TXD Figure 29-1. FCC Block Diagram Table 29-1. Internal Clocks to CPM Clock Frequency Ratio Mode 29.
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Fast Communications Controllers (FCCs) 0 Field 1 2 DIAG 3 TCI 4 TRX TTX 5 CDP Reset 6 7 8 9 10 11 CTSP CDS CTSS 12 14 15 29 30 31 — 0000_0000_0000_0000 R/W R/W Addr 0x0x11300 (GFMR1), 0x0x11320(GFMR2), 0x0x11340(GFMR3) 16 Field 13 17 SYNL 18 19 RTSM 20 RENC Reset 21 REVD 22 23 TENC 24 25 TCRC 26 27 ENR ENT 28 MODE 0000_0000_0000_0000 R/W R/W Addr 0x11302 (GFMR1), 0x11322 (GFMR2), 0x11342 (GFMR3) Figure 29-2.
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Fast Communications Controllers (FCCs) Table 29-2. GFMR Register Field Descriptions (continued) Bits Name Description 3 TRX Transparent receiver. The PowerQUICC II FCCs offer totally transparent operation. However, to increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of the MODE bits. This lets the user implement unique applications such as an FCC transmitter configured to HDLC and a receiver configured to totally transparent operation.
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Fast Communications Controllers (FCCs) Table 29-2. GFMR Register Field Descriptions (continued) Bits Name Description 8 CTSS CTS sampling 0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized by the FCC, data is sent after a delay of no more than two serial clocks. 1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode, CTS must transition while the transmit clock is in the low state.
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Fast Communications Controllers (FCCs) Table 29-2. GFMR Register Field Descriptions (continued) Bits Name Description 26 ENR Enable receive. Enables the receiver hardware state machine for this FCC. 0 The receiver is disabled and any data in the receive FIFO buffer is lost. If ENR is cleared during reception, the receiver aborts the current character. 1 The receiver is enabled. ENR may be set or cleared regardless of whether serial clocks are present. Describes how to disable and reenable an FCC.
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Fast Communications Controllers (FCCs) 29.4 FCC Data Synchronization Registers (FDSRx) Each FCC has a 16-bit, memory-mapped, read/write data synchronization register (FDSR) that specifies the pattern used in the frame synchronization procedure of the synchronous protocols. In the totally transparent protocol, the FDSR should be programmed with the preferred SYNC pattern. For Ethernet protocol, it should be programmed with 0xD555.
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Fast Communications Controllers (FCCs) 0 1 15 Field TOD — Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x11308 (FTODR1), 0x0x11328 (FTODR2), 0x0x11348 (FTODR3) Figure 29-4. FCC Transmit-on-Demand Register (FTODR) Fields in the FTODR are described in Table 29-3. . Table 29-3. FTODR Field Descriptions Field Name 0 TOD 1–15 — 29.6 Description Transmit on demand 0 Normal polling.
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Fast Communications Controllers (FCCs) Dual-Port RAM System Memory Tx Buffer Descriptors Status and Control Data Length FCCx TxBD Table FCCx RxBD Table Pointer (RBASE) Buffer Pointer Tx Buffer FCCx TxBD Table Pointer (TBASE) Rx Buffer Descriptors FCCx RxBD Table Status and Control Data Length Buffer Pointer Rx Buffer Figure 29-5. FCC Memory Structure The format of transmit and receive BDs, shown in Figure 29-6, is the same for every FCC mode of operation except ATM mode; see Section 30.10.
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Fast Communications Controllers (FCCs) The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC is enabled, it starts with the first BD in that FCC’s TxBD table. When the CP detects that TxBD[R] is set, it begins processing the buffer. The CP detects that the BD is ready either by polling the R bit periodically or by the user writing to the FTODR.
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Fast Communications Controllers (FCCs) • See Section 29.12, “Disabling the FCCs On-the-Fly.” Some parameters in Table 29-4. are not described and are listed only to provide information for experienced users and for debugging. The user need not access these parameters in normal operation. Table 29-4. FCC Parameter RAM Common to All Protocols except ATM Offset1 Name Width 0x00 RIPTR Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for data.
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Fast Communications Controllers (FCCs) Table 29-4. FCC Parameter RAM Common to All Protocols except ATM (continued) Offset1 Name 0x1C TBASE 1 Width Description Word TxBD base address (must be divisible by eight). Defines the starting location in the memory map for the FCC TxBDs. This provides great flexibility in how FCC TxBDs are partitioned.
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Fast Communications Controllers (FCCs) Table 29-5. FCRx Field Descriptions Bits Name 0 — Description Reserved, should be cleared. 1 FCCP FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level. 0 Disables CPM low request level to refer to FCCs and MCCs. 1 Enables CPM low request level to refer to FCCs and MCCs. 2 GBL 3–4 BO Byte ordering. Used to select the byte ordering of the buffer.
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Fast Communications Controllers (FCCs) no effect on bit values. FCCE is cleared at reset. Fields of this register are protocol-dependent and are described in the respective protocol sections. 29.8.2 FCC Mask Registers (FCCMx) Each FCC has a read/write FCC mask register (FCCM) used to enable or disable CP interrupts to the core for events reported in an event register (FCCE). Bit positions in FCCM are identical to those in FCCE.
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Fast Communications Controllers (FCCs) The first RxBD’s empty bit must be set before the INIT RX COMMAND. However TxBDs can have their ready bits set at any time. Notice that the CPCR does not need to be accessed after a power-on reset until an FCC is to be used. An FCC should be disabled and reenabled after any dynamic change in its parallel I/O ports or serial channel physical interface configuration. A full reset using CPCR[RST] is a comprehensive reset that also can be used. 29.
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Fast Communications Controllers (FCCs) 6. Enable FCC transmission by setting GFMR[ENT]. 29.10.1.2 Recovery Sequence 1. Determine which BD is to be transmitted next and, if necessary, modify BDs. 2. Modify TBPTR field in Parameter RAM to point to next BD (if necessary). 3. Issue a “RESTART TX” command using the CPCR. 29.10.1.3 Adjusting Transmitter BD Handling When a TXE event occurs, the TBPTR may already point beyond BDs still marked as ready due to internal pipelining.
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Fast Communications Controllers (FCCs) TCLK TXD (Output) RTS (Output) First Bit of Frame Data Last Bit of Frame Data CTS (Input) Note: 1. A frame includes opening and closing flags and syncs, if present in the protocol. Figure 29-8. Output Delay from RTS Asserted If CTS is not already asserted when RTS is asserted, the delays to the first bit of data depend on when CTS is asserted. Figure 29-9 shows that the delay between CTS and the data can be approximately 0.
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Fast Communications Controllers (FCCs) TCLK TXD (Output) Data Forced High First Bit of Frame Data RTS (Output) CTS (Input) CTS Sampled Low RTS Forced High CTS Sampled High Note: 1. GFMR[CTSS] = 0. CTSP=0 or no CTS lost can occur. CTS Lost Signaled in BD TCLK TXD (Output) Data Forced High First Bit of Frame Data RTS (Output) RTS Forced High CTS (Input) Note: 1. GFMR[CTSS] = 1. CTSP=0 or no CTS lost can occur. CTS Lost Signaled in BD Figure 29-10.
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Fast Communications Controllers (FCCs) RCLK RXD (Input) CD (Input) First Bit of Frame Data Last Bit of Frame Data CD Sampled Low CD Sampled High Notes: 1. GFMR[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
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Fast Communications Controllers (FCCs) 29.12.1 FCC Transmitter Full Sequence For the FCC transmitter, the full disable and enable sequence is as follows. 1. Issue the STOP TRANSMIT command. This is recommended if the FCC is currently transmitting data because it stops transmission in an orderly way. If the FCC is not transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command has been issued and completed), then the STOP TRANSMIT command is not required.
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Fast Communications Controllers (FCCs) 2. Issue the INIT RX PARAMETERS command. Any additional changes can be made now. 3. Set GFMR[ENR]. 29.12.5 Switching Protocols A user can switch the protocol that the FCC is executing (HDLC) without resetting the board or affecting any other FCC by taking the following steps: 1. Clear GFMR[ENT] and GFMR[ENR]. 2. Issue the INIT TX AND RX PARAMETERS command. This command initializes both transmit and receive parameters.
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Chapter 30 ATM Controller and AAL0, AAL1, and AAL5 NOTE The functionality described in this chapter is not available on the MPC8250. The ATM controller provides the ATM and AAL layers of the ATM protocol using the universal test and operations physical layer (PHY) interface for ATM (UTOPIA level II) for both master and slave modes.
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ATM Controller and AAL0, AAL1, and AAL5 • • • • • • • • • • • • • • • Up to 255 active VCs internally, and up to 64K VCs using external memory TM 4.0 CBR, VBR, UBR, UBR+ traffic types VBR type 1 and 2 traffic using leaky buckets (GCRA) TM 4.
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ATM Controller and AAL0, AAL1, and AAL5 • • • • • • • – Sequence number generation – Sequence number protection (CRC-3 and even parity) generation — Structured AAL1 cell format – Automatic synchronization using the structured pointer during reassembly – Structured pointer generation during segmentation — Unstructured AAL1 cell format – Clock recovery using external SRTS (synchronous residual time stamp) logic during reassembly – SRTS generation using external logic during segmentation AAL0 format — Re
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ATM Controller and AAL0, AAL1, and AAL5 • • • • 30.2 — Performs ATMF UNI 4.
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ATM Controller and AAL0, AAL1, and AAL5 30.2.1 Transmitter Overview Before the transmitter is enabled, the host must initialize the PowerQUICC II and create the transmit data structure, described in Section 30.10, “ATM Memory Structure.” When data is ready for transmission, the host arranges the BD table and writes the pointer of the first BD in the transmit connection table (TCT). The host issues an ATM TRANSMIT command, which inserts the current channel to the ATM pace control (APC) unit.
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ATM Controller and AAL0, AAL1, and AAL5 For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them into the AAL1 user data field. The CP generates the AAL1 PDU header and inserts it into the cell. The header consists of the SN, SNP, and the structured pointer. The PowerQUICC II supports partially filled cells configured on a per-VC basis.
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ATM Controller and AAL0, AAL1, and AAL5 (UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell transfers use the UTOPIA level II, cell-level handshake. Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to indicate that the PHY has a complete cell in its receive FIFO. The receiver reads a complete cell from the UTOPIA interface and translates the header address (VP/VC) to a channel code by performing an address look-up.
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ATM Controller and AAL0, AAL1, and AAL5 The PowerQUICC II supports partially filled cells configured on a per-VC basis. In this mode (RCT[PFM] = 1), the ATM controller copies only the valid octets from the cell user data field to the buffer. 30.2.2.2.1 AAL1 CES Receiver Overview Refer to Section 31.3, “AAL1 CES Receiver Overview.” 30.2.2.3 AAL0 Receiver Overview For AAL0, no specific adaptation layer processing is done. The ATM controller copies the whole cell to an external buffer.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-1. ATM Service Types Service Type Cell Rate Pacing Real-Time/ Non-Real-Time Relative Priority CBR PCR RT 1 (highest) VBR-RT PCR, SCR (peak-and-sustain) RT 2 VBR-NRT PCR, SCR (peak-and-sustain) NRT 3 ABR1 PCR NRT 4 UBR+ PCR, MCR (peak-and-minimum) NRT 5 UBR PCR NRT 6 (lowest) 1 When ABR flow control is active, the CP automatically adapts the APC parameters PCR, PCR_FRACTION.
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ATM Controller and AAL0, AAL1, and AAL5 Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to transmit in the same slot are linked to each other using the APC linked-channel field in the TCT. The linked list is not limited; however, if the number of channels for the current slot exceeds the cells per slot parameter (CPS), the extra channels are sent in subsequent time slots. (The rescheduling of extra channels is based on the original slot to maintain each channel’s pace.
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ATM Controller and AAL0, AAL1, and AAL5 line rate (B) Min bit rate = (number_of_slots - 1) × cells per slot For the above example, 32 kbps = 155.52 Mbps/((1216-1) × 4). Use equations (A) and (B) to obtain the maximum and minimum bit rates of a scheduling table. For example, given a line rate = 155.52 Mbps, number_of_slots = 1025, and CPS = 8: Max bit rate = (155.52 Mbps)/8 = 19.44 Mbps Min bit rate = (155.52 Mbps)/(1024 × 8) = 18.98 kbps. 30.3.
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ATM Controller and AAL0, AAL1, and AAL5 30.3.5.3 Peak and Sustain Traffic Type (VBR) Variable bit rate (VBR) traffic can burst at the peak cell rate as long as the long-term average rate does not exceed the sustainable cell rate. To support VBR channels, the APC implements the GCRA (generic cell rate algorithm) using three parameters—the peak cell rate (PCR), the sustained cell rate (SCR), and burst tolerance (BT), as shown in Figure 30-2. (The GCRA is also known as the leaky bucket algorithm.
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ATM Controller and AAL0, AAL1, and AAL5 Equation D yields the number of slots the user writes to the channel’s TCT[BT]. BT [slots] = (MBS[cells] - 2) × (SCR[slots] - PCR[slots]) + SCR[slots] (D) = (1000 - 2) × ((9+185/256) - (3+62/256)) + (9 +185/256) = 6477 30.3.5.3.2 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2 The PowerQUICC II supports two ways to schedule VBR traffic based on the cell loss priority (CLP).
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ATM Controller and AAL0, AAL1, and AAL5 30.4.1 External CAM Lookup An external CAM is usually used when the range of VCI/VPI values varies widely or is unknown. Clearing GMODE[ALM] selects the external CAM address lookup mechanism. If there is no match in the external CAM, the cell is considered a misinserted cell. The external CAM can point to internal or external channels (channels whose connection table resides in external memory).
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ATM Controller and AAL0, AAL1, and AAL5 30.4.2 Address Compression The address compression mechanism uses two levels of address translation to help minimize the memory space needed to cover the available address range. The first level of translation (VP-level) uses a look-up table based on the 4-bit PHY address and the 12-bit virtual path identifier; the second level (VC-level) uses the 16-bit virtual channel identifier.
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ATM Controller and AAL0, AAL1, and AAL5 to indicate the received cell’s channel code. Address compression field descriptions are shown in Table 30-3. Table 30-3. Field Descriptions for Address Compression Field PHY Addr Description In multiple PHY mode, this field contains the 4 least-significant bits of the current channel’s physical address. Because this comparison field is limited to 4 bits, two sets of look-up tables are needed if using more than 16 PHYs.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs VP-Level Table Entry VC_MASK Number of Ones in VC_MASK VC-Level Table Size VCOFFSET 2 0xA007 5 25 = 32 entries 64 + 8 = 72 3 x x x 72 + 32 = 104 The PowerQUICC II can check that all unallocated bits of the PHY + VPI are 0 by setting GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell is considered a misinserted cell.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-6. VC-Level Table Entry Address Calculation Example VCT_BASE VCOffset VC-Level Table Size VC_MASK VCI VC Pointer VC Entry Address 0x0084_0000 0x0100 32 entries 0x0037 0x0031 0x19 VC Base = 0x840000 0x100 x 4 = 0x000400 0x19 x 4 = 0x000064 0x840464 Figure 30-8 shows the VC pointer address compression from Table 30-6.
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ATM Controller and AAL0, AAL1, and AAL5 Check address No Discard cell Match Yes No PTI=1xx or VCI=3,4,6,7-15 and filter enable Send cell to VC queue Yes Send cell to raw cell queue Figure 30-9. ATM Address Recognition Flowchart NOTE Even reserved VCI channels should appear in the CAM or address compression tables; otherwise, a cell on a reserved channel will be considered misinserted. 30.
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ATM Controller and AAL0, AAL1, and AAL5 support. The destination receives forward RM cells and returns them to the source as backward RM cells. The PowerQUICC II implements source behavior by adjusting the rate according to each returning backward RM cell’s ER. Explicit rate feedback has several advantages over binary feedback (EFCI). Explicit rate feedback allows immediate source rate adaptation, eliminating rate oscillation caused by incremental rate changes.
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ATM Controller and AAL0, AAL1, and AAL5 7. Before sending an F-RM cell, if more than ADTF (ACR decrease time factor) has elapsed since sending the last F-RM cell, ACR is reduced to ICR. In other words, if the source does not fully use its gained bandwidth, it loses it and resumes sending at its initial cell rate. 8.
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ATM Controller and AAL0, AAL1, and AAL5 Start Channel Tx No ACR < TCR Yes Source End-Sys 9 ACR is low sent only out-of-rate cells at TCR Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1) Schedule: Time_to_send = now+1/TCR EXIT ACR>=TCR RM/DATA In Rate Cell Tx Figure 30-11. ABR Transmit Flow MPC8260 PowerQUICC II Family Reference Manual, Rev.
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ATM Controller and AAL0, AAL1, and AAL5 RM/DATA In Rate Cell Tx Source End-Sys 3 B-RM/DATA In Rate Cell Tx No Count >= Nrm or (Count > Mrm and Now ≥ (Last_RM+Trm)) Count=Number of data cells from last F-RM. Nrm=Number of data cells between every RM cell Mrm=Fixed number=2 Trm=Max time between every F-RM Cells. F-RM In Rate Cell Tx Checking “Time-Out Factor” Max time allowed between RM Cells before a rate Decrease is required.
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ATM Controller and AAL0, AAL1, and AAL5 B-RM/DATA In Rate Cell Tx No Turn-around and (First-turn or not data-in-queue) Destination End-Sys 1,2,3,4 B-RM In Rate Cell Tx Yes CI-TA = CI-TA || CI-VC Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA, CI-TA, NI-TA, CLP=0) CI-VC = 0 Turn-around = first-turn = FALSE Count = Count+1 EXIT Data Cell Tx Send Data Cell CLP = EFCI = 0 Count = Count+1 Schedule:Time_to_send = Now+1/ACR EXIT Figure 30-13.
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ATM Controller and AAL0, AAL1, and AAL5 B-RM Cells Rx No CI = 1 Yes Source End-Sys 5 ACR = ACR-ACR×RDF No NI = 0 Yes Source End-Sys 1, 6 ACR = ACR+RIF×PCR ACR = min(ACR,PCR) ACR = min(ACR,ER) ACR = max(ACR,MCR) Source End-Sys 5, 6 No BN = 0 Yes The source generate this RM Unack = 0 Unack = Number of F-RM in absence of B-RM = 0 EXIT Figure 30-14. ABR Receive Flow 30.5.2 RM Cell Structure Table 30-7 describes the structure of the RM cell supported by the PowerQUICC II.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-7. Fields and their Positions in RM Cells Fields Octet Bits Header 1–5 All ATM cell header RM-VCC PTI=6 ID 6 All Protocol ID 1 DIR 7 0 Direction of RM cell (0 = forward, 1 = backward) BN 7 1 Backward notification (BN = 0, the cell was generated by the source; BN=1, the cell was generated by the network or by the destination) CI 7 2 Congestion indication. (1 = congestion, 0 = otherwise) NI 7 3 No increase indication.
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ATM Controller and AAL0, AAL1, and AAL5 30.5.3 ABR Flow Control Setup Follow these steps to setup ABR flow control: 1. Initialize the ABR data structure: RCT, TCT, RCT-ABR protocol-specific, TCTE-ABR protocol-specific. 2. Initialize ABR global parameters in the parameter RAM. See Section 30.10.1, “Parameter RAM.” 3. Program the AAL-type in the RCT and TCT to AAL5 and set TCT[ABRF]. NOTE ABR flow control is available only with AAL5. 4.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-9. Pre-Assigned Header Values at the NNI Use VPI VCI PTI CLP Segment OAM F4 flow cell aaaa_aaaa_aaaa 0000_0000_0000_0011 0a0 a End-to-end OAM F4 flow cell aaaa_aaaa_aaaa 0000_0000_0000_0100 0a0 a Segment OAM F5 flow cell aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa 100 a End-to-end OAM F5 flow cell aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa 101 a a= available for use by the appropriate ATM layer function 30.6.
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ATM Controller and AAL0, AAL1, and AAL5 insert it in an AAL0 TxBD. Finally, issue a ATM TRANSMIT command to send the OAM cell. For multiple PHYs, use several AAL0 channels—each PHY should have one transmit raw cell queue that is associated with its scheduling table. A series of OAM cells can be sent using one ATM TRANSMIT command by creating a table of AAL0 TxBDs.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-10. Performance Monitoring Cell Fields Field Description BRC FMC MCSN Monitoring cell sequence number. The sequence number of the performance monitoring cell (modulo 256). Yes Yes TUC0+1 Total user cell 0+1 count. Counts all user cells (modulo 65,536) sent before the FMC was inserted. Yes Yes TUC0 Total user cell 0 count. Counts CLP = 0 user cells (modulo 65,536) sent before the FMC was inserted. Yes Yes TSTP Time stamp.
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ATM Controller and AAL0, AAL1, and AAL5 Before the BRC is transferred to the transmit raw cell queue, the PM function type should be changed to backward reporting and additional checking should be done regarding the BLER field. If the sequence numbers (MCSN) of the last two FMCs are not sequential or the differences between the last two TUCs and the last two TRCCs are not equal, BLER should be set to all ones (see the ITU I.610 recommendation).
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ATM Controller and AAL0, AAL1, and AAL5 30.6.6.4 BRC Performance Calculations BRC reception uses the regular AAL0 raw cell queue. On receiving two consecutive BRC cells, the management layer can calculate the following: • The difference between two TUCs (Nt) • The difference between two TRCCs (Nr) Information about the connection can be gained by comparing Nt and Nr: • If Nt > Nr, the difference indicates the number of lost cells of this block test.
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ATM Controller and AAL0, AAL1, and AAL5 CAM data in field: 16-bit 4-bit 12-bit 16-bit UEAD PHY addr VPI VCI 0 15 16 19 20 31 32 47 Figure 30-20. External CAM Address in UDC Extended Address Mode 30.8 ATM Layer Statistics ATM layer statistics can be used to identify problems, such as the line-bit error rate, that affect the UNI performance.
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ATM Controller and AAL0, AAL1, and AAL5 BD Table TDM Interface Buffer 1 MCC Transmitter MCC Tx ptr ATM Rx ptr UTOPIA Interface ATM* Receiver 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Buffer 2 Buffer 3 Buffer 4 Buffer 5 BD Table UTOPIA Interface Buffer 1 ATM Transmitter ATM Tx ptr MCC Rx ptr TDM Interface MCC* Receiver 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Buffer 2 Buffer 3 Buffer 4 Buffer 5 * The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit. Figure 30-21.
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ATM Controller and AAL0, AAL1, and AAL5 30.9.3 Timing Issues Use of the TDM interface assumes that all communicating entities are synchronized (that is, that they are using a synchronized serial clock). If the TDM interfaces are not synchronized, a slip can occur in the reassembly buffer. If a buffer-not-ready event occurs at the MCC transmitter, the user must restart the MCC transmit channel. If a buffer-not-ready event occurs at the ATM transmitter, the user must restart the ATM transmit channel. 30.
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ATM Controller and AAL0, AAL1, and AAL5 The MCC and ATM controller should be synchronized with the framer’s multi-frame block boundary. At the ATM side, the structured block size should equal the multi-frame block size plus the size of the CAS block so that the structured pointer, inserted by the ATM controller, points to the start of the structured data block. At the MCC side, the MCC must to be synchronized with the super frame sync signal.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-11. ATM Parameter RAM Map (continued) Offset1 Name 0x44 UDC_TMP_BASE Hword UDC mode only. Points to a total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined offset from dual-port RAM base. (Recommended address space: 0x3000–0x4000 or 0xB000–0xC000) 0x46 INT_RCT_BASE Hword Internal receive connection table base. User-defined offset from dual-port RAM base.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-11. ATM Parameter RAM Map (continued) Offset1 Name 0x78 VPT1_BASE / EXT_CAM1_BASE 0x7C VCT1_BASE 0x80 VP_MASK 0x82 VCIF Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCIF bit = 1 the cell is sent to the raw cell queue. VCIF[0–2, 5] should be zero. See Section 30.10.1.2, “VCI Filtering (VCIF).” 0x84 GMODE Hword Global mode. User-defined. See Section 30.10.1.3, “Global Mode Entry (GMODE).
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-11. ATM Parameter RAM Map (continued) 1 Offset1 Name 0xB0 TCR Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the APC minimum cell rate (MCR) should be at least TCR.
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ATM Controller and AAL0, AAL1, and AAL5 30.10.1.3 Global Mode Entry (GMODE) Figure 30-23 shows the layout of the global mode entry (GMODE). 0 Field 0 1 0 2 GBL 3 0 4 0 5 0 6 7 8 9 ALB CTB REM 0 10 IMA_EN 11 1 UEAD 12 13 14 15 0 ALM CUAB EVPT Figure 30-23. Global Mode Entry (GMODE) 1 MPC8264 and MPC8266 only. Table 30-14 describes GMODE fields. Table 30-14.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-14. GMODE Field Descriptions (continued) 1 Bits Name 14 — 15 ALM Description Reserved, should be cleared. Address look-up mechanism. See Section 30.4, “VCI/VPI Address Lookup Mechanism.” 0 External CAM lookup. 1 Address compression. MPC8264 and MPC8266 only: GMODE[REM] must be set to disable receive emergency mode.
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ATM Controller and AAL0, AAL1, and AAL5 a VC when sending a ATM TRANSMIT command, initiating the external CAM or address compression tables, and when the CP sends an interrupt to an interrupt queue. Example: Suppose a configuration supports 1,024 regular ATM channels. To allocate 4 Kbytes of dual-port RAM space to the internal connection table, determine that channel codes 0–63 are internal (64 VCs × 64 bytes (RCT and TCT) = 4 K). Channels 0–1 are reserved.
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ATM Controller and AAL0, AAL1, and AAL5 0 Offset + 0x00 1 — 2 3 GBL 4 BO 5 6 — DTB Offset + 0x02 — INF 7 8 BIB 9 10 11 — BUFM SEGF ENDF — Offset + 0x04 12 13 — 14 15 INTQ ABRF AAL RX Data Buffer Pointer (RXDBPTR) Offset + 0x06 Offset + 0x08 Cell Time Stamp Offset + 0x0A Offset + 0x0C RBD_Offset Offset + 0x0E Protocol Specific Offset + 0x10 • Offset + 0x12 • • Offset + 0x14 • • Offset + 0x16 For AAL5,Section 30.10.2.2.1, “AAL5 Protocol-Specific RCT.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-16. RCT Field Descriptions Offset Bits Name Description 0x00 0–1 — 2 GBL Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. 3–4 BO Byte ordering—used for data buffers. 00 Reserved 01 Munged little endian 1x Big endian 5 — Reserved, should be cleared. 6 DTB Data buffers bus 0 Data buffers reside on the 60x bus. 1 Data buffers reside on the local bus.
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ATM Controller and AAL0, AAL1, and AAL5 Table 30-16. RCT Field Descriptions (continued) Offset Bits Name Description 0x02 0 — 1 INF 2–11 — 12 ABRF 13–15 AAL 0x04 — RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer. 0x08 — Cell Time Stamp Used for reassembly time-out. Whenever a cell is received, the PowerQUICC II time stamp timer is sampled and written to this field. See Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).
PAGE 966
ATM Controller and AAL0, AAL1, and AAL5 0 15 Offset + 0x0E TML Offset + 0x10 RX CRC Offset + 0x12 Offset + 0x14 RBDCNT Offset + 0x16 — Offset + 0x18 — RXBM RXFM — BPOOL Figure 30-26. AAL5 Protocol-Specific RCT Table 30-17 describes AAL5 protocol specific RCT fields. Table 30-17. RCT Settings (AAL5 Protocol-Specific) Offset Bits Name 0x0E — TML 0x10 — RxCRC 0x14 — RBDCNT 0x16 — — Reserved, should be cleared. 0x18 0–7 — Reserved, should be cleared.
PAGE 967
ATM Controller and AAL0, AAL1, and AAL5 0 15 Offset + 0x0E AAL5 Protocol-Specific Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 PCR Offset + 0x18 RDF RIF AAL5 Protocol-Specific Figure 30-27. AAL5-ABR Protocol-Specific RCT Table 30-18 describes AAL5-ABR protocol-specific RCT fields. Table 30-18. ABR Protocol-Specific RCT Field Descriptions Offset Bits Name 0x0E — — 0x16 — PCR Peak cell rate. The peak number of cells per second of the current ABR channel.
PAGE 968
ATM Controller and AAL0, AAL1, and AAL5 Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions Offset Bits Name 0x0E 0–7 — 8 PFM Partially filled mode. 0 Partially filled cells mode is not used. 1 Partially filled cells mode is used. The receiver copies only valid octets from the AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the AAL1 user data field is specified in the VOS (valid octet size) field. 9 SRT Synchronous residual time stamp.
PAGE 969
ATM Controller and AAL0, AAL1, and AAL5 Table 30-19. AAL1 Protocol-Specific RCT Field Descriptions (continued) Offset Bits Name 0x18 0–3 — 4 SNEM 5–7 — 8 RXBM 9–15 — 30.10.2.2.4 Description Reserved, should be cleared. Sequence number error flag interrupt mask 0 This mode is disabled. 1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt queue even if RCT[RXBM] is cleared.
PAGE 970
ATM Controller and AAL0, AAL1, and AAL5 Table 30-20. AAL0-Specific RCT Field Descriptions (continued) Offset Bits Name 0x18 0–7 — 8 RXBM 9–15 — 30.10.2.2.5 Description Reserved, should be cleared. Receive buffer interrupt mask 0 The receive buffer event of this channel is masked. (The RXB event is not sent to the interrupt queue when receive buffers are closed.) 1 The receive buffer event of this channel is enabled. Reserved, should be cleared.
PAGE 971
ATM Controller and AAL0, AAL1, and AAL5 Table 30-21 describes general TCT fields. MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 972
ATM Controller and AAL0, AAL1, and AAL5 MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 973
ATM Controller and AAL0, AAL1, and AAL5 Table 30-21. TCT Field Descriptions Offset Bits Name Description 0x00 0–1 — 2 GBL Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. 3–4 BO Byte ordering. This field is used for data buffers. 00 Reserved 01 Power PC little endian 1x Big endian 5 — Reserved, should be cleared. 6 DTB Data buffer bus 0 Reside on the 60x bus. 1 Reside on the local bus.
PAGE 974
ATM Controller and AAL0, AAL1, and AAL5 Table 30-21. TCT Field Descriptions (continued) Offset Bits Name Description 0x02 0 — 1 INF 2–11 — 12 ABRF 13–15 AAL 0x04 — TxDBPTR Tx data buffer pointer. Holds the real address of the current position in the Tx buffer. 0x08 — TBDCNT Transmit BD count. Counts the remaining data to transmit in the current transmit buffer.
PAGE 975
ATM Controller and AAL0, AAL1, and AAL5 Table 30-21. TCT Field Descriptions (continued) Offset Bits Name 0x1C 0–1 — 2–7 PMT 8–15 0x1E 0–11 0x1E 30.10.2.3.1 Description Reserved, should be cleared. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed on-the-fly. TBD_BASE TxBD base. Points to the first BD in the channel’s TxBD table.
PAGE 976
ATM Controller and AAL0, AAL1, and AAL5 0 Offset + 0x10 1 2 3 — 4 5 6 7 Valid Octet Size (VOS) 8 9 10 11 PFM SRT SPF STF Offset + 0x12 SRTS_DEV Block Size Offset + 0x14 SRTS_TMP Structured Pointer (SP) 12 — 13 14 15 SN Figure 30-32. AAL1 Protocol-Specific TCT Table 30-23 describes AAL1 protocol-specific TCT fields. Table 30-23. AAL1 Protocol-Specific TCT Field Descriptions Offset Bits Name 0x10 0-1 — 2–7 VOS Valid octet size. Partially filled cell mode only.
PAGE 977
ATM Controller and AAL0, AAL1, and AAL5 30.10.2.3.3 AAL0 Protocol-Specific TCT Figure 30-33 shows the AAL0 protocol-specific TCT. 0 7 Offset + 0x10 — Offset + 0x12 8 9 10 11 0 CR10 — ACHC 12 15 — — Offset + 0x14 Figure 30-33. AAL0 Protocol-Specific TCT Table 30-24 describes AAL0 protocol-specific TCT fields. Table 30-24. AAL0-Specific TCT Field Descriptions Offset Bits Name 0x10 0–7 — Reserved, should be cleared. 8 0 Must be 0.
PAGE 978
ATM Controller and AAL0, AAL1, and AAL5 0 1 7 8 Offset + 0x00 SCR Offset + 0x02 Burst Tolerance (BT) Offset + 0x04 Out of Buffer Rate (OOBR) Offset + 0x06 Sustain Rate Remainder (SRR) Offset + 0x08 15 SCR Fraction (SCRF) Sustain Rate (SR) Offset + 0x0A Offset + 0x0C VBR2 — Offset + 0x0E-1E — Figure 30-34. Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific Table 30-25 describes VBR protocol-specific TCTE fields. Table 30-25.
PAGE 979
ATM Controller and AAL0, AAL1, and AAL5 0 7 Offset + 0x00 Offset + 0x02 8 15 MCR — Offset + 0x04 MCR Fraction (MCRF) Maximum Delay Allowed (MDA) Offset + 0x06–0x1E — Figure 30-35. UBR+ Protocol-Specific TCTE Table 30-26 describes UBR+ protocol-specific TCTE fields. Table 30-26. UBR+ Protocol-Specific TCTE Field Descriptions Offset Bits Name 0x00 — MCR 0x02 0–7 — 8–15 Minimum cell rate for this channel. MCR is in units of APC time slots. Reserved, should be cleared.
PAGE 980
ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 6 7 8 Offset + 0x00 ER-TA Offset + 0x02 CCR-TA Offset + 0x04 MCR-TA Offset + 0x06 TUAR — CI-TA NI-TA — CP-TA Offset + 0x08 MCR Offset + 0x0A UNACK Offset + 0x0C ACR Offset + 0x0E ACRC 9 — 10 11 12 CI-VC 13 14 15 — — Offset + 0x10 RM Cell Time Stamp (RCTS) Offset + 0x12 Offset + 0x14 FRST — CDF COUNT Offset + 0x16 ICR Offset + 0x18 CRM Offset + 0x1A ADTF Offset + 0x1C ER Offset + 0x1E ER-BRM Figure 30-3
PAGE 981
ATM Controller and AAL0, AAL1, and AAL5 Table 30-27. ABR-Specific TCTE Field Descriptions (continued) Offset Bits Name Description 3 NI-TA No increase–turn-around cell. Holds the NI of the last received F-RM cell. If another F-RM cell arrives before the previous one was turned around, NI-TA is overwritten by the new RM cell’s NI. 4–6 — 7 CP-TA 8–9 — 10 CI-VC 11–15 — 0x08 — MCR 0x0A — UNACK Used by the CP to count F-RM cells sent in an absence of received B-RM cells.
PAGE 982
ATM Controller and AAL0, AAL1, and AAL5 Table 30-27. ABR-Specific TCTE Field Descriptions (continued) Offset Bits Name Description 0x1C — ER Explicit rate. Holds the explicit rate value (in cells/sec) of the current ABR channel. ER is copied to the F-RM cell ER field. The user usually initializes this field to PCR. ER uses the ATMF TM 4.0 floating-point format. 0x1E — ER-BRM Explicit rate-backward RM cell. Holds the maximum explicit rate value (in cells/sec) allowed for B-RM cells.
PAGE 983
ATM Controller and AAL0, AAL1, and AAL5 Table 30-28. OAM—Performance Monitoring Table Field Descriptions Offset Bits 0x00 Name Description 0 FMCE Enables FMC transmission. Initialize to 1. 1 TSTE FMC time stamp enable 0 The time stamp field of the FMC is coded with all 1’s. 1 The value of the time stamp timer is inserted into the time stamp field of the FMC. 2–4 — 5–15 BLCKSIZE 0–4 — 5–15 TCC TX cell count. Used by the CP to count data cells sent. Initialize to zero.
PAGE 984
ATM Controller and AAL0, AAL1, and AAL5 APC Parameter Tables APC Priority Table APC Scheduling Tables Parameter Table PHY #0 Priority 1 Priority 1 Scheduling Table Priority 2 Priority 2 Scheduling Table Parameter Table PHY #1 Priority 3 Priority 3 Scheduling Table Priority 4 Priority 4 Scheduling Table Priority 5 Priority 5 Scheduling Table Priority 6 Priority 6 Scheduling Table Priority 7 Priority 7 Scheduling Table Priority 8 Priority 8 Scheduling Table Parameter Table PHY #31 Note:
PAGE 985
ATM Controller and AAL0, AAL1, and AAL5 Table 30-29. APC Parameter Table (continued) 1 Offset1 Name Width 0x09 CPS_ABR Byte 0x0A LINE_RATE_AB R 0xC REAL_TSTP Word Real-time stamp pointer used internally by the APC. Should be cleared initially. 0x10 APC_STATE Word Used internally by the APC. Should be cleared initially. Description ABR only. Cells per slot represented as a power of two. User-defined. (For example, if CPS is 1, CPS_ABR = 0x00; if CPS is 8, CPS_ABR = 0x03.) Hword ABR only.
PAGE 986
ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 Field TCTE 6 7 8 9 10 11 12 13 14 15 000_0000_0000_0000 Figure 30-40. Control Slot Table 30-31 describes control slot fields. Table 30-31. Control Slot Field Description Bits Name 0 TCTE 1–15 — Description Used for external channels only. 0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+ channels) 1 Channels in this scheduling table use external TCTE.
PAGE 987
ATM Controller and AAL0, AAL1, and AAL5 Ch1 TxBD Table Tx Buffer 1 of Channel 1 Ch1 TxBD Table Pointers in the TCT TBD_BASE TBD_Offset 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Tx Buffer 2 of Channel 1 Tx Buffer 3 of Channel 1 Tx Buffer 4 of Channel 1 Tx Buffer 5 of Channel 1 Ch4 TxBD Table Tx Buffer 1 of Channel 4 Ch4 TxBD Table Pointers in the TCT TBD_BASE TBD_Offset 1 0 0 0 0 1 1 BD BD BD BD BD BD BD 1 2 3 4 5 6 7 Tx Buffer 2 of Channel 4 Tx Buffer 3 of Channel 4 Tx Buffer 4 of Channel 4 Tx Buffer
PAGE 988
ATM Controller and AAL0, AAL1, and AAL5 Ch1 RxBD Table Rx Buffer 1 of Channel 1 Ch1 RxBD Table Pointers in the RCT RBD_BASE RBD_Offset 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Rx Buffer 2 of Channel 1 Rx Buffer 3 of Channel 1 Rx Buffer 4 of Channel 1 Rx Buffer 5 of Channel 1 Ch4 RxBD Table Rx Buffer 1 of Channel 4 Ch4 RxBD Table Pointers in the RCT RBD_BASE RBD_Offset 1 0 0 0 0 1 1 BD BD BD BD BD BD BD 1 2 3 4 5 6 7 Rx Buffer 2 of Channel 4 Rx Buffer 3 of Channel 4 Rx Buffer 4 of Channel 4 Rx Buffer
PAGE 989
ATM Controller and AAL0, AAL1, and AAL5 Ch1 RxBD Table RBD_BASE RBD_Offset Free Buffer Pool 1 FBP1_BASE Pointer 1 Pointer 2 Pointer 3 Pointer 4 Pointer 5 Pointer 6 FBP1_PTR 0 1 1 1 1 BD BD BD BD BD 1 2 3 4 5 Buffer 1 of FBP1 Buffer 2 of FBP1 Ch4 RxBD Table Buffer 4 Buffer 5 RBD_BASE, RBD_Offset Buffer 6 1 1 1 1 BD BD BD BD 1 2 3 4 Buffer 3 of FBP1 Notes: Buffers 2 and 3 are receiving data. After buffer 1 is processed, it can be returned to the pool. Figure 30-43.
PAGE 990
ATM Controller and AAL0, AAL1, and AAL5 Offset + 0x00 0 1 2 3 V — W I Offset + 0x02 4 15 Buffer Pointer (BP) Buffer Pointer (BP) Figure 30-45. Free Buffer Pool Entry Table 30-32 describes free buffer pool entry fields. Table 30-32. Free Buffer Pool Entry Field Descriptions Offset Bits Name 0x00 0 V Valid buffer entry. 0 This free buffer pool entry contains an invalid buffer pointer. 1 This free buffer pool entry contains a valid buffer pointer. 1 — Reserved, should be cleared.
PAGE 991
ATM Controller and AAL0, AAL1, and AAL5 Table 30-33. Free Buffer Pool Parameter Table (continued) Offset 1 Bits Name 0x0A 0 BUSY 1 RLI Red-line interrupt. Set by the CP when it fetches a buffer pointer with I = 1. FCCE[GRLI] is also set. Initialize to zero. 2–7 — Reserved, should be cleared. 8 EPD 9–15 — — FBP_ENTRY 0x0C 1 Description The CP sets this bit when it tries to fetch buffer pointer with V bit clear. FCCE[GBPB] is also set. Initialize to zero. Early packet discard.
PAGE 992
ATM Controller and AAL0, AAL1, and AAL5 Table 30-35 describes AAL5 RxBD fields. m Table 30-35. AAL5 RxBD Field Descriptions Offset Bits Name Description 0x00 0 E Empty. 0 The buffer associated with this RxBD is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The buffer associated with this RxBD is empty or reception is in progress.
PAGE 993
ATM Controller and AAL0, AAL1, and AAL5 Table 30-35. AAL5 RxBD Field Descriptions (continued) Offset Bits Name Description 0x02 — DL Data length. The number of octets written by the CP into this BD’s buffer. It is written by the CP once the BD is closed. In the last BD of a frame, DL contains the total frame length. 0x04 RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in internal or external memory.
PAGE 994
ATM Controller and AAL0, AAL1, and AAL5 Table 30-36. AAL1 RxBD Field Descriptions Offset Bits Name Description 0x00 0 E Empty 0 The buffer associated with this RxBD is filled with received data or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP cannot use this BD again while E = 0. 1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD.
PAGE 995
ATM Controller and AAL0, AAL1, and AAL5 Table 30-37. AAL0 RxBD Field Descriptions Offset Bits Name Description 0x00 0 E Empty 0 The buffer associated with this RxBD is filled with received data, or data reception was aborted due to an error. The core can examine or write to any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The Rx buffer is empty or reception is in progress. This RxBD and its associated receive buffer are owned by the CP.
PAGE 996
ATM Controller and AAL0, AAL1, and AAL5 30.10.5.9 AAL5, AAL1 CES User-Defined Cell—RxBD Extension In user-defined cell mode, the AAL5 and AAL1 CES RxBDs are extended to 32 bytes; see Figure 30-49. NOTE For AAL0, a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. Offset + 0x08 Extra Cell Header. Used to store the user-defined cell’s extra cell header. The extra cell header can be 1–12 bytes long. Offset + 0x14 Reserved (12 bytes) Figure 30-49.
PAGE 997
ATM Controller and AAL0, AAL1, and AAL5 Table 30-38. AAL5 TxBD Field Descriptions Offset Bits Name Description 0x00 0 R Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or after an error condition is encountered. 1 The user-prepared buffer has not been sent or is currently being sent. No fields of this BD may be written by the user once R is set.
PAGE 998
ATM Controller and AAL0, AAL1, and AAL5 Offset + 0x00 0 1 2 3 R — W I 4 5 — 6 7 8 9 10 CM 11 12 13 14 15 — Offset + 0x02 Data Length (DL) Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Figure 30-51. AAL1 TxBD Table 30-39 describes AAL1 TxBD fields. Table 30-39. AAL1 TxBD Field Descriptions Offset Bits Name Description 0x00 0 R Ready 0 The buffer associated with this BD is not ready for transmission.
PAGE 999
ATM Controller and AAL0, AAL1, and AAL5 Offset + 0x00 0 1 2 3 R — W I 4 5 — 6 7 10 CM — Offset + 0x02 — Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) 11 OAM 12 15 — Offset + 0x06 Figure 30-52. AAL0 TxBDs Table 30-40 describes AAL0 TxBD fields. Table 30-40. AAL0 TxBD Field Descriptions Offset Bits Name Description 0x00 0 R Ready 0 The buffer is not ready for transmission. The user can manipulate this BD or its buffer.
PAGE 1000
ATM Controller and AAL0, AAL1, and AAL5 30.10.5.14 AAL2 TxBDs Refer to Section 32.3.5.5, “SSSAR Transmit Buffer Descriptor.” 30.10.5.15 AAL5, AAL1 User-Defined Cell—TxBD Extension In user-defined cell mode, the AAL5 and AAL1 TxBDs are extended to 32 bytes; see Figure 30-53. NOTE For AAL0 a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. Offset + 0x08 Extra Cell Header. Used to store the user-defined cell’s extra cell header.
PAGE 1001
ATM Controller and AAL0, AAL1, and AAL5 30.10.7 UNI Statistics Table The UNI statistics table, shown in Table 30-41, resides in the dual-port RAM and holds UNI statistics parameters. UNI_STATT_BASE points to the base address of this table. Each PHY’s own table has a starting address given by UNI_STATT_BASE+ PHY# × 8. Table 30-41. UNI Statistics Table 1 Offset1 Name Width Description 0x00 UTOPIAE Hword Counts cells dropped as a result of UTOPIA/ATM protocol violations.
PAGE 1002
ATM Controller and AAL0, AAL1, and AAL5 the queue. If the CP tries to overwrite a valid entry (V = 1), an overflow condition occurs and the queue’s overflow flag, FCCE[INTOx], is set. The interrupt queue structure is displayed in Figure 30-55. Word INTQ_BASE Software (Core) Pointer INTQ_PTR V=0 W=0 Invalid V=0 W=0 Invalid V=0 W=0 Invalid V=1 W=0 Interrupt Entry V=1 W=0 Interrupt Entry V=1 W=0 Interrupt Entry V=0 W=0 Invalid V=0 W=0 Invalid V=0 W=1 Invalid Figure 30-55.
PAGE 1003
ATM Controller and AAL0, AAL1, and AAL5 Table 30-42. Interrupt Queue Entry Field Description Offset Bits Name Description 0x00 0 V Valid interrupt entry 0 This interrupt queue entry is free and can be use by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. 1 — Reserved, should be cleared. 2 W Wrap bit. When set, this is the last interrupt circular table entry.
PAGE 1004
ATM Controller and AAL0, AAL1, and AAL5 Table 30-43. Interrupt Queue Parameter Table (continued) Offset 1 1 Name Width Description 0x0A INT_ICNT Half Word Interrupt initial count. User-defined global interrupt threshold—the number of interrupts required before the CP issues a global interrupt (FCCE[GINTx]). 0x0C INTQ_ENTRY Word Interrupt queue entry. Must be initialized to the entry pointed to by INTQ_PTR, which is initially the first empty entry of the queue.
PAGE 1005
ATM Controller and AAL0, AAL1, and AAL5 Table 30-44. UTOPIA Master Mode Signal Descriptions (continued) Signal Description TxClav/TxCLAV[3–0] Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a complete cell. TxPRTY Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits. TxCLK Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV, TxPRTY signals.
PAGE 1006
ATM Controller and AAL0, AAL1, and AAL5 30.12.2 UTOPIA Interface Slave Mode In UTOPIA slave mode (single or multiple PHY), cells are transferred using cell-level and octet-level handshakes as defined by the UTOPIA level-2 standard. The FCC allows cell transfer to be halted or paused. If the master negates TXENB, the cell that the FCC is transmitting is halted. If the master negates RXENB, the cell that the FCC is receiving is paused.
PAGE 1007
ATM Controller and AAL0, AAL1, and AAL5 Table 30-45. UTOPIA Slave Mode Signals (continued) Signal Description RxENB Receive enable. Asserted by the master device to signal the slave to sample the RxDATA and RxSOC signals. RxCLAV Receive cell available. Asserted by the ATM controller to indicate it can receive a complete cell. RxPRTY Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA[15–0].
PAGE 1008
ATM Controller and AAL0, AAL1, and AAL5 30.13.1 General FCC Mode Register (GFMR) The GFMR mode field should be programmed for ATM mode. To enable transmit and receive functions, ENT and ENR must be set as the last step in the initialization process. Full GFMR details are given in Section 29.2, “General FCC Mode Registers (GFMRx).” 30.13.2 FCC Protocol-Specific Mode Register (FPSMR) The FCC protocol-specific mode register (FPSMR), shown in Figure 30-59, controls various protocol-specific FCC functions.
PAGE 1009
ATM Controller and AAL0, AAL1, and AAL5 Table 30-47. FCC ATM Mode Register (FPSMR) (continued) Bits Name Description 8 ICD Idle cells discard 0 Discard idle cells (GFC, VPI, VCI, PTI =0) 1 Do not discard idle cells Note: For IMA 1 It is recommended to program ICD=1 so that idle cells will not be discarded. Idle cells should not occur on an IMA link, and their presence indicates an IMA protocol violation.
PAGE 1010
ATM Controller and AAL0, AAL1, and AAL5 Table 30-47. FCC ATM Mode Register (FPSMR) (continued) 1 Bits Name Description 24 TSIZE Transmit UTOPIA data bus size 0 UTOPIA 8-bit data bus size 1 UTOPIA 16-bit data bus size 25 RSIZE Receive UTOPIA data bus size 0 UTOPIA 8-bit data bus size 1 UTOPIA 16-bit data bus size 26 UPRM UTOPIA priority mode. 0 Round robin. Polling is done from PHY zero to the PHY specified in LAST PHY.
PAGE 1011
ATM Controller and AAL0, AAL1, and AAL5 0 4 Field — 5 6 7 8 9 10 11 12 13 14 15 TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0 Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x11310 (FCCE1), 0x0x11330 (FCCE2), 0x0x11350 (FCCE3)/ 0x0x11314 (FCCM1), 0x0x11334 (FCCM2), 0x0x11354 (FCCM3) 16 31 Field — Reset 0000_0000_0000_0000 R/W R/W Addr 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Figure 30-60.
PAGE 1012
ATM Controller and AAL0, AAL1, and AAL5 The first four PHY devices (address 00– 03) on FCC1 and FCC2 have their own transmit internal rate registers (FTIRRx_PHY0–FTIRRx_PHY3) for use in transmit internal rate mode. In this mode, the total transmission rate is determined by FCC internal rate timers. As a master, the controller only polls the PHY’s Clav status at the rate determined by the internal rate. As a slave, the controller attempts to insert cells into the FIFO at the internal rate.
PAGE 1013
ATM Controller and AAL0, AAL1, and AAL5 Example: Suppose the PowerQUICC II is connected to four 155 Mbps PHY devices and the maximum transmission rate is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set according to the highest rate.
PAGE 1014
ATM Controller and AAL0, AAL1, and AAL5 Table 30-50. COMM_INFO Field Descriptions Offset Bits Name Description 0x86 0–4 — 5 CTB 6–10 PHY# 11–12 ACT ATM channel type 00 Other channel 01 VBR channel 1x Reserved 13-15 PRI APC priority level. 000 Highest priority (APC_LEVEL1) 111 Lowest priority (APC_LEVEL8). 0x88 0-15 CC Channel code. The channel code associated with the current channel. 0x8A 0-15 BT Burst tolerance. For use by VBR channels only (ACT field is 0b01).
PAGE 1015
ATM Controller and AAL0, AAL1, and AAL5 samples a new SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz reference clock (for E1/T1) synchronized with the network clock. The PowerQUICC II supports clock recovery using an external SRTS PLL. If SRTS recovery is enabled (RCT[SRT]=1), the PowerQUICC II tracks the SRTS from four incoming cells whose SN field equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in Figure 30-65.
PAGE 1016
ATM Controller and AAL0, AAL1, and AAL5 For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can configure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100 Mbps.
PAGE 1017
Chapter 31 ATM AAL1 Circuit Emulation Service NOTE The functionality described in this chapter is not available on the MPC8250 nor on .29µm (HiP3) rev A.1 silicon. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. This chapter describes implementation of circuit emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the PowerQUICC II and should be used as a supplement to Chapter 30, “ATM Controller and AAL0, AAL1, and AAL5.” 31.
PAGE 1018
ATM AAL1 Circuit Emulation Service – – – – – – – • Segment PDU directly from external memory Partially filled cells support (configurable on a per-VC basis) Sequence number generation Sequence number protection (CRC-3 and even parity) generation Pointer generation during segmentation in structure AAL1 cell format Clock recovery using external SRTS logic during reassembly in unstructured AAL1 Statistics gathering on a per-VC basis: – AAL1 Tx cell count – AAL1 Tx buffer underrun Circuit emulation service (
PAGE 1019
ATM AAL1 Circuit Emulation Service 31.2 AAL1 CES Transmitter Overview The PowerQUICC II supports both structured and unstructured AAL1 cell formats. For unstructured format, the transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data field. For structured format, the transmitter reads 46 or 47 bytes from the external buffer and inserts them into the AAL1 user data field. 31.2.
PAGE 1020
ATM AAL1 Circuit Emulation Service Section 31.4.6, “Channel Associated Signaling (CAS) Support.” The signaling information that resides in the internal RAM is inserted into the AAL1 cell according to the af-vtoa-0078 specification. The AAL1 structure is divided into two sections. The first section carries the Nx64 payload, and the second carries the signaling bits that are associated with the payload.
PAGE 1021
ATM AAL1 Circuit Emulation Service received octet becomes the first byte of the new BD (new super frame). (See Section 31.5, “ATM-to-TDM Adaptive Slip Control,” and Section 31.4, “Interworking Functions.”) Note that when the ATM channel is not in CES mode, no restart sequence is performed; the ATM receiver immediately starts hunting for the first valid cell. The first received octet becomes the first byte of the next BD.
PAGE 1022
ATM AAL1 Circuit Emulation Service Process payload User information Bit count integrity Cell size Unstructured data format Valid/dummy/drop Pointer verification Valid cell Tag cell Drop cell 3-step SN algorithm Invalid SN Valid SN SN/SNP verification AAL1 cell stream Figure 31-4. AAL1 CES Receiver Data flow 31.4 Interworking Functions The PowerQUICC II supports the interworking of ATM and TDM.
PAGE 1023
ATM AAL1 Circuit Emulation Service ATM receiver, set RCT[INVE] of the AAL1 CES-specific areas of the receive connection table; see Section 31.9.1, “Receive Connection Table (RCT).” For the MCC receiver, set CHAMR[EP]. 31.4.1.1 ATM-to-TDM When going from ATM to TDM (depicted in Figure 31-5), the ATM receiver reassembles data received from a particular channel to a specific BD table. The MCC transmitter is programmed to operate on the same table.
PAGE 1024
ATM AAL1 Circuit Emulation Service In order to prevent an overrun condition on the MCC receiver, the ATM transmitter should be programmed to work at a faster rate than the MCC super channel. This ensures that the ATM channel polls the common BD table at a higher rate than it is being filled by the MCC.
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ATM AAL1 Circuit Emulation Service and CESAC reaches the ATM_Start threshold, the receiver’s write pointer is not longer in danger of overrunning the read pointer of the MCC transmitter; that is, it is safe to begin receiving cells again. The ATM receiver then begins the resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer.
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ATM AAL1 Circuit Emulation Service 31.4.5 Trunk Condition According to the Bellcore standard, the interworking function should be able to transmit special payloads on both the ATM and TDM channels to signal alarm conditions (bellcore TR-NWT-000170). The trunk condition can be generated under core control. The core may deliver buffers containing special data (trunk condition payload) to the ATM controller or MCC or even overwrite data buffers being used by the channels. 31.4.
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ATM AAL1 Circuit Emulation Service CAS block per trunk E1 CAS block (32 bytes) T1 – ESF CAS block (24 bytes) 0 XXXX ABCD 0 XXXX ABCD 1 • • • 31 XXXX XXXX • • XXXX ABCD ABCD • • ABCD 1 • • • 23 XXXX XXXX • • XXXX ABCD ABCD • • ABCD T1 – SF CAS block (24 bytes) 0 XXXX ABA’B’ 1 XXXX ABA’B’ • • • XXXX • • XXXX ABA’B’ • • ABA’B’ 23 1 2 ABCD ABCD CAS block resides in the internal RAM.
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ATM AAL1 Circuit Emulation Service F/S=0 One MCC super channel that contains only 4 active channels Slot 1 Slot 0 Slot 2 One ATM CAS routing table ABCD XXXX • • • • • • 0 0 0 0 0 0 0 1 0 1 0 0 0 0 2 23 Slot 23 Example of one MCC super channel in ESF framing (T1) containing 4 TDM slots connected to an ATM channel with one CAS routing table (CRT). See Section 1.4.7.1, “CAS Routing Table.” Figure 31-9. Mapping CAS Entry 31.4.7.
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ATM AAL1 Circuit Emulation Service Table 31-1 describes CAS routing table entry fields. Table 31-1. CAS Routing Table Entry Field Descriptions Bits Name 0 W Wrap bit. When set, this bit indicates the last circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. 1 — Reserved, should be cleared during initialization. 2 F/S First/Second. 0 Indicates that the signaling information occupies the first nibble in the CAS block (LSB).
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ATM AAL1 Circuit Emulation Service The user may use external logic to convert the framer super-frame SYNC to trigger the MCC. The MCC captures the CAS block from the external framer and copies it transparently into one of four internal CAS blocks. Each byte in the CAS block contains a nibble of valid CAS information (depicted in Figure 31-8). Note that the buffer data size should not include the CAS octets. 31.4.7.2.
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ATM AAL1 Circuit Emulation Service the external framer. Each byte in the CAS block contains one nibble of valid CAS information (depicted in Figure 31-8). Note that the buffer data size should not include the CAS octets. 31.4.7.3.1 CAS Updates Using the Core (Optional) To avoid using another TDM dedicated to CAS information, the user can use a parallel interface controlled by the core to deliver the outgoing CAS block to the framer.
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ATM AAL1 Circuit Emulation Service Mode.” In the example shown in Figure 31-14, the MCC is programmed to send the current BD during the pre-underrun condition. The pre-overrun state occurs when the ATM write pointer goes faster than the MCC read pointer. When the adaptive counter reaches the ATM_Stop threshold, the ATM write pointer does not advance. The ATM receiver waits until the adaptive counter reaches the ATM_start threshold.
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ATM AAL1 Circuit Emulation Service 0 7 8 15 Offset + 0x00 — CES Adaptive Counter Offset + 0x02 ATM Stop Threshold ATM Start Threshold Offset + 0x04 MCC Stop Threshold MCC Start Threshold Offset + 0x06 — Figure 31-15. CES Adaptive Threshold Table Table 31-2 describes CES adaptive threshold table fields. Table 31-2. CES Adaptive Threshold Table Field Descriptions Offset1 Bits 0x00 0-7 — 8-15 CESAC CES adaptive counter.
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ATM AAL1 Circuit Emulation Service ATM-to-TDM BD table MCC Tx pointer 0 0 0 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 ATM Rx pointer MCC_Start Step 1: Initialize the MCC and ATM pointers to the same BD table. CESAC=0 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 MCC_Start ATM Rx pointer Step 2: When CESAC reaches MCC_Start, the MCC starts transmitting.
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ATM AAL1 Circuit Emulation Service ATM-to-TDM BD table MCC Tx pointer 0 0 0 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 ATM Rx pointer MCC_Start Step 1: Initialize the MCC and ATM pointers to the same BD table. CESAC=0 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 MCC_Start ATM Rx pointer Step 2: When CESAC reaches MCC_Start, the MCC starts transmitting.
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ATM AAL1 Circuit Emulation Service 31.6 3-Step-SN Algorithm The 3-step-SN algorithm is a fast and efficient state machine that has the ability to recover one lost or misinserted cell. The 3-step-SN algorithm does not add significant delay to the AAL1 CES reassembly process due to the fact that the decision to accept a cell is taken immediately after cell arrival. If a lost cell is detected, the receiver will insert a dummy cell.
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ATM AAL1 Circuit Emulation Service No valid SN Else Hunt mode Valid SN Valid SN ESC=RSC–1/0/1 Sync mode Sync fail Valid SN Invalid SN or out of sequence Figure 31-19. 3-Step-SN-Algorithm 31.7 Pointer Verification Mechanism After the 3-step-SN algorithm processes the incoming cells, the cells status (Valid, Tag, Drop or Dummy) is delivered to the pointer verification mechanism. This state machine calculates the expected received pointer.
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ATM AAL1 Circuit Emulation Service No pointer Hunt mode Valid pointer new structured Valid pointer Sync mode Pointer mismatch/error Missing pointer Pre-hunt mode Valid pointer Pointer mismatch/error Missing pointer Figure 31-20. Pointer verification mechanism 31.8 AAL-1 Memory Structure The CPM manages ATM traffic by means of transmit and receive buffer descriptors (BD) and by transmit and receive connection tables (referred to as TCTs and RCTs, respectively).
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ATM AAL1 Circuit Emulation Service Table 31-3. AAL1 CES Field Descriptions (continued) Offset Name Width Description 0x44 UDC_TMP_BASE Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined. (recommended address space: 3000h-4000h or b000h-c000h) 0x46 INT_RCT_BASE Hword Internal receive connection table base. User-defined. 0x48 INT_TCT_BASE Hword Internal transmit connection table base. User-defined.
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ATM AAL1 Circuit Emulation Service Table 31-3. AAL1 CES Field Descriptions (continued) Offset Name Width Description 0x82 VCI_Filtering Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See Section 30.10.1.2, “VCI Filtering (VCIF).” 0x84 GMODE Hword Global mode.
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ATM AAL1 Circuit Emulation Service Additional CES parameters needed by the AAL1 microcode are described in the following table. Table 31-4. AAL1 CES Parameters Offset Name Width Description 0x4A INT_RTCRT_BASE 0x58 EXT_RTCRT_BASE Word 0xB2 AAL1_INT_RX_CRT Hword (CES only) Points to a reserved scratchpad area of 32 bytes in the dual-port RAM used by the CES microcode. Should be 32 byte aligned. User-defined.
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ATM AAL1 Circuit Emulation Service between transmit and receive connection tables of the same channel is the CRT (CAS routing table); see Section 31.4.7.1, “CAS Routing Table.” Each connection table entry resides in 32 bytes. The pointers to these connection tables reside in the parameter RAM. 31.9.1 Receive Connection Table (RCT) Figure 31-21 shows the format of an RCT entry.
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ATM AAL1 Circuit Emulation Service Table 31-5. RCT Field Descriptions Offset 0x00 0x02 Bits Name Description 0–1 — Reserved, should be cleared during initialization. 2 GBL Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. 3–4 BO Byte ordering—used for data buffers. 00 Reserved 01munged little endian 1x Big endian 5 — Reserved, should be cleared during initialization. 6 DTB Data buffers bus 0 Data buffers reside on the 60x bus.
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ATM AAL1 Circuit Emulation Service Table 31-5. RCT Field Descriptions (continued) Offset Bits Name Description 0x04 — RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer. 0x08 — Cell Time Stamp Used for reassembly time-out. Whenever a cell is received, the PowerQUICC II time stamp timer is sampled and written to this field. See Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” 0x0C — RBD_Offset RxBD offset from RBD_BASE.
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ATM AAL1 Circuit Emulation Service Offset + 0x16 Block Size Offset + 0x18 Super Channel Number — RXBM SLIPIM — SN CASBS Figure 31-22. AAL1 CES Protocol-Specific RCT Table 31-6 describes AAL1 CES protocol-specific RCT fields. Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions Offset 0x0E Bits Name 0–3 SRTS_DEV Selects an SRTS device, whose address is SRTS_BASE[0–27] + SRTS_DEV[28–31]. The 16 byte-aligned SRTS_BASE is taken from the parameter RAM.
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ATM AAL1 Circuit Emulation Service Table 31-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued) Offset 0x12 Bits Name Description 0 SPV Structured pointer valid. Should be user-initialized user to zero. Structured format only. 1–3 — Reserved, should be cleared during initialization. 4–15 SP Structured pointer. Used by the CP to calculate the structured pointer. This field should be initialized by the user to zero. Used in structured format only. 0x14 — RBDCNT RxBD count.
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ATM AAL1 Circuit Emulation Service 31.9.2 Transmit Connection Table (TCT) Figure 31-23 shows the format of an TCT entry. 0 Offset + 0x00 1 — 2 3 GBL 4 5 BO 6 — Offset + 0x02 7 8 DTB BIB 9 — 10 11 ATT 12 13 AVCF VCON — Offset + 0x04 14 15 INTQ AAL Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Offset + 0x08 TBDCNT Offset + 0x0A TBD_OFFSET Offset + 0x0C Rate Remainder PCR Fraction Offset + 0x0E PCR Offset + 0x10 Protocol Specific. Refer to Section 31.9.2.
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ATM AAL1 Circuit Emulation Service Table 31-7. TCT Field Descriptions Offset 0x00 Bits 0–1 Name — Description Reserved, should be cleared during initialization. 2 GBL Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. 3–4 BO Byte ordering. This field is used for data buffers. 00 Reserved. 01 Power PC little endian. 1x Big endian. 5 — Reserved, should be cleared during initialization.
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ATM AAL1 Circuit Emulation Service Table 31-7. TCT Field Descriptions (continued) Offset 0x02 Bits Name 0-12 Description — 13–15 Reserved, should be cleared during initialization. AAL AAL type 000 AAL0 —Reassembly with no adaptation layer 001 AAL1 —ATM adaptation layer 1 010 AAL5 —ATM adaptation layer 5. 100 AAL2 —ATM adaptation layer 2. Refer to Chapter 32, “ATM AAL2.” 101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service All others reserved.
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ATM AAL1 Circuit Emulation Service 31.9.2.1 AAL1 CES Protocol-Specific TCT Figure 31-24 shows the AAL1 CES protocol-specific transmission connection tables (TCT). 0 1 Offset + 0x10 2 — 3 4 5 6 Valid Octet Size (VOS) 7 8 9 PFM SRT 10 11 12 SPIF STF — Offset + 0x12 SRTS_DEV Block Size Offset + 0x14 ICASB/SRTS_TMP Structured Pointer (SP) 13 14 15 SN Figure 31-24. AAL1 CES Protocol-Specific TCT Table 31-8 describes AAL1 CES protocol-specific TCT fields. Table 31-8.
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ATM AAL1 Circuit Emulation Service Table 31-8. AAL1 CES Protocol-Specific TCT Field Descriptions (continued) Offset 0x14 Bits 0–3 Name Description ICASB/SRT ICASB applies when in CAS mode. Incoming CAS Block. Points to one of the eight S_TMP available internal CAS block. The starting address of the table is IN_CAS_BLOCK_BASE+ICASB × 32. See Section 31.4.7.1, “CAS Routing Table” for more details. Note that the RCT and TCT use the same CAS routing table (CRT). SRTS_TMP applies when not in CAS mode.
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ATM AAL1 Circuit Emulation Service 31.11 Buffer Descriptors The AAL1 CES controller operates as a multi-channel protocol, performing simultaneous segmenting and reassembling of transmit and receive data, to and from different sets of memory buffers for all channels. This behavior makes it necessary to have a separate list of BDs for each channel. Each channel is configured with two BD lists: one for transmit and the other for receive operations. The amount of BDs’ in the table is defined by the user.
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ATM AAL1 Circuit Emulation Service BD memory space Pointers from ch 1 entry of TCT TBD_Base TBD_Offset TBD_Base Pointers from ch 4 entry of TCT TBD_Offset Tx BD table of ch 1 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 Tx buffer 1 of channel 1 Tx buffer 3 of channel 1 • • • Tx BD table of ch 4 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 TxBD 7 TxBD 8 TxBD 9 Data memory space Tx buffer 4 of channel 1 Tx buffer 1 of channel 4 Tx buffer 2 of channel 1 • • • Tx buffer 2 of channel 4 Tx buffer 3 of cha
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ATM AAL1 Circuit Emulation Service BD memory space Pointers from ch 1 entry of RCT Data memory space Rx BD table of ch 1 RBD_Base RxBD 1 RxBD 2 RxBD 3 RxBD 4 RxBD 5 RxBD 6 RBD_Offset Rx buffer 1 of channel 1 Rx buffer 3 of channel 1 • • • Rx buffer 4 of channel 1 Rx buffer 1 of channel 4 Rx BD table of ch 4 RBD_Base RxBD 1 RxBD 2 RxBD 3 RxBD 4 RxBD 5 RxBD 6 RxBD 7 RxBD 8 RxBD 9 Pointers from ch 4 entry of RCT RBD_Offset Rx buffer 2 of channel 1 Rx buffer 2 of channel 4 • • • Rx buffer 3 of
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ATM AAL1 Circuit Emulation Service Offset + 0x00 0 1 2 3 4 5 6 E — W I — — CM 7 8 9 — — EOSF Offset + 0x02 Data Length Offset + 0x06 Rx Data Buffer Pointer 10 11 15 — Offset + 0x08 Figure 31-28. AAL1 CES RxBD Table 31-11 describes AAL1 CES RxBD fields. Table 31-11. AAL1 CES RxBD Field Descriptions Offset 0x00 Bits Name Description 0 E Empty. 0 The buffer associated with this RxBD is filled with received data or data reception was aborted due to an error.
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ATM AAL1 Circuit Emulation Service 31.12.2 AAL1 CES TxBDs Figure 31-29 shows the AAL1 CES TxBD. Offset + 0x00 0 1 2 3 R — W I 4 5 — 6 7 CM 8 — 9 10 EOSF Offset + 0x02 Data Length (DL) Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) 15 — Offset + 0x06 Figure 31-29. AAL1 CES TxBD Table 31-12 describes AAL1 CES TxBD fields. Table 31-12.
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ATM AAL1 Circuit Emulation Service Table 31-12. AAL1 CES TxBD Field Descriptions (continued) Offset Bits Name Description 0x02 — DL The number of octets the ATM controller should transmit from this BD’s buffer. It is not modified by the CP. The value of DL should be greater than zero. 0x04 — TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may reside in either internal or external memory. This value is not modified by the CP. 31.
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ATM AAL1 Circuit Emulation Service Table 31-13. AAL1 CES Interrupt Queue Entry Field Descriptions (continued) Offset 0x02 Bits Name Description 9 SLIPS Slip Start.Set when an AAL1 channel enters a slip state (the channel’s adaptive counter reaches the ATM_Stop threshold or the ATM channel loses its SYNC). At this point the receiver drops incoming cells until the adaptive counter reaches the ATM_Start threshold and the channel is resynchronized. See Section 31.6, “3-Step-SN Algorithm.
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ATM AAL1 Circuit Emulation Service 0 15 Offset + 0x00 0x0000 Offset + 0x02 0x0007 Offset + 0x04 0x000D Offset + 0x06 0x000A Offset + 0x08 0x000E Offset + 0x0A 0x0009 Offset + 0x0C 0x0003 Offset + 0x0E 0x0004 Offset + 0x10 0x000B Offset + 0x12 0x000C Offset + 0x14 0x0006 Offset + 0x16 0x0001 Offset + 0x18 0x0005 Offset + 0x1A 0x0002 Offset + 0x1C 0x0008 Offset + 0x1E 0x000F Figure 31-31. AAL1 Sequence Number (SN) Protection Table 31.
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ATM AAL1 Circuit Emulation Service 31.16 External AAL1 CES Statistics Tables An AAL1 CES statistics table, shown in Table 31-15, resides in the external memory and holds AAL1 CES statistics on a per-VC basis. AAL1_Ext_STATT_BASE points to the base address of these tables. Each AAL1 channel has its own table with a starting address given by AAL1_Ext_STATT_BASE + ATM_CHANNEL# × 16. Table 31-15.
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ATM AAL1 Circuit Emulation Service • • • The external framer then places the signaling information at the appropriate position in the super frame. See Section 31.4.6, “Channel Associated Signaling (CAS) Support.” Simple external logic is needed to synchronize the MCC-to-framer serial connection. When going from TDM-to-ATM, the CAS information should be read by the MCC on the 24th frame of a super frame.
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ATM AAL1 Circuit Emulation Service MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 32 ATM AAL2 NOTE The functionality described in this chapter is not available on the MPC8250 nor on rev A.1 .29µm (HiP3) silicon. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. The microcode implementation of the ATM adaptation layer type 2 (AAL2) on the PowerQUICC II is compliant with the ITU-T recommendations I.363.2 and I.366.1.
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ATM AAL2 AAL2 is subdivided into two sublayers, as shown in Figure 32-2: • Common part sublayer (CPS)—In the CPS sublayer, variable length packets coming from multiple users are assembled into CPS-PDUs belonging to a single ATM VC. • Service-specific convergence sublayer (SSCS)—The SSCS sublayer handles the mapping of user data to the CPS sublayer. The SSCS segments large data frames into smaller CPS packets and also provides different services to the user, such as transmission error detection.
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ATM AAL2 UTOPIA PHY4 VP=5|VC=20|CID=13 X VP=27|VC=3|CID=212 UTOPIA PHY7 Figure 32-3. AAL2 Switching Example 32.2 Features The PowerQUICC II’s AAL2 features are as follows: • Fully complies with ITU-T I.363.2 (09/97 and 11/00) and ITU-T I.366.1 (06/98) specifications. • Number of AAL2 external channels supported is subject to internal memory constraints — Each external channel requires space for one Transmit Queue Descriptor in internal memory.
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ATM AAL2 • • • — A separate queue for every VP | VC | CID or a common queue for multiple VP | VC | CID combinations — Receive one or multiple VP | VC | CIDs directly to a specific TX queue to enable switching — Sequence number (SN) protection check for CPS-PDU — CRC5 (HEC) check to detect errors in the CPS-PH of the CPS-Packet — OSF (offset field) of the STF (start of frame) check (a valid value is less than 48) — An SDU length limit parameter (Max_SDU_Deliver_Length) per ATM VC — Odd parity check for t
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ATM AAL2 32.3 AAL2 Transmitter The following sections describe the AAL2 transmitter. 32.3.1 Transmitter Overview A transmitter cycle starts when the APC schedules an ATM channel number for transmission. The TCT is fetched and the AAL type of the channel is checked. For AAL2 cells, the transmitter first handles uncompleted packets from the previous cell of the current CID (partial and split cases) by filling the beginning of the cell with the remainder of the last packet.
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ATM AAL2 • • Round robin (TCT[Fix]=0) Fixed priority (TCT[Fix]=1) The following sections describe the priority options. 32.3.2.1 Round Robin Priority In round robin priority mode, the Tx queues all have equal priority. The transmitter starts with the TxQD pointed to by TCT[FirstQueue], as shown in Figure 32-4. The number of packets that the transmitter services from each queue is determined by the one-packet bit (TCT[OneP]).
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ATM AAL2 TxQD Highest priority queue TCT NextQueue Fix=1 TxQD FirstQueue NextQueue TxQD 0x0000 (null link) Lowest priority queue Figure 32-5. Fixed Priority Mode The TCT[OneP] determines the number of packets that the transmitter attempts to take from each queue (see the explanation in round robin mode). The NextQueue field of the lowest priority TxQD should be cleared (null link), and TCT[MaxStep] should be programmed to the total number of TX queues in the channel.
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ATM AAL2 1. Five packets fit exactly within the PFT limit Cell header AAL2 packet 1 STF AAL2 packet 2 AAL2 packet 3 AAL2 packet 4 AAL2 packet 5 Padding Transmit 0 PFT 2. Because PFT is less than the combined lengths of packet 1, packet 2 and packet 3, the ATM cell is sent only with packets 1 and 2. (Packet 3 will be sent with the next cell.
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ATM AAL2 32.3.5.1 AAL2 Protocol-Specific TCT The transmit connection table (TCT) is a VC-level table and is where the AAL type for the ATM channel number is selected. The parameters related to the ATM channel number or to all the TX Queues of the ATM channel are maintained here. Figure 32-6 shows the AAL2-specific TCT.
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ATM AAL2 . MPC8260 PowerQUICC II Family Reference Manual, Rev.
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ATM AAL2 Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions Offset 0x00 Bits 0–1 Name1 — Description Reserved, should be cleared during initialization. 2 GBL Global. Setting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. 3–4 BO Byte ordering. This field is used for data buffers. 00 Reserved. 01 Power PC little endian. 1x Big endian. 5 — Reserved, should be cleared during initialization. 6 DTB Data buffer bus selection.
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ATM AAL2 Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued) Offset 0x02 Bits 0-11 12 13–15 Name1 — NoSTF AAL Description Reserved, should be cleared during initialization. No STF byte. See Section 32.3.4, “No STF Mode.” 0 Normal AAL2 cell structure. 1 The cell does not include the STF byte. In this mode each cell starts with a new packet and contains only whole packets (no split or partial).
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ATM AAL2 Table 32-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued) Offset 0x1C 0x1E 1 Bits Name1 0–1 — 2–7 PMT 8–15 MaxStep 0-1 — 2–7 PFT 8-11 — Description Reserved, should be cleared during initialization. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT*32. Holds the number of TX Queues visited for each cell being prepared for transmission.
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ATM AAL2 0 7 Offset + 0x00 — 8 9 BNM SW 10 11 12 13 HEC CPS TBM Offset + 0x02 TxBD Table Offset In (switched mode only) Offset + 0x04 TxBD Table Base 15 — Offset + 0x06 Offset + 0x08 TxBD Table Offset Out Offset + 0x0A Number of Packets In Queue Offset + 0x0C NextQueue Offset + 0x0E — Figure 32-7. CPS Tx Queue Descriptor (TxQD) Table 32-2 describes the CPS TxQD fields. . Table 32-2.
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ATM AAL2 Table 32-2. CPS TxQD Field Descriptions (continued) Offset Bits Name1 Description 0x0A — Number of Packets In Queue Counts the number of packets currently in the queue. If this queue is switched, the receiver increments this counter with each new received packet and the transmitter decrements it with each packet sent. For switching, the user should initialize this counter to zero. When this queue is not switched, this counter counts down with every packet sent.
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ATM AAL2 Offset + 0x00 0 1 2 3 R CM W I 4 7 8 — 15 CPS Packet Header Offset + 0x02 CPS Packet Header Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Figure 32-9. CPS TxBD Table 32-3 describes the CPS TxBD fields. . Table 32-3. CPS TxBD Field Descriptions Name1 Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer.
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ATM AAL2 0 7 Channel identifier (CID) 8 13 Length indicator (LI) 14 18 User-to-user ID (UUI) 19 23 Header error check (HEC) Figure 32-10. CPS Packet Header Format 32.3.5.4 SSSAR Tx Queue Descriptor A SSSAR TxBD table and its associated buffers are collectively called an SSSAR TX Queue. Each SSSAR TX Queue is managed by an SSSAR TxQD, as shown in Figure 32-11.
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ATM AAL2 . Table 32-4. SSSAR TxQD Field Descriptions Offset 0x00 Bits 0-7 — Reserved, should be cleared during initialization. BNM Buffer-not-ready interrupt mask of the TxBD table. 0 The transmit buffer-not-ready event for this queue is masked. (The event is not sent to the interrupt queue.) 1 The buffer-not-ready event for this queue is enabled. 9 UUI UUI insertion mode 0 UUI of last CPS packet is 0. 1 UUI of last CPS packet is taken from the next byte after the end of the buffer.
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ATM AAL2 32.3.5.5 SSSAR Transmit Buffer Descriptor The SSSAR buffer structure consists of a BD table that points to data buffers. The buffers may contain SSSAR SDUs belonging to different CIDs. Each buffer may contain a whole SSSAR SDU or part of it. The CPS CID is located in the first BD of the SSSAR SDU. See Figure 32-12. Offset + 0x00 0 1 2 3 4 R CM W I L 5 7 8 — 15 CID Offset + 0x02 Data Length (DL) Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Figure 32-12.
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ATM AAL2 Table 32-5. SSSAR TxBD Field Descriptions (continued) Offset Bits Name1 Description 0x02 — Data Length Contains the length of the buffer associated with this BD. If this is the last buffer (L=1) and the UUI bit in the SSSAR TxQD is set, the 5-bit UUI field is located at (TXDBPTR+Data Length)[3:7] with bit [3] being the msb, that is, in the byte (right justified) immediately following the last byte of the buffer.
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ATM AAL2 The receiver issues an interrupt for each of the above errors.When a SSSAR buffer is closed with RxBD[RxError = US or OS], indicating Uncompleted SDU or Oversized, then RxBD[L] is set, and if RxQD[RFM]=1 then the receiver also issues an RXF interrupt. Then, if no errors have occurred in the packet header, the packet CID is used to match the PHY | VP | VC | CID with an RxQD; see Section 32.4.2, “Mapping of PHY | VP | VC | CID.” The match process yields an RxQD pointer.
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ATM AAL2 • • • RxQD offsets from 8 through 511 point into the internal RxQD table located in dual-port RAM at RxQD_Base_Int. Note that the first 32 bytes of the internal RxQD table are reserved (so offsets 0–7 are reserved). RxQD offsets greater than 511 point into the external RxQD table located at RxQD_Base_Ext + (512*4). Because the three types of RxQDs are different sizes, some offset numbers may not be used.
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ATM AAL2 ATM Rx VC1 ATM Tx VC CID mapping table CID71 TxQD Offset TxBD table Tx buffers TxBD table Tx buffers RxQD table SW=1 Switch RxQD ATM Rx VC2 CID mapping table Switch RxQD TxQD SW=1 CID14 Offset Figure 32-14. AAL2 Switching A partial packet discard mode is provided for the AAL2 switched channels that perform end-to-end SSSAR.
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ATM AAL2 32.4.4.1 AAL2 Protocol-Specific RCT The receive connection table (RCT) is a VC-level table and is where the AAL type for the ATM channel number is selected. The parameters related to the ATM channel number or to all the RX Queues of the ATM channel are maintained here. The RCT also contains the pointer to the CID mapping table for the ATM VC. Figure 32-15 shows the AAL2-specific RCT.
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ATM AAL2 Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions Offset 0x00 0x02 Name 1 Bits Description 0–1 — Reserved, should be cleared during initialization. 2 GBL Global. Setting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. 3–4 BO Byte ordering—used for data buffers. 00 Reserved 01 munged little endian 1x Big endian 5 — Reserved, should be cleared during initialization. 6 DTB Data buffer bus selection. 0 Reside on the 60x bus.
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ATM AAL2 Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions Offset Name 1 Bits 0x04 — 0x06 — 0x08 — 0x0A — 0x0C — 0x0E — 0x10 — 0x12 — 0x14 — 0x16 — 0x18 — CID Mapping Points to the base address of the CID mapping table (see Figure 32-13). Table Base If RCT[MAP] = 0, the pointer contains a dual-port RAM address and only the 16 lsb (at 0x1A and 0x1B) are relevant. If MAP = 1, the pointer is a full 32-bit address in the memory space.
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ATM AAL2 32.4.4.2 CID Mapping Tables and RxQDs Each PHY | VP | VC | CID combination is assigned an RxQD using a CID mapping table. To multiplex several receive CIDs into a single common queue, map each multiplexed PHY | VP | VC | CID combination to one RxQD. The ATM channel’s RCT contains the base address of the associated CID mapping table. This base address is external (32 bits) when RCT[MAP]=1; otherwise, the table resides in the dual-port RAM and the base address is two bytes.
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ATM AAL2 Table 32-7. CPS RxQD Field Descriptions Offset 0x00 Name1 Bits Description 0–11 — Reserved, should be cleared during initialization. 12 RBM Receive buffer mask. 0 Disable receive buffer interrupt. 1 Enable receive buffer interrupt. 13 — Reserved, should be cleared during initialization. 14-15 SubType SubType. Sublayer type, should be 00 (CPS) for this descriptor. 00 CPS sublayer. 01 CPS switched. 10 SSSAR. 11 Reserved.
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ATM AAL2 . Table 32-8. CPS RxBD Field Descriptions Offset 0x00 Name1 Bits Description 0 E Buffer empty bit 0 The CPS RX buffer is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD while E remains zero. 1 The CPS RX buffer is empty or reception is in progress. This is controlled by the CP. Once E is set, the core should not access any fields of this buffer.
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ATM AAL2 0 7 Offset + 0x00 8 11 TX CID — Offset + 0x02 12 13 RBM PPD 14 15 SubType TxQD Pointer Figure 32-18. CPS Switch Rx Queue Descriptor Table 32-9 describes the CPS switch RxQD fields. Table 32-9. CPS Switch RxQD Field Descriptions Offset 0x00 0x02 1 Name1 Bits Description 0-7 TX CID Translation CID. The received CID is saved in a TX Queue with this new CID number. 8-11 — Reserved, should be cleared during initialization.
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ATM AAL2 Table 32-10. Switch RxBD Field Descriptions Offset 0x00 0x02 Name1 Bits Description 0 E/R Buffer Ready Must be set to zero. 1 0 Not valid for switching mode, should be cleared to 0 upon initialization. 2 W Wrap (final BD in table) 0 This is not the last BD in the RxBD table. 1 This is the last BD in the RxBD table of this current channel. After this buffer has been used, the CP receives incoming data for this channel into the first BD in the table.
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ATM AAL2 0 10 Offset + 0x00 — Offset + 0x02 RxBD Table Offset Offset + 0x04 RxBD Table Base 11 12 13 RasT RBM RFM 14 15 SubType Offset + 0x06 Offset + 0x08 — Offset + 0x0A Offset + 0x0c Time Stamp Offset + 0x0e Offset + 0x10 — Offset + 0x12 — Offset + 0x14 MRBLR Offset + 0x16 Max_SSSAR_SDU_Length Offset + 0x18 — Offset + 0x1A Offset + 0x1C Offset + 0x1E Figure 32-20. SSSAR Rx Queue Descriptor Table 32-11 describes the SSSAR RxQD fields. . Table 32-11.
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ATM AAL2 Table 32-11. SSSAR RxQD Field Descriptions (continued) Offset Name1 Bits Description 0x02 — RxBD Table Offset Points to the next BD to be handled by the CP. The user should initialize this pointer to zero. 0x04 — RxBD Table Base Points to the beginning of the BD table. 0x08 — — Reserved, should be cleared during initialization. 0x0A — — Reserved, should be cleared during initialization. 0x0C — Time Stamp Used for reassembly timeout of the SSSAR SDU.
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ATM AAL2 Table 32-12. SSSAR RxBD Field Descriptions Offset 0x00 Name1 Bits Description 0 E Empty 0 The buffer associated with this RxBD is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD and its receive buffer are controlled by the CP. Once E is set, the core should not write any fields of this RxBD.
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ATM AAL2 2 When RAS timer expires the RxBD is closed with RAS timer expired indication, the Last (L) bit is not set, and RXF interrupt is not issued. A new RxBD is opened for the next incoming AAL2 packet and the frame is processed as normal and is treated as a new frame. When the next SSSAR end-of-frame indication is received, the RxBD at that time is closed with an L indication, and if RxQD[RFM] = 1, the receiver issues an RXF interrupt. 32.
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ATM AAL2 Table 32-13. AAL2 Parameter RAM (continued) Offset Name Width Description 0x62 APCP_BASE Hword APC parameters table base address. User-defined. 0x64 FBT_BASE Hword Free buffer pool parameters table base. User-defined. 0x66 INTT_BASE Hword Interrupt queue parameters table base. User-defined. 0x68 — — 0x6A UNI_STATT_BASE Hword UNI statistics table base. User-defined. 0x6C BD_BASE_EXT Word BD table base address extension.
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ATM AAL2 Table 32-13. AAL2 Parameter RAM (continued) Offset Name Width Description 0xA4 EPAYLOAD Word Reserved payload. Initialize to 0x6A6A6A6A. 0xA8 Trm Word (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler (See RTSCR). For time stamp prescalar of 1µs, Trm should be set to 100 ms/1µs = 100,000.
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ATM AAL2 32.6 User-Defined Cells in AAL2 The user-defined cell (UDC) mode for ATM as described in Section 30.7, “User-Defined Cells (UDC),” also applies to AAL2 operation. However, for AAL2 operation only, the UDC headers reside in a table in external memory, not in the BDs. For transmit channels in AAL2 UDC mode, initialize its UDC header entry in the TX UDC header table before activating the channel. The header can be up to 12 bytes.
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ATM AAL2 Offset + 0x00 0 1 2 V — W 3 10 CID Offset + 0x02 11 12 13 14 15 TBNR RXB BSY TXB RXF Channel Code (CC) Figure 32-23. AAL2 Interrupt Queue Entry CID ≠ 0 Table 32-14 describes the interrupt queue entry fields for a CID. Table 32-14. AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions Offset 0x00 0x02 1 Bits Name Description 0 V Valid interrupt entry 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid.
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ATM AAL2 Table 32-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions Offset 0x00 0x02 Bits Name Description 0 V Valid interrupt entry 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. 1 — — 2 W Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set.
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Chapter 33 Inverse Multiplexing for ATM (IMA) NOTE The functionality described in this chapter is available only on the MPC8264 and the MPC8266. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. This chapter provides specifications for the inverse multiplexing for ATM (IMA) microcode. In this chapter, ‘IMA microcode’ and ‘microcode’ are synonymous. 33.1 Features The IMA ATM Forum Specification defines the functions shown in Table 33-1.
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Inverse Multiplexing for ATM (IMA) I Table 33-1.
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Inverse Multiplexing for ATM (IMA) • • • • • — Discards cells with bad HECs (available on .25µm (HiP4) rev B silicon and forward) Delay synchronization--correlating IMA frames among links of a group Maximum differential delay supported is user-programmable Optionally recovers IMA data clock rate (IDCR) Provides interrupts on errors/state changes Maintains low-level statistic counters — Transmit stuff events — Receive stuff events — Receive ICP violations — Receive Out-of-IMA Frame anomalies 33.1.
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Inverse Multiplexing for ATM (IMA) (2) can be programmed not to screen out HEC-errorred cells. Most PHYs have this mode available for IMA also. 33.1.5 ATM Features Not Supported The following ATM features are not available for IMA links only, but are available for non-IMA links: • User-defined cells (UDC) (i.e. cells that are not 53 bytes and/or with customized headers) • Internal rate mode for APC scheduling 33.1.
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Inverse Multiplexing for ATM (IMA) IMA Group IMA Group Single ATM Cell Stream from ATM Layer TC Physical Link #1 + PHY TC + PHY TC Physical Link #2 + PHY TC + PHY TC Physical Link #3 + PHY TC + PHY TC Physical Link #4 + PHY TC + PHY Original ATM Cell Stream to ATM Layer Figure 33-1. Basic Concept of IMA In the transmit direction (near-end), the ATM cell stream received from the ATM layer is distributed on a cell by cell basis, across the multiple links within the IMA group.
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Inverse Multiplexing for ATM (IMA) IMA Frame Length = M cells Link 0 ATM ATM ATM F ICP2 F ATM ATM F ICP1 F F ATM F ICP0 Link 1 F F ICP2 F ATM ATM ATM ICP1 F F M-1 3 F F 2 ICP0 1 0 F ATM F F Link 3 ATM ICP2 F F ATM: ATM Layer Cell ATM F ICP1 ATM F ATM ATM ICPx: IMA Control Protocol Cell ICP0 ATM F: Filler Cell Figure 33-2. Illustration of IMA Frames At the transmitting end, the cells are transmitted continuously.
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Inverse Multiplexing for ATM (IMA) Link ID #1 Cell n+1 Cell 1 Cell n Cell 4 Cell 3 Cell 2 IMA TX Function acting as a Virtual PHY ATM TX Function Links 1 - N make up an IMA group Phy 1 Cell 1 Phy n Cell 1 IMA RX Function acting as a Virtual PHY ATM RX Function Phy 2 Cell n Link ID #N Cell 1 Cell 2 Cell 3 Cell 4 Cell n Cell 2 Fast Communication Controller Cell n+1 Cell 2 Phy 1 Fast Communication Controller Phy 2 Cell n Phy n 33.2.
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Inverse Multiplexing for ATM (IMA) Link ID #1 Cell n+1 Cell 1 Cell n Cell 4 Cell 3 Cell 2 IMA TX Function acting as a Virtual PHY ATM TX Function Links 1 - N make up an IMA group RX Function Cell 2 Fast Communication Controller Phy 2 Cell n Link ID #N Cell 1 Cell 2 Cell 3 Cell 4 Cell n ATM Phy 1 Cell 1 Phy n Cell 1 IMA RX Function acting as a Virtual PHY Cell n+1 Cell 2 Phy 1 Fast Communication Controller Phy 2 Cell n Phy n MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Inverse Multiplexing for ATM (IMA) Link ID #1 Cell n+1 Cell 1 Cell n Cell 4 Cell 3 Cell 2 IMA TX Function acting as a Virtual PHY ATM TX Function Links 1 - N make up an IMA group RX Function Cell 2 Fast Communication Controller Phy 2 Cell n Link ID #N Cell 1 Cell 2 Cell 3 Cell 4 Cell n ATM Phy 1 Cell 1 Phy n Cell 1 IMA RX Function acting as a Virtual PHY Cell n+1 Cell 2 Phy 1 Fast Communication Controller Phy 2 Cell n Phy n MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Inverse Multiplexing for ATM (IMA) IMA Frame ..... Cell n ICP Cell Cell 4 Cell 3 Cell 2 Cell 1 ICP Cell offset should be different for each link. ICP cell offset is determined at start-up. ICP Cell 6 7 8 Cell OAM Cell ID IMA Header Label Link ID FSN 1-5 9 10 11 ICP Link Stat. & cell SI Ctrl CI offset 12 13 14 15 16 17 18-49 50 51 52-53 end to IMA Grp. TX TX TX RX Link ID Stat. & timing test test test info. X end CRC ctrl ptrn. ptrn Ctrl. info ch.
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Inverse Multiplexing for ATM (IMA) 33.3.1.1 • • • • • • User Plane Functions Performed by Microcode ATM cell stream splitting and reconstruction ICP cell insertion/removal Cell rate decoupling (i.e. filler cell insertion/removal) IMA frame synchronization Stuffing Discards cells with bad HECs (available on .25µm (HiP4) rev B silicon and forward) 33.3.1.2 Plane Management Functions Performed by Microcode As stated above, most plane management functions must be performed in software.
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Inverse Multiplexing for ATM (IMA) APC TRL Tx Task N times SAR Tx Queue Tx Queue Tx Queue Tx Queue Jitter Buffers TRL Tx non-TRL Tx Task UTOPIA Multi-PHY Figure 33-5. IMA Transmit Task Interaction 33.3.2.1 TRL Operation A request from the TRL PHY is used to trigger a complete round-robin process of cell scheduling and distribution, distributing one cell for each of the transmit queues of the N links in the IMA group. For each link, the microcode will: 1.
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Inverse Multiplexing for ATM (IMA) At startup, the non-TRL links will transmit filler cells until their transmit queues have reached a minimum depth. In order to maintain less than the specified maximum +/-2.5 cell transmit timing differential (for cells within an IMA frame), the TRL must exhibit the same behavior. Therefore, a 4-cell transmit buffer is also maintained for the timing reference link.
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Inverse Multiplexing for ATM (IMA) At group start-up, instead of accessing its transmit queue, the link will send filler cells. This is to allow the transmit queues to reach their target steady-state depth. After the group start-up flag is cleared, normal operation as described above will commence. 33.3.2.3 Transmit Queue Operation Examples (ITC mode) The following diagrams demonstrate the different cases of queue operation, and consequently justify the queue depth of 5 cells.
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Inverse Multiplexing for ATM (IMA) Tx Queue Queue insertion pointer creeps up such that it floats between these two positions (wrapped) Depth is 4.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Queue insertion pointer TRL stuff event happens, so this link is not given a cell during round robin. Depth ratchets down to normal operation of 3.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Figure 33-8.
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Inverse Multiplexing for ATM (IMA) Tx Queue TRL stuff event occurs and this link is not given a cell during a round robin pass. Depth decreases to 2.x “imminent stuff” flagged Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Normal ‘Wander zone’ Before stuff event can happen, queue depth creeps down below 2.x threshold to 1.x Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Stuff event occurs, bringing queue depth back to 2.
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Inverse Multiplexing for ATM (IMA) 2. The non-TRL tasks do not determine when to perform stuffing on the non-TRL links. When the TRL flags ‘imminent stuff’ on its own link, it will flag ‘imminent stuff’ on all of the non-TRL links as well. Thus, the non-TRL links will also stuff their links every 2048 cells. 3. The non-TRL queue depths are the same as the TRL’s queue (i.e. 4 cells). 33.3.3 Receive Architecture The receive task consists of three parts. The first part is for cell reception from the link.
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Inverse Multiplexing for ATM (IMA) received cells (and other event indications) are used by the software to initialize IMA links and groups, and to manage transitions between link and group states. The cell reception task centers around a four-state link state machine. Microcode tasks are performed within each state, but transitions between states are managed by software. The processing of received cells (both ICP cells and data cells) is determined by the state of the link.
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Freescale Semiconductor - data ATM cell reception enable - “Added Link Delay Synchro Algo” OR - “New Group Link Delay Synchro Algo” - look for several lCP cells in expected position - search for one ICP cell - screen incoming cells - keep only ICP cells, discard other cells - screen incoming cells Microcode Actions - Group & Link initialized by the driver based on the ICP content ( Link’s M value, ICP frame format) Configuration to reach to move to next state IFSW INT generated (IMA_event) to t
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Inverse Multiplexing for ATM (IMA) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Inverse Multiplexing for ATM (IMA) Figure 33-11. IMA Microcode: Receive Process MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Inverse Multiplexing for ATM (IMA) The states are described as follows: • Group Unassigned—This corresponds to a link which is known to be IMA, but for which no information is known (e.g. IMA group number, IMA frame size). In this state, the receive task only screens the incoming cells for ICP cells and discards all others.
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Inverse Multiplexing for ATM (IMA) • The system is only capable of carrying services that either do not require CDV control (e.g. some data services), or where the CDV is handled in some other way (e.g. absorbed in a play-out buffer at the ATM layer connection termination). The PowerQUICC II may qualify as such a system, if the PowerQUICC II terminates all ATM connections that it receives. The buffer-descriptors and external memory serve as a play-out buffer.
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Inverse Multiplexing for ATM (IMA) available in its delay compensation buffers, then the group is determined to have stalled and an error interrupt is provided to software. 33.3.3.3 Cell Processing Task The cell processing task is triggered by the cell processing activation function. When the cell processing task is triggered, it will extract cells in-order from the delay compensation buffers.
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Inverse Multiplexing for ATM (IMA) IMA Root Table Filler Cell Template Transmit Queue Info IMA Group Tx Table IMA Data Structures Group 0 DCBs, TX Queue . . . IMA Control Parameter PHY Management External memory (Local or 60x Bus) must be aligned to 1MByte Boundary. Group 7 IMA Group Rx Table IMAEXTBASE Group 0 IMAGRPT_TX . . . IMAGRPT_RX Group 7 IMALINKT_TX Link 0 . . .
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Inverse Multiplexing for ATM (IMA) 33.4.2 33.4.2.1 33.4.2.1.1 IMA FCC Programming FCC Registers FPSMRx The FCC protocol-specific mode register (FPSMR) for ATM operation is described in Section 30.13.2, “FCC Protocol-Specific Mode Register (FPSMR).” Refer to that section for information pertaining to IMA. 33.4.2.1.2 FTIRRx For any PHY programmed in IMA mode (i.e. corresponding bit in IMAPHY is set), the corresponding FTIRRx must be programmed to zero, for external rate mode.
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Inverse Multiplexing for ATM (IMA) NOTE IMAROOT must be programmed to a 128-byte aligned address terminating with 0x80 (i.e. 0xnn80). 33.4.3 IMA Root Table Table 33-3. IMA Root Table1 Offset Name Width Description 0x04 IMAFILLERHD2 0x00– 0x2F IMAFILLERPLD 0x30 FILLTAG Byte Tag indicating that the filler template is a filler cell. Program to zero. 0x31 TQ_SIZE Byte Transmit queue size. Recommended value is 0x18. Must be a multiple of 4. Refer to Section 33.4.6.
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Inverse Multiplexing for ATM (IMA) Table 33-3. IMA Root Table1 (continued) Offset Name Width Description 0x3C TXPHYEN Word Transmit PHY enable. Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0). Setting a bit enables transmission for the corresponding PHY. Must be used to enable/disable the corresponding PHY regardless of whether or not the PHY is defined as IMA in IMAPHY. Only idle/unassigned cells are transmitted on disabled PHYs.
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Inverse Multiplexing for ATM (IMA) 2 IMAFILLERHD is located at the word which immediately precedes the 128-byte aligned region defined by IMAROOT. Thus it is located at offset - 0x04 from base of IMAROOT table. 33.4.3.1 IMA Control (IMACNTL) The fields of the IMACNTL are shown in Figure 33-13. 0 Field 1 — 2 3 4 5 IRSE IQB DSB — 6 7 INTQ Figure 33-13. IMA Control (IMACNTL) Table 33-4 describes the IMACNTL bit fields. Table 33-4.
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Inverse Multiplexing for ATM (IMA) 33.4.4.1 IMA Group Transmit Table Entry Table 33-5. IMA Group Transmit Table Entry 1 Offset Name Width Description 0x00 IGTCNTL Byte IMA group transmit control parameters. 0x01 IGTSTATE Byte IMA group transmit state. Microcode-managed parameter. Must be initialized to zero at group start-up. 0x02 TGRPORDER Hword Offset of transmit group order table in DPRAM. Can be changed on the fly. 0x04 TVPHYNUM Byte Transmit Virtual PHY number.
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Inverse Multiplexing for ATM (IMA) Table 33-5. IMA Group Transmit Table Entry (continued)1 Offset Name Width Description 0x0E IASNCCtr Byte Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells Counter - Number of cells passed to the groups links upon request. Initialize to IASNC. 0x0F IASNC Byte Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells - reset for IASNCtr.
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Inverse Multiplexing for ATM (IMA) Field 0 1 2 3 4 5 6 7 TSTF TIMSTf GTE TRQS ELX — ICH ICPCA Figure 33-15. IMA Group Transmit State (IGTSTATE) Table 33-7 describes the IGTSTATE bit fields. Table 33-7. IGTSTATE Field Descriptions Bits Name Description 0 TSTF TRL stuff flag. Microcode-managed parameter. Indicates that the next ICP cell on the TRL will be part of a stuff event. Initialize to zero at group startup. 1 TIMSTF TRL imminent stuff flag. Microcode-managed parameter.
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Inverse Multiplexing for ATM (IMA) Table 33-8. Transmit Group Order Table Entry Field Descriptions Bits Name Description 0–2 — Reserved 3–7 PHY ADDRESS PHY address (Up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin. A value of 0x1F in this field indicates the end of the group order table. 33.4.4.1.4 ICP Cell Templates The ICP cell templates are areas of memory provided by software to the microcode for construction of ICP cells for transmission.
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Inverse Multiplexing for ATM (IMA) Table 33-9.
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Inverse Multiplexing for ATM (IMA) Table 33-9.
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Inverse Multiplexing for ATM (IMA) 33.4.4.2 IMA Group Receive Table Entry Table 33-10. IMA Group Receive Table Entry 1 Offset Name Width Description 0x00 IGRCNTL Byte IMA group receive control parameters. 0x01 IGRSTATE Byte IMA group receive state. Microcode-managed parameter. Initialize to zero at group startup. 0x02 RIMAID Byte Receive IMA ID. Program to the validated receive IMA ID value. 0x03 IMAVER Byte IMA version. Program to the validated IMA version value. 1 IMA Version 1.
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Inverse Multiplexing for ATM (IMA) Table 33-10. IMA Group Receive Table Entry (continued)1 Offset Name Width Description 0x16 TRLR Hword TRL rate. Used only when IDCR-regulated cell processing is used (i.e. IGRCTNL[IDCR]=1). Calculated by microcode during group startup, prior to group activation. Referenced by software in order to program the IDCRREQ and IDCRREQF of the group’s IDCR table entry. Value is valid after IGRSTATE[IDCR_DN] is set by the microcode.
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Inverse Multiplexing for ATM (IMA) Table 33-10. IMA Group Receive Table Entry (continued)1 Offset Name Width Description 0x2A STALL_THR Byte Stall threshold. Used to detect stalled links when performing round-robin cell extraction from the delay compensation buffers (Dcbz). This is the number of cells which may be received without advancing the cell extraction pointer. The value is application-dependent and must be tuned by the user to the “expected worst case.
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Inverse Multiplexing for ATM (IMA) Table 33-11. IGRCNTL Field Descriptions Bits Name Description 0 GOTP Group order table pointer. Defines which group order table pointer (RGRPORDER0 or RGRPORDER1) will be used for the cell extraction round-robin. Initialize to zero at group startup. 1–2 — Reserved, initialize to zero. 3-4 RXSC Receive status/control. Sets the receive mode of the IMA group. 00 Filler mode. The IMA group processes only ICP cells. Data cells are replaced with filler cells.
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Inverse Multiplexing for ATM (IMA) 0 Field 1 6 0 — 7 GSC-M Figure 33-19. IMA Receive Group Frame Size (IGRSTATE) Table 33-13 describes the IRGFS bit fields. Table 33-13. IRGFS Field Descriptions Bits Name Description 0 0 Reserved, initialize to zero. 1-5 — Reserved, initialize to zero. 6-7 GSC-M IMA Receive Group Frame Size Bits 0-5: Reserved Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field (Bits 1:0) which determine the IMA frame size.
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Inverse Multiplexing for ATM (IMA) Table 33-14. Receive Group Order Table Entry Field Descriptions Bits Name Description 0–2 — Reserved, initialize to zero. 3–7 PHY ADDRESS PHY address (up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin. A value of 0x1F in this field indicates the end of the group order table. 33.4.5 IMA Link Tables The IMA link tables consist of multiple IMA group structures indexed by the PHY address of their corresponding PHYs.
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Inverse Multiplexing for ATM (IMA) Table 33-15. IMA Link Transmit Table Entry (continued)1 Offset Name Width Description 0x0C ITQFP Hword IMA link transmit queue fill pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Initialize this to the value of ITQSP. Refer to Section 33.4.6.1, “Transmit Queues.” 0x0E ITQXP Hword IMA link transmit queue extract pointer.
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Inverse Multiplexing for ATM (IMA) Table 33-16. ILTCNTL Field Descriptions (continued) Bits Name Description 3-4 TXSC Transmit status/control. Sets the transmit mode of the IMA link. 00 Filler mode. The IMA link transmits only ICP and filler cells, no data cells. 01 Active mode. The IMA link is capable of sending data cells. 1X Reserved. 5-7 IGNUM Determines to which IMA group this link belongs. Contains the number of the link’s associated IMA Group Table entry.
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Inverse Multiplexing for ATM (IMA) Table 33-18 describes the ITINTSTAT bit fields. Table 33-18. ITINTSTAT Field Descriptions Bits Name Description 0-3 — Reserved, initialize to zero. 4 PTQO Persistent transmit queue overflow. Set when a transmit queue overflow occurs for two cells in a row. Further transmit queue overflow events are masked when this bit is set, in order to avoid a ’flood’ of interrupts.
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Inverse Multiplexing for ATM (IMA) Table 33-19. IMA Link Receive Table Entry1 (continued) Offset Name Width Description 0x07 DFC Byte Number of frames to discard on a this link until it is caught up with the other links in this group (long propagation delay). Microcode-managed parameter. 0x08 DCBSP Hword IMA link delay compensation buffer start pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Refer to Section 33.4.6.
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Inverse Multiplexing for ATM (IMA) 1 Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 33.4.5.2.1 IMA Link Receive Control (ILRCNTL) The fields of the ILRCNTL register are shown in Figure 33-24 Field 0 1 2 GA SES TRL 8 9 10 Field Add_new 3 4 5 RXSC 7 IGNUM 15 MON_ICP — Figure 33-24.
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Inverse Multiplexing for ATM (IMA) 33.4.5.2.2 IMA Link Receive State (ILRSTATE) The fields of the ILRSTATE register are shown in Figure 33-25 0 1 Field ADD_NEW_M 8 Field icp_cell 2 3 4 5 MASK_ERR STFEX SU 11 12 13 SYNC_DeFeCT STFIP DL IFSS 9 10 FSES 6 7 CHK_NXT DATA_ERR 14 15 — Figure 33-25. IMA Link Receive State (ILRSTATE) Table 33-21 describes the ILRSTATE bit fields. Table 33-21. ILRSTATE Field Descriptions Bits Name Description 0 ADD_NEW_M New Link shadow bit.
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Inverse Multiplexing for ATM (IMA) 33.4.5.3 IMA Link Receive Statistics Table The IMA link receive statistics table is optional. It is enabled globally for this FCC via IMACNTL[IRSE]. The base of this table is determined by IRLINKSTAT. Entries in the table are indexed by the link number of the associated link. The format for the IMA link receive statistic table entries is shown in Table 33-22 Table 33-22.
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Inverse Multiplexing for ATM (IMA) 33.4.6.2 Delay Compensation Buffers (DCB) Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs are allocated on a per-link basis. They are of user-definable length, thereby providing a programmable maximum synchronizable delay. Note that DCBs of links within a group must all have the same size. DCBs consist of a circular queue of 64-byte cell buffers.
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Inverse Multiplexing for ATM (IMA) IMA events sent to this queue include only those described in this section. ICP receive events are treated as normal receive events, and should therefore go to the interrupt queue allocated for receive events. 33.4.7.1 IMA Interrupt Queue Entry The format for the IMA interrupt queue entries is shown in Figure 33-29 OFFSET + 0 0 1 2 V — W OFFSET + 2 L/G 3 5 — 6 7 TQU TQO 8 9 10 — DSL LS 11 12 13 14 15 DCBO LDS GDS IFSD IFSW NUM Figure 33-29.
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Inverse Multiplexing for ATM (IMA) Table 33-23. IMA Interrupt Queue Entry Field Descriptions Offset Bits Offset + 0 0 Description V Valid interrupt entry. 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. 1 — Reserved. 2 W Wrap bit.When set, this is the last interrupt circular table entry.
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Inverse Multiplexing for ATM (IMA) 33.4.8 IDCR Timer Programming Programming of the IDCR timer data structures is optional. It is only required if any of the IMA groups use IDCR-regulated cell processing. Only one IDCR master clock per FCC is supported; the IDCR timers for the individual groups are derived from the IDCR master clock. Each IDCR timer has an associated IDCR table entry, indexed by the IMA group number. 33.4.8.
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Inverse Multiplexing for ATM (IMA) Table 33-24. Unavailable Features when DREQx used as IDCR Master Clock IDCR Master Clock DPRAM Page PowerQUICC II Features Not Available DREQ1 8 MCC1, SMC1, and IDMA1 are unavailable. DREQ2 9 MCC2, SMC2, and IDMA2 DREQ3 10 SPI and IDMA3 DREQ4 11 RISC Timers, Microcode Rev Num, Random Number Generator function and IDMA4 33.4.8.2.
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Inverse Multiplexing for ATM (IMA) 33.4.8.3 IDCR_Init Command The IDCR_Init command is a host command issued to the CPCR (refer to Section 14.4.1, “CP Command Register (CPCR)”). This command selects and configures the IDMA request which will be used for the IDMA master clock. Any of the IDMA channels may be selected for this function. The format of the command is as follows: • SBC = [per the selected IDMA channel] • OPCODE = 0x00 • PAGE = [per the selected IDMA channel] 33.4.8.
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Inverse Multiplexing for ATM (IMA) Table 33-26. IDCR Table Entry Offset Name Width Description 0x04 IDCRREQ Hword IDCR request rate. Program to [TRLR/(RNUMLINKS x 128)] x (2048/2049). 0x06 IDCRREQF Hword IDCR request rate fraction. Holds the fractional portion of the IDCR request rate, represented as (IDCRREQF / 65536). 33.4.8.6 IDCR Counter Algorithm The IDCR count of each enabled IDCR timer is decremented each tick of the IDCR master clock.
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Inverse Multiplexing for ATM (IMA) Table 33-27. IDSR/IDMR Field Descriptions (continued) Bits Name Description 6 INTO1/ GRLI INTO1: Interrupt queue overflow 1. See INTOx above. GRLI: Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set in the free buffer pool’s parameter table. 7 INTO0/ GBPB INTO0: Interrupt queue overflow 1. See INTOx above. GBPB: Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set.
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Inverse Multiplexing for ATM (IMA) Table 33-28. Examples of APC Programming for IMA Example Description 4 Assume that one link is dropped from the IMA group in Example 4. The overall bandwidth of the group is now 8Mbps, and TNUMLINKS becomes 4. Therefore, the pace for the 6Mbps CBR channel described above scales to 4/3 (PCR=1, PCR_Fraction=84), indicating that the channel will use 75% of the bandwidth of the group, which is still 6Mbps.
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Inverse Multiplexing for ATM (IMA) 33.4.10 Changing IMA Version A new CPCR command has been added to the IMA microcode to change the IMA version on-the-fly without software intervention. Use the following procedure: 1. Before issuing the command, the user should initialize the COMM_INFO fields in the parameter RAM as described in Figure 33-31. 2. To issue this FCC command, refer to Section 14.4, “Command Set.” Use opcode 1110(0xE).
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Inverse Multiplexing for ATM (IMA) Tx ICP Template ICP Cells Link 1 Interrupts Layer Management IMA Parameters IMA Tx Microcode Routine Link n Host Software Link 1 Plane Management Interrupts IMA Rx Microcode Routine Rx ICP Channel Link n ICP Cells Figure 33-32. IMA Microcode/Software Interaction 33.5.2 Initialization Procedure 1. Program FCC registers/parameters for ATM operation with UTOPIA multi-PHY (excluding APC parameters for IMA PHYs). 2. Program IMA FCC and root parameters. 3.
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Inverse Multiplexing for ATM (IMA) 33.5.3.2 • • React to received ICP cells. ICP cells are only received when their SCCI field changes, except the first received ICP cell Report any NE and FE timing mode mismatches (ITC vs. CTC) to the Unit Management 33.5.3.
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Inverse Multiplexing for ATM (IMA) 33.5.3.
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Inverse Multiplexing for ATM (IMA) 33.5.3.11 Test Pattern Control • • Initiate transmit test patterns in the group’s transmit ICP cells (via TXTC and TXTP), and monitor response in the receive ICP cells of the associated receive group Respond to test patterns by: — Recognizing test pattern activity in the received ICP cells — Locating the Tx Test Pattern field in the ICP cell of the test link.
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Inverse Multiplexing for ATM (IMA) of ICP cells requires that the corresponding PHYs (i.e., links) have been enabled and the corresponding connection table entry/entries initialized (see RXPHYEN, IMAPHYEN, and RICPH). In “group unassigned” mode, the first received ICP cell will always be reported to the corresponding channel’s buffer (RICPCH) and subsequently every time there is a change in the SCCI (Status and Control Change Indication) field of the ICP cell. • Set ILRCNTL[GA] to 0 (zero).
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Inverse Multiplexing for ATM (IMA) • Set IGRSTATE[GDSS] to 1 (one) to enable GDS. Once group delay synchronization is achieved, a “GDS” exception is generated. At this point, ATM stream reconstruction can take place. In order for stream reconstruction to be performed by the PowerQUICC II, the user must switch all links and corresponding group (both directions) to “active” mode (i.e., capable of receiving data cells).
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Inverse Multiplexing for ATM (IMA) Tx ICP Template TX GSM/ LSM Near-end PowerQUICC II RX ICP buffer Tx ICP Template TX Far-end PowerQUICC II GSM/ LSM RX ICP buffer Figure 33-33. Near-End versus Far-End 33.5.4.3.2 As Responder (RX) The IMA GSM/LSM software will receive ICP cells in the ICP buffer conveying the state of the FE’s group and links.
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Inverse Multiplexing for ATM (IMA) 2. 3. 4. 5. 6. 7. Assign corresponding group number for the new link: ILRCNTL[IGNUM] = x. Assign channel number for ICP cell reception: RICPCH = x. Enable desired interrupts: IRINTMSK = x Allow for the reception of ICP cells during the IFSM stage: ILRCNTL[MON_ICP] = 1. Indicate that this link has not yet been assigned to a group: ILRCNTL[GA] = 0. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in IMAPHY. See Table 33-3. 8.
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Inverse Multiplexing for ATM (IMA) 5. 6. 7. 8. 9. Program the Link’s ID (LID) in the IMA Link Transmit Table Entry (ILTTE): ILID = x. Program the ICP offset (ILTTE): LICPOS = x. Initialize the Transmit Queue pointers accordingly: ITQSP, ITQEP, ITQFP, and ITQXP. Construct the new TX Group Order Table (includes the added/new link). Point to new TX Group Order Table in the corresponding IMA Group Transmit Table Entry (IGTTE): TGRPORDER = New Table Offset. 10.
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Inverse Multiplexing for ATM (IMA) 8. Inhibit reception of cells over dropped link in the IMA Root Table: RXPHYEN &= ~x (i.e., clear the corresponding link bit in the RXPHYEN entry). Note, you must reenable (set to 1) the corresponding bit at a later point if you wish to use this link as a non-IMA link. 9. Software should wait (poll) for the PowerQUICC II to be using the new group order table. This simply ensures that it is safe to modify/re-use the dropped link parameters (i.e.
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Inverse Multiplexing for ATM (IMA) 5. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2. 6. Software should wait (poll) for the PowerQUICC II to remove the link from the DCB routine. The corresponding bit in the group table’s LINK_DCB entry will be cleared by the PowerQUICC II (IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB != REF_LINK). 7. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x. 8.
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Inverse Multiplexing for ATM (IMA) 33.5.4.9 Transmit Event Response Procedures The following TX events may take place when operating in IMA mode. It is recommended that all events be handled via an “exception/interrupt service routine” (ISR) as the response time inherent with interrupt driven events should diminish the negative impact/propagation of such events: 1. TQU (Transmit Queue Underrun)—Indicates that a transmit queue was emptied.
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Inverse Multiplexing for ATM (IMA) 4. GDS (Group Delay Synchronized)—Group delay synchronized achieved or group delay synchronized not achieved. In some cases, it is not possible for the GDS to complete. GDS can not complete if a link experiences problems during the GDS process - for example losing SYNC state for the IFSM. If this occurs, it is not possible to determine the links true differential delay with respect to other member links of the group.
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Inverse Multiplexing for ATM (IMA) 33.5.4.11 Test Pattern Procedure Test patterns are used verify “connectivity” of a link in a particular group. The NE will request, via an ICP cell, that a test pattern be looped back to the FE over all links currently in the group. For this test, the FE will look only at ICP cells received over the link being tested (LID = x) and upon receiving an ICP cell “echo” the pattern back to the NE over all the links in the group.
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Inverse Multiplexing for ATM (IMA) for the first link encountered in which a change (SCCI) is detected, it may or may not be the link under test. An alternate method is to monitor only the link under test: 1. Don’t Monitor link for changes in SCCI for all links except link under test: ILRCNTL[MON_ICP] = 0 (alter the corresponding Link Table Entries). 2. Monitor link under test for changes in SCCI: ILRCNTL[MON_ICP] = 1.
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Inverse Multiplexing for ATM (IMA) 9. Program to appropriate rate and enable timer if using a BRG (refer to Chapter 17, “Baud-Rate Generators (BRGs)”): TMRx, TRRx, and TGCRx. Note: This is only required if the IDCR clock is supplied by the PowerQUICC II. If an external source is used, this step can be skipped. An external connection (physical) is required between the output of the BRG (TOUTx) and DREQx (see step 7 above). 10. Enable IDMAx interrupts (refer to Section 19.8.
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Inverse Multiplexing for ATM (IMA) 33.5.4.13.2 Receive No special facility is included for reception of the end-to-end channel. The end-to-end channel field is part of the received ICP cells, so its information can be read by software from those cells. However, ICP cells are only received when the SCCI field changes, so changes in the end-to-end channel will not be received until the SCCI field also changes (when there is a change in the status and/or control of the far end).
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Inverse Multiplexing for ATM (IMA) MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Chapter 34 ATM Transmission Convergence Layer NOTE The functionality described in this chapter is available only on the MPC8264 and the MPC8266. The PowerQUICC II can support applications which receive ATM traffic over the standard serial protocols like E1, T1, and xDSL via its serial interface (SIx TDMx) ports because the ATM TC-layer functionality is implemented internally. This allows the use of standard low-cost PHY devices in system applications instead of PHYs that support UTOPIA bus devices.
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ATM Transmission Convergence Layer • • • • • — Protocol-specific overhead bits may be discarded or routed to other controllers by the SI — Performing ATM TC layer functions (according to ITU-T I.
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ATM Transmission Convergence Layer • • • 34.2 Cell counters for performance monitoring: — 16-bit counters count: – HEC errored cells – HEC single bit errored and corrected cells – Idle/unassigned cells filtered – Idle/unassigned cells transmitted – Transmitted ATM cells – Received ATM cells — Maskable interrupt sent to the host when a counter expires Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt May be operated at E1 and DS-1 rates.
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ATM Transmission Convergence Layer 60x Bus PowerQUICC II Registers FCC2 Rx Cell Functions Rx Serial I/F Rx FIFO • cell delineation • descrambling • coset • HEC error detection and correction M-PHY UTOPIA Rx I/F Rx Rx UTOPIA I/F (PHY) Counters Tx Tx Cell Functions Tx FIFO M-PHY UTOPIA Tx I/F Tx Serial I/F • HEC generation • scrambling • coset • rate adaptation Tx UTOPIA I/F (PHY) SI PHY one channel TC Layer Figure 34-2. TC Layer Block Diagram 34.2.
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ATM Transmission Convergence Layer SYNCH state, the TC is assumed to be synchronized so that other functions can be applied to the received cell. A transition back to the HUNT state is made only after ALPHA consecutive incorrect HEC patterns are detected. The cell delineation state machine is shown in Figure 34-3. The ALPHA and DELTA parameters determine the robustness of the delineation method. ALPHA determines the robustness against false misalignment due to bit errors.
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ATM Transmission Convergence Layer Multi-bit error detected (Cell discarded) No error detected (No action) Correction Mode No error detected Detection Mode Error detected (Cell discarded) Single-bit error detected (correction) Figure 34-4. HEC: Receiver Modes of Operation The RCF can also perform idle/unassigned cell filtering. Both features are programmable (TCMODE[CF]). Cells that are detected to be idle/unassigned are discarded, that is, not forwarded to the UTOPIA interface Rx FIFO. 34.2.1.
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ATM Transmission Convergence Layer The FIFO management includes emptying cells from the transmit FIFO, indicating to the UTOPIA interface that it is full, maintaining the FIFO read and write pointers, and detecting FIFO underrun (TCER[UR]) conditions. 34.2.3 Receive UTOPIA Interface This block performs the receive interface with the FCC via the UTOPIA bus. It implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface. 34.2.
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ATM Transmission Convergence Layer 0 1 Field RXEN 2 TXEN RPS 3 4 5 6 TPS RC TC SBC Reset 7 8 CF 9 10 URE 11 LB 12 13 14 15 TBA IMA SM CM 0000_0000_0000_0000 R/W R/W Figure 34-5. TC Layer Mode Register (TCMODEx) Table 34-2 describes TCMODE fields. Table 34-2. TCMODEx Field Descriptions Bits Name Description 0 RXEN TC Layer Rx enable bit. Enables the TC Layer Rx block operation: 0 TC Layer Rx operation is disabled. 1 TC Layer Rx operation is enabled.
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ATM Transmission Convergence Layer Table 34-2. TCMODEx Field Descriptions (continued) Bits 10–11 Name LB Description Loopback/echo modes 00 Normal operation. 01 Cell echo mode operation. Received cells are transmitted and do not go out to the UTOPIA bus. 10 Data loopback mode operation. Transmit data stream is connected to the receive data stream. 11 Not used. Note that for echo mode operation, TCMODE[SM] should be cleared, independent of the FCC multi-PHY mode configuration.
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ATM Transmission Convergence Layer 34.4.1.3 TC Layer Event Register [1–8] (TCERx) The TC layer event registers (TCERx), as shown in Figure 34-7, records error events for each TC block. TCER event bits are cleared by writing ones to them. Field 0 1 2 3 4 OR UR CDT MS PARE Reset 5 9 — 10 ROF 11 12 13 TOF EOF COF 14 15 IOF FOF 0000_0000_0000_0000 R/W R/W Figure 34-7. TC Layer Event Register (TCERx) The TCER bits are described in Table 34-4. Table 34-4.
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ATM Transmission Convergence Layer 34.4.1.4 TC Layer Mask Register (TCMRx) This register’s field description is identical to that of TCER (refer to Section 34.4.1.3, “TC Layer Event Register [1–8] (TCERx)”). Each bit that is set in TCMR enables an interrupt when the corresponding bit in TCER is set. 34.4.2 TC Layer General Registers The TC layer general registers are registers that are distributed to all of the TC blocks. Each TC block is represented by specific bits.
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ATM Transmission Convergence Layer 0 Field CD1 1 2 3 4 5 6 7 CD2 CD3 CD4 CD5 CD6 CD7 CD8 Reset 8 15 — 0000_0000_0000_0000 R/W R Figure 34-9. TC Layer General Status Register (TCGSR) Table 34-6 describes TCGSR fields. f Table 34-6. TCGSR Field Descriptions Bits Name Description 0–7 CDx Cell Delineation. The cell delineation state machine status of TCx. 0 Cell delineation state machine is in Hunt or Pre-Synch modes. 1 Cell delineation machine is in Synch mode.
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ATM Transmission Convergence Layer 34.4.3.6 Filtered Cell Counter [1–8] (TC_FCCx) This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are not enabled (TCMODE[CF] is cleared), this counter is not updated. 34.4.4 Programming FCC2 FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the UTOPIA bus internally.
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ATM Transmission Convergence Layer The TC layer requests ATM cells for transmission via the internal UTOPIA interface. Then, when the ATM cell is passed to the TC layer transmit block, it is stored in the TC layer transmit FIFO. When the ATM cell is to be transmitted, it is read and processed from the TC layer transmit FIFO. The scrambling function is performed on the ATM cell payload if TCMODEx[TPS] = 1.
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ATM Transmission Convergence Layer PowerQUICC II 1M Sub Rate BRG Generate Cell Req CP Write to FIFO ATM Cells Only cell req 2M Serial Rate 1M Cell Sub Rate ATM Channels UTOPIA BTM PHY TC Generate Idle Cells FCC (Internal/Sub Rate) DPR Idle cell ATM cell Figure 34-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode) Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly.
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ATM Transmission Convergence Layer PowerQUICC II SONET UTOPIA 16-bit bus 155 mbps PHY FCC1 UTOPIA 8-bit bus FCC2 PHY 4*1.5 mbps SI-1 4 channel T1 Framer TDMa TDMb TDMc TDMd 4 channel T1 Framer TDMa TDMb TDMc TDMd DPR 8*1.5 mbps TC PHY 4*1.5 mbps SI-2 Figure 34-12. Example of Serial ATM Application 34.5.1 Operating the TC Layer at Higher Frequencies The operation of the TC layer requires a minimum frequency ratio of 1:2.
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ATM Transmission Convergence Layer 6. Program the Serial Interface (SI) 7. Enable TDM Step 1 To setup and initialize FCC2, program the FPSMR and GFMR as shown in Table 14. This is for working with one TC block operating in a single PHY environment. The transmitter and receiver should not be enabled at this time. In this example, FCC2 does not discard idle cells. Table 34-7.
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ATM Transmission Convergence Layer Step 6 Program the SI to retrieve the data bits (192 bits) out of the T1 frame (193 bits). The SI frame pattern is programmed in the SI RAM (Rx or Tx), as shown in Table 18. Table 34-11. Programming the SI RAM (Rx or Tx) for a T1 Application Init Values Description SI_RAM[00]=0x0000 1 bit is ignored. SI_RAM[02]=0x015E Route 8 bytes to FCC2. SI_RAM[04]=0x015E Route 8 bytes to FCC2. SI_RAM[06]=0x015F Route 8 bytes to FCC2 and go back to the first entry in table.
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Chapter 35 Fast Ethernet Controller The Ethernet IEEE 802.3 protocol is a widely-used LAN based on the carrier-sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted. Ethernet/IEEE 802.3 frames are based on the frame structure shown in Figure 35-1.
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Fast Ethernet Controller 10-Mbps Ethernet basic timing specifications follow: • Transmits at 0.8 µs per byte • The preamble plus start frame delimiter is sent in 6.4 µs. • The minimum interframe gap is 9.6 µs. • The slot time is 51.2 µs. 100-Mbps Ethernet basic timing specifications follow: • Transmits at 0.08 µs per byte • The preamble plus start frame delimiter is sent in 0.64 µs. • The minimum interframe gap is 0.96 µs. • The slot time is 5.12 µs. 35.
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Fast Ethernet Controller • • • • • • • • • • • Performs framing functions — Preamble generation and stripping — Destination address checking — CRC generation and checking — Automatic padding of short frames on transmit — Framing error (dribbling bits) handling Full collision support — Enforces the collision (jamming and TX_ER assertion) — Truncated binary exponential backoff algorithm for random wait — Two nonaggressive backoff modes — Automatic frame retransmission (until retry limit is reached) — Au
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Fast Ethernet Controller • • • • • • 35.
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Fast Ethernet Controller The PowerQUICC II has additional signals for interfacing with an optional external content-addressable memory (CAM), which are described in Section 35.7, “CAM Interface.” The PowerQUICC II uses the SDMA channels to store every byte received after the start frame delimiter into system memory. On transmit, the user provides the destination address, source address, type/length field, and transmit data.
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Fast Ethernet Controller or for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller stops immediately if no transmission is in progress or continues transmission until the current frame either finishes or terminates with a collision. When the Ethernet controller is given the RESTART TRANSMIT command, it resumes transmission. The Ethernet controller sends bytes least-significant nibble first. 35.
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Fast Ethernet Controller 35.6 Flow Control Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the maximum rate. When the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame size. The length/type fields of these frames have a special value. Table 35-1 shows the flow-control frame structure. Table 35-1.
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Fast Ethernet Controller When an external CAM is used for address filtering, users can choose to either discard rejected frames (FPSMR[ECM] = 0) or receive rejected frames and signal the CAM miss in the RxBD (FPSMR[ECM] = 1). NOTE The bus atomicity mechanism for CAM accesses may not function correctly when the CPM performs a DMA access to an external CAM device. This only impacts systems in which multiple CPMs will access the CAM. 35.
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Fast Ethernet Controller Table 35-2. Ethernet-Specific Parameter RAM (continued) Offset1 Name 0x68 TFCSTAT 0x6A TFCLEN 0x6C TFCPTR 0x70 MFLR 0x72 Width Description Hword Out-of-sequence TxBD. Includes the status/control, data length, and buffer pointer fields in the same format as a regular TxBD. Useful for sending flow control frames. Hword This area’s TxBD[R] is always checked between frames, regardless of FPSMRx[FCE]. Word If it is not ready, a regular frame is sent.
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Fast Ethernet Controller Table 35-2. Ethernet-Specific Parameter RAM (continued) Offset1 Name 0xB4 CF_RANG E 0xB6 MAX_B Hword Maximum BD byte count. Internal usage 0xB8 MAXD1 Hword Max DMA1 length register (typically 1520 decimal). Lets the user prevent system bus writes after a frame exceeds a specified size. The MAXD1 value is valid only if an address match is detected.
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Fast Ethernet Controller Table 35-2. Ethernet-Specific Parameter RAM (continued) 1 2 Offset1 Name 0xDC JBRC 2 Word (RMON mode only) The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets), and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). Note that this definition of jabber is different than the definition in IEEE-802.3 section 8.2.1.
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Fast Ethernet Controller NOTE Before resetting the CPM, configure TX_EN (RTS) to be an input. Transmit commands that apply to Ethernet are described in Table 35-3. Table 35-3. Transmit Commands Command STOP TRANSMIT GRACEFUL STOP TRANSMIT RESTART TRANSMIT INIT TX PARAMETERS Description When used with the Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE 802.3 station. It should not be used.
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Fast Ethernet Controller If an address from the hash table must be deleted, the Ethernet channel must be disabled, the hash table registers must be cleared, and the SET GROUP ADDRESS command must be executed for the remaining preferred addresses. This is required because the hash table might have mapped multiple addresses to the same hash table bit. 35.
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Fast Ethernet Controller Table 35-5. RMON Statistics and Counters (continued) Statistic Description Counter etherStatsFragments The total number of packets received that were less than 64 octets long (excluding framing bits but including FCS octets) and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error).
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Fast Ethernet Controller Check Address I G I/G Address F Broadcast Addr T Broadcast Enabled F Hash Search Hash Search Use Group Table Use Individual Table T T T Receive Frame F Individual Addr Match? Match? F F T Promiscuous? T Use CAM? F T Discard Frame Rejected by CAM? F Start Receive MPC8260 PowerQUICC II Family Reference Manual, Rev.
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Fast Ethernet Controller Figure 35-4. Ethernet Address Recognition Flowchart In the physical type of address recognition, the Ethernet controller compares the destination address field of the received frame with the physical address that the user programs in the PADDR. If it fails, the controller performs address recognition on multiple individual addresses using the IADDR_H/L hash table.
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Fast Ethernet Controller small fraction of frames from reaching memory. In such instances, an external CAM is advised if the extra bus use cannot be tolerated. See Section 35.7, “CAM Interface.” NOTE The hash tables cannot be used to reject frames that match a set of selected addresses because unintended addresses can map to the same bit in the hash table. Thus, an external CAM must be used to implement this function. 35.
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Fast Ethernet Controller Transmission errors are described in Table 35-6. Table 35-6. Transmission Errors Error Transmitter underrun Response The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after receiving the RESTART TRANSMIT command.
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Fast Ethernet Controller 0 Field HBC 1 2 3 FC SBT 4 5 6 7 LPB LCW FDE MON Reset 8 9 — 10 11 12 15 PRO FCE RSH — 0000_0000_0000_0000 R/W R/W Addr 0x0x11304 (FPSMR1), 0x0x11324 (FPSMR2), 0x0x11324 (FPSMR3) 16 20 Field — 21 22 23 24 CAM BRO ECM Reset 25 26 CRC 31 — 0000_0000_0000_0000 R/W R/W Addr 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3) Figure 35-5. FCC Ethernet Mode Registers (FPSMR) Table 35-8 describes FPSMR fields. Table 35-8.
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Fast Ethernet Controller Table 35-8. FPSMR Ethernet Field Descriptions (continued) Bits Name Description 7–8 — Reserved, should be cleared. 9 PRO Promiscuous 0 Check the destination address of incoming frames. 1 Receive the frame regardless of its address. A CAM can be used for address filtering when FSMR[CAM] is set. 10 FCE Flow control enable 0 Flow control is not enabled. 1 Flow control is enabled.
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Fast Ethernet Controller Figure 35-6. Ethernet Event Register (FCCE)/Mask Register (FCCM) Reset 0000_0000_0000_0000 R/W R/W Addr 0x0x11310 (FCCE1), 0x0x11330 (FCCE2), 0x0x11350 (FCCE3)/ 0x0x11314 (FCCM1), 0x0x11334 (FCCM2), 0x0x11354 (FCCM3) 16 31 Field — Reset 0000_0000_0000_0000 R/W R/W Addr 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Table 35-9 describes FCCE/FCCM fields. Table 35-9.
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Fast Ethernet Controller Frame Received in Ethernet Stored in Rx Buffer Time RXD P SFD DA SA T/L Line Idle D CR Line Idle RX_DV Ethernet FCCE Events RXB RXF Notes: 1. RXB event assumes receive buffers are 64 bytes each. 2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency. Frame Transmitted by Ethernet Stored in Tx Buffer P SFD DA SA T/L Line Idle TXD D CR Line Idle TX_EN COL Ethernet FCCE Events TXB TXB, GRA Notes: 1.
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Fast Ethernet Controller Offset + 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 E — W I L F CMR M BC MC LG NO SH CR OV CL Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 35-8. Fast Ethernet Receive Buffer (RxBD) Table 35-10 describes Ethernet RxBD fields. Table 35-10. RxBD Field Descriptions Bits Name Description 0 E Empty 0 The buffer associated with this RxBD is full or reception terminated due to an error.
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Fast Ethernet Controller Table 35-10. RxBD Field Descriptions (continued) Bits Name Description 8 BC Broadcast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address is the broadcast address. 9 MC Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address is a multicast address other than a broadcast address. 10 LG Rx frame length violation.
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Fast Ethernet Controller E MRBLR = 64 Bytes for this FCC Buffer Receive BD 0 L F 0 1 Destination Address (6) Length 0x0040 Source Address (6) Pointer 32-Bit Buffer Pointer Status 0 Buffer Full Type/Length (2) 64 Bytes Data Bytes (50) E Status 0 Receive BD 1 L F Buffer 1 0 Length 0x0045 Pointer 32-Bit Buffer Pointer CRC Bytes (4) Buffer Closed after CRC Received.
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Fast Ethernet Controller Offset + 0 0 1 2 3 4 5 6 7 8 9 R PAD W I L TC DEF HB LC RL Offset + 2 Data length Offset + 4 Tx data Buffer Pointer 10 11 12 RC 13 14 15 UN CSL Offset + 6 Figure 35-10. Fast Ethernet Transmit Buffer (TxBD) Table 35-11 describes Ethernet TxBD fields. Table 35-11.
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Fast Ethernet Controller Table 35-11. Ethernet TxBD Field Definitions (continued) Field Name Description 10–13 RC Retry count. Indicates the number of retries required for this frame to be successfully sent. If RC = 0, the frame is sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15 retries were needed. If RC = 15 and RET_LIM > 15, 15 or more retries were needed. The Ethernet controller updates RC after sending the buffer. 14 UN Underrun.
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Fast Ethernet Controller MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1225
Chapter 36 FCC HDLC Controller Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most common protocols. The framing structure of HDLC is shown in Figure 36-1. HDLC uses a zero insertion/deletion process (commonly known as bit stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags.
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FCC HDLC Controller • • • • • • • • • • • • 36.
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FCC HDLC Controller 36.3 HDLC Channel Frame Reception Processing The HDLC receiver is designed to work with almost no core intervention and can perform address recognition, CRC checking, and maximum frame length checking. The received frame is available for any HDLC-based protocol. When the core enables a receiver, the receiver waits for an opening flag character. When it detects the first byte of the frame, the HDLC controller compares the frame address against the user-programmable addresses.
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FCC HDLC Controller Table 36-1. FCC HDLC-Specific Parameter RAM Memory Map (continued) 1 2 Offset1 Name Width 0x4E CRCEC2 Hword CRC error counter. Counts frames not addressed to the user or frames received in the BSY condition, but does not include overrun, CD lost, or abort errors. 0x50 ABTSC2 Hword Abort sequence counter 0x52 NMARC2 Hword Nonmatching address Rx counter. Counts nonmatching addresses received (error-free frames only). See the HMASK and HADDR[1–4] parameter description.
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FCC HDLC Controller 16-Bit Address Recognition Flag 0x7E Address 0x68 Address 0xAA Control 0x44 HMASK HADDR1 0xFFFF 0xAA68 HADDR2 HADDR3 HADDR4 8-Bit Address Recognition etc. Flag 0x7E Address 0x55 HADDR1 0x00FF 0xXX55 0xFFFF 0xAA68 HADDR2 0xXX55 HADDR3 0xXX55 0xAA68 HADDR4 0xXX55 Recognizes one 16-bit address (HADDR1) and the 16-bit broadcast address (HADDR2) HMASK Control 0x44 etc. Recognizes one 8-bit address (HADDR1) Figure 36-2. HDLC Address Recognition Example 36.
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FCC HDLC Controller Table 36-2. Transmit Commands (continued) Command Description Enables character transmission on the transmit channel. This command is expected by the HDLC controller after a STOP TRANSMIT command, after a STOP TRANSMIT command is issued and the channel in its FCC mode register is disabled, after a GRACEFUL STOP TRANSMIT command, or after a transmitter error (underrun or CTS lost with no automatic frame retransmission).
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FCC HDLC Controller Table 36-5. HDLC Reception Errors Error Description Overrun Error The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins programming the SDMA channel and updating the CRC whenever data is received in the FIFO buffer. When a receive FIFO overrun occurs, the channel writes the received data byte to the internal FIFO buffer over the previously received byte. The previous byte and the frame status are lost.
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FCC HDLC Controller 0 Field 3 NOF 4 5 FSE MFF Reset 6 8 9 — 10 TS 15 — 0000_0000_0000_0000 R/W R/W Addr 0x0x11304 (FPSMR1), 0x0x11324 (FPSMR2), 0x0x11324 (FPSMR3) 16 Field NBL 17 23 24 — Reset 25 26 CRC 31 — 0000_0000_0000_0000 R/W R/W Addr 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3) Figure 36-3. HDLC Mode Register (FPSMR) The FPSMR fields are described in Table 36-6. Table 36-6. FPSMR Field Descriptions 1 Bits Name Description 0–3 NOF Number of flags.
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FCC HDLC Controller Table 36-6. FPSMR Field Descriptions (continued)1 1 Bits Name Description 16 NBL Nibble mode enable 0 Nibble mode disabled (1 bit of data per clock). Note that at the end of the frame (after the closing flag), RTS negates immediately after the active edge of TCLK. 1 Nibble mode enabled (4 bits of data per clock). The negation of of the RTS output signal is not synchronized to the serial clock.
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FCC HDLC Controller MRBLR = 32 Bytes for this FCC Buffer E RxBD 0 L F 0 0 1 Address 1 Length 0x0020 Address 2 Pointer 32-Bit Buffer Pointer Status Buffer Full 32 Bytes Control Byte 29 Information (I-Field) Bytes Status E RxBD 1 L F 0 1 0 Buffer Last I-Field Byte Length 0x0023 Pointer 32-Bit Buffer Pointer CRC Byte 1 Buffer Closed When Closing Flag Received 32 Bytes CRC Byte 2 Empty Status E RxBD 2 L F 0 1 1 AB Buffer 1 Address 1 Length 0x0003 Pointer 32-Bit Buffer Po
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FCC HDLC Controller Figure 36-5 shows the FCC HDLC RxBD. Offset + 0 0 1 2 3 4 5 6 E — W I L F CM 7 8 9 — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer 10 11 12 13 14 15 LG NO AB CR OV CD Offset + 6 Figure 36-5. FCC HDLC Receive Buffer Descriptor (RxBD) Table 36-7 describes RxBD fields. Table 36-7. RxBD field Descriptions Bits Name Description 0 E Empty 0 The buffer is full with received data or data reception stopped because of an error.
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FCC HDLC Controller Table 36-7. RxBD field Descriptions (continued) Bits Name Description 11 NO Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by eight. 12 AB Rx abort sequence. At least seven consecutive 1s are received during frame reception. 13 CR Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive buffer. 14 OV Overrun. A receiver overrun occurs during frame reception. 15 CD Carrier detect lost.
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FCC HDLC Controller Table 36-8. HDLC TxBD Field Descriptions Bits Name Description 0 R Ready 0 The buffer associated with this BD is not ready for transmission. The user can manipulate this BD or its associated buffer. The CP clears R after the buffer has been sent or an error occurs. 1 The buffer is ready to be sent. The transmission may have begun, but it has not completed. The user cannot set fields in this BD once R is set. 1 — Reserved, should be cleared.
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FCC HDLC Controller 36.9 HDLC Event Register (FCCE)/Mask Register (FCCM) The FCCE is used as the HDLC event register when the FCC operates as an HDLC controller. The FCCE reports events recognized by the HDLC channel and generates interrupts. On recognition of an event, the HDLC controller sets the corresponding FCCE bit. FCCE bits are cleared by writing ones; writing zeros does not affect bit values. All unmasked bits must be cleared before the CP clears the internal interrupt request.
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FCC HDLC Controller Table 36-9. FCCE/FCCM Field Descriptions Bits Name Description 0–7 — 8 GRA 9–10 — 11 TXE Tx error. An error (CTS lost or underrun) occurs on the transmitter channel. 12 RXF Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two clocks after receipt of the last bit of the closing flag. 13 BSY Busy condition. A frame is received and discarded due to a lack of buffers. 14 TXB Transmit buffer. Enabled by setting TxBD[I].
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FCC HDLC Controller Frame Received by HDLC Stored in Rx Buffer Time RXD F Line Idle F A A C I I I CR CR F Line Idle CD HDLC FCCE Events CD IDL FLG FLG RXB RXF FLG IDL FLG CD Notes: 1. RXB event assumes receive buffers are 6 bytes each. 2. The second IDL event occurs after 15 ones are received in a row. 3. The FLG interrupts show the beginning and end of flag reception. 4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency. 5.
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FCC HDLC Controller Table 36-10 describes FCCS bits. Table 36-10. FCCS Register Field Descriptions Bits Name Description 0–4 — Reserved, should be cleared. 5 FG Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are examined to see if a flag is present. FG is set as soon as an HDLC flag (0x7E) is received on the line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined.
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FCC HDLC Controller MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1243
Chapter 37 FCC Transparent Controller The FCC transparent controller functions as a high-speed serial-to-parallel and parallel-to-serial converter. Transparent mode provides a clear channel on which the FCC performs no bit-level manipulation—implementing higher-level protocols would require software. Transparent mode is also referred to as a totally transparent or promiscuous operation.
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FCC Transparent Controller • • • Reverse data mode Another protocol can be performed on the FCC’s other half (transmitter or receiver) during transparent mode External BD table 37.2 Transparent Channel Operation The transparent transmitter and receiver operates in the same way as the HDLC controller of the FCC (see Chapter 36, “FCC HDLC Controller”) except in the following ways: 1. The FPSMR does not affect the transparent controller, only the GFMR does. 2.
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FCC Transparent Controller following the 8-bit SYNC. This effectively links the transmitter synchronization to the receiver synchronization. 37.3.2 External Synchronization Signals If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the transmitter and CD is used for the receiver; these signals share the following sampling options.
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FCC Transparent Controller PowerQUICC II (A) PowerQUICC II (B) TXD RXD RTS CD BRGOx RXD CD CLKx CLKx TXD RTS BRGOx BRGOx (Output is CLKx Input) TXD (Output is RXD Input) RTS (Output is CD Input) Last Bit of Frame Data First Bit of Frame Data or CRC TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame Notes: 1 Each PowerQUICC II generates its own transmit clocks.
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Chapter 38 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the PowerQUICC II to exchange data between other PowerQUICC II chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock and slave select).
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Serial Peripheral Interface (SPI) • • • • • • • • • • 38.
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Serial Peripheral Interface (SPI) 38.3 Configuring the SPI Controller The SPI can be programmed to work in a single- or multiple-master environment. This section describes SPI master and slave operation in a single-master configuration and then discusses the multi-master environment. 38.3.1 The SPI as a Master Device In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
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Serial Peripheral Interface (SPI) When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD is processed after data from the current buffer is sent. Typically there is no delay on SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current buffer is sent.
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PowerQUICC II SPISEL0 SPISEL1 SPISEL2 SPISEL3 Serial Peripheral Interface (SPI) SPI #0 SPIMOSI SPIMISO SPICLK SPISEL SELOUT1 SELOUT2 SELOUT3 PowerQUICC II SPI #1 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT2 SELOUT3 PowerQUICC II SPI #2 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT3 PowerQUICC II SPI #3 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT2 Notes: • All signals are open-drain • For a system with more than two masters, SPISEL and SPIE[MME] do not detect all possible conflicts • I
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Serial Peripheral Interface (SPI) mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate. 38.4 Programming the SPI Registers The following sections describe the registers used in configuring and operating the SPI. 38.4.1 SPI Mode Register (SPMODE) The SPI mode register (SPMODE), shown in Figure 38-4, controls both the SPI operation mode and clock source.
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Serial Peripheral Interface (SPI) Table 38-1. SPMODE Field Descriptions (continued) Bits Name Description 7 EN Enable SPI. Do not change other SPMODE bits when EN is set. 0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not functioning and the input clock is disabled. 1 The SPI is enabled. Configure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as described in Section 40.2, “Port Registers. “ 8–11 LEN Character length in bits per character.
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Serial Peripheral Interface (SPI) SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (From Master) SPIMISO (From Slave) msb Q lsb msb lsb SPISEL NOTE: Q = Undefined Signal. Figure 38-6. SPI Transfer Format with SPMODE[CP] = 1 38.4.1.1 SPI Examples with Different SPMODE[LEN] Values The examples below show how SPMODE[LEN] is used to determine character length. To help map the process, the conventions shown in Table 38-2 are used in the examples. Table 38-2.
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Serial Peripheral Interface (SPI) with LEN=7 (data size=8), the following data is selected: msb ghij_klmn__opqr_stuv lsb the data string is selected: msb ghij_klmn__opqr_stuv lsb with REV=0, the string transmitted, a byte at a time with lsb first is: first nmlk_jihg__vuts_rqpo last with REV=1, the string is byte reversed and transmitted, a byte at a time, with lsb first: first ghij_klmn__opqr_stuv last Example 3 with LEN=0xC (data size=13), the following data is selected: msb ghij_klmn__xxxr_stuv lsb t
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Serial Peripheral Interface (SPI) Table 38-3. SPIE/SPIM Field Descriptions Bits Name Description 6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two character times to be sure data is completely sent over the transmit signal. 7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed. 38.4.
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Serial Peripheral Interface (SPI) Table 38-5. SPI Parameter RAM Memory Map Offset 1 Name 0x00 RBASE 0x02 TBASE 0x04 RFCR Byte 0x05 TFCR Byte 1 Width Description Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM. Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are Hword allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling the SPI.
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Serial Peripheral Interface (SPI) 2 Normally, these parameters need not be accessed. They are listed to help experienced users in debugging. 38.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR) Figure 38-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR). 0 Field 1 2 — 3 GBL Reset 4 BO 5 6 7 TC2 DTB — 0000_0000 R/W R/W Addr SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR) Figure 38-9.
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Serial Peripheral Interface (SPI) Table 38-7. SPI Commands (continued) Command Description CLOSE RXBD Forces the SPI controller to close the current RxBD and use the next BD for subsequently received data. If the controller is not receiving data, no action is taken. Use this command to extract data from a partially full buffer. INIT RX Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when the receiver is disabled.
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Serial Peripheral Interface (SPI) — For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this value should be greater than zero. If the character length is more than 8 bits, the data length should be even. For example, to send three characters of 8-bit data, 1 start, and 1 stop, the data length field should be initialized to 3.
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Serial Peripheral Interface (SPI) Table 38-8. SPI RxBD Status and Control Field Descriptions (continued) Bits Name Description 4 L Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode only). Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer. 0 This buffer does not contain the last character of the message. 1 This buffer contains the last character of the message. 5 — Reserved, should be cleared. 6 CM Continuous mode.
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Serial Peripheral Interface (SPI) Table 38-9. SPI TxBD Status and Control Field Descriptions (continued) Bits Name Description 2 W Wrap (last BD in TxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. 3 I Interrupt.
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Serial Peripheral Interface (SPI) 8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR. 10. Write 0xFF to SPIE to clear any previous events. 11. Write 0x37 to SPIM to enable all possible SPI interrupts. 12.
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Serial Peripheral Interface (SPI) NOTE If the master sends 3 bytes and negates SPISEL, the RxBD is closed but the TxBD remains open. If the master sends 5 or more bytes, the TxBD is closed after the fifth byte. If the master sends 16 bytes and negates SPISEL, the RxBD is closed without triggering an out-of-buffers error. If the master sends more than 16 bytes, the RxBD is closed (full) and an out-of-buffers error occurs after the 17th byte is received. 38.
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Chapter 39 I2C Controller The inter-integrated circuit (I2C®) controller lets the PowerQUICC II exchange data with other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. It uses two signals—serial data (SDA) and serial clock (SCL)—to carry information between the integrated circuits connected to it.
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I2C Controller 39.1 Features The following is a list of the I2C controller’s main features: • Two-signal interface (SDA and SCL) • Support for master and slave I2C operation • Multiple-master environment support • Continuous transfer mode for automatic scanning of a peripheral • Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%), assuming a 100-MHz system clock.
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I2C Controller because the R/W request follows the slave port address in the I2C bus specification, the R/W request bit must be placed in the lsb (bit 7) unless operating in reverse data mode; see Section 39.4.1, “I2C Mode Register (I2MOD).” To write to a slave, the master sends a write request (R/W = 0) along with either the target slave’s address or a general call (broadcast) address of all zeros, followed by the data to be written.
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I2C Controller A master write occurs as follows: 1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel loads the Tx FIFO with data and the I2C bus is not busy. 2. The I2C master generates a start condition—a high-to-low transition on SDA while SCL is high—and the transfer clock SCL pulses for each bit shifted out on SDA.
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I2C Controller 3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave is an PowerQUICC II, the address is programmed in its I2C address register (I2ADD). — If a match is found, the slave acknowledges the received byte and begins transmitting on the clock pulse immediately following the acknowledge. — If a match is found but the slave is not ready, the read request is not acknowledged and the transaction is aborted.
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I2C Controller I2C Registers 39.4 The following sections describe the I2C registers. 39.4.1 I2C Mode Register (I2MOD) The I2C mode register, shown in Figure 39-6, controls the I2C modes and clock source. 0 Field 1 — 2 3 4 REVD GCD FLT Reset 5 6 PDIV 7 EN 0000_0000 R/W R/W Addr 0x0x11860 Figure 39-6. I2C Mode Register (I2MOD) Table 39-1 describes I2MOD bit functions. Table 39-1. II2MOD Field Descriptions Bits Name 0–1 — Description Reserved and should be cleared.
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I2C Controller 0 6 Field SAD Reset 7 — Undefined R/W R/W Addr 0x0x11864 2 Figure 39-7. I C Address Register (I2ADD) Table 39-2 describes I2ADD fields. Table 39-2. I2ADD Field Descriptions Bits Name 0–6 SAD 7 — 39.4.3 Description Slave address 0–6. Holds the slave address for the I2C port. Reserved and should be cleared. I2C Baud Rate Generator Register (I2BRG) The I2C baud rate generator register, shown in Figure 39-8, sets the divide ratio of the I2C BRG.
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I2C Controller 0 Field 2 — 3 4 5 6 7 TXE — BSY TXB RXB Reset 0000_0000 R/W R/W Addr 0x0x11870(I2CER)/0x0x11874 I2CMR) 2 Figure 39-9. I C Event/Mask Registers (I2CER/I2CMR) Table 39-4 describes the I2CER/I2CMR fields. Table 39-4. I2CER/I2CMR Field Descriptions Bits Name 0–2 — 3 TXE 4 — 5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available. 6 TXB Tx buffer.
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I2C Controller Table 39-5. I2COM Field Descriptions Bits Name 1–6 — 7 M/S 39.5 Description Reserved and should be cleared. Master/slave. Configures the I2C controller to operate as a master or a slave. 0 I2C is a slave. 1 I2C is a master. I2C Parameter RAM The I2C controller parameter table is used for the general I2C parameters and is similar to the SCC general-purpose parameter RAM.
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I2C Controller Table 39-6. I2C Parameter RAM Memory Map (continued) Offset 1 Name 0x10 RBPTR Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in an idle state or to the current descriptor during frame processing for each I2C channel. After a reset or when the end of the descriptor table is reached, the CP initializes RBPTR to the value in RBASE.
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I2C Controller Table 39-7. RFCR/TFCR Field Descriptions Bits Name Description 3–4 BO Byte ordering. Selects the required byte ordering for the buffer. If BO is changed on-the-fly, it takes effect at the beginning of the next frame or BD. 00 True little-endian. Note this mode can only be used with 32-bit port size memory. 01 Big-endian 1x Munged little-endian 5 TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory access.
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I2C Controller Dual-Port RAM External Memory TxBD Table Tx Buffer Status and Control Data Length I2C TxBD Table I2C RxBD Table Buffer Pointer RxBD Table Status and Control I2C RxBD Table Pointer (RBASE) Tx Buffer Rx Buffer Data Length Buffer Pointer I2C TxBD Table Pointer (TBASE) Figure 39-12. I2C Memory Structure 39.7.1 I2C Buffer Descriptors (BDs) Receive and transmit buffer descriptors report information about each buffer transferred and whether a maskable interrupt should be generated.
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I2C Controller Offset + 0 0 1 2 3 4 E — W I L 5 13 — Offset + 2 Data Length Offset + 4 RX Buffer Pointer 14 15 OV — Offset + 6 Figure 39-13. I2C RxBD Table 39-9 describes I2C RxBD status and control bits. Table 39-9. I2C RxBD Status and Control Bits Bits Name Description 0 E Empty. 0 The buffer is full or stopped receiving because of an error. The core can examine or write to any fields of this RxBD, but the CP does not use this BD while E = 0.
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I2C Controller Offset + 0 0 1 2 3 4 5 R — W I L S 6 12 — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer 13 14 15 NAK UN CL Offset + 6 Figure 39-14. I2C TxBD Table 39-10 describes I2C TxBD status and control bits. Table 39-10. I2C TxBD Status and Control Bits Bits Name Description 0 R Ready. 0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R after the buffer is sent or an error occurs.
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Chapter 40 Parallel I/O Ports The CPM supports four general-purpose I/O ports—ports A, B, C, and D. Each pin in the I/O ports can be configured as a general-purpose I/O signal or as a dedicated peripheral interface signal. Port C is unique in that 16 of its pins can generate interrupts to the interrupt controller. Each pin can be configured as an input or output and has a latch for data output, read or written at any time, and configured as general-purpose I/O or a dedicated peripheral pin.
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Parallel I/O Ports 0 1 Field OD0 1 2 OD1 1 3 1 OD2 OD3 4 1 OD4 5 6 OD5 OD6 Reset 7 8 OD7 OD8 9 10 11 12 13 14 15 OD9 OD10 OD11 OD12 OD13 OD14 OD15 0000_0000_0000_0000 R/W R/W Addr 0x0x10D0C (PODRA), 0x0x10D2C (PODRB), 0x0x10D4C (PODRC), 0x0x10D6C (PODRD) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31 Reset 0000_0000_0000_0000 R/W R/W Addr 0x10D0E (PODRA), 0x10D2E (PODRB
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Parallel I/O Ports 0 Field D0 1 1 2 D1 1 D2 3 1 D3 1 4 5 6 7 8 9 10 11 12 13 14 15 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Reset — R/W R/W Addr 0x0x10D10 (PDATA), 0x0x10D30 (PDATB), 0x0x10D50 (PDATC), 0x0x10D70 (PDATD) 16 Field D16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 14 15 Reset — R/W R/W Addr 0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD)
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Parallel I/O Ports 40.2.4 Port Pin Assignment Register (PPAR) The port pin assignment register (PPAR) is cleared at system reset.
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Parallel I/O Ports 0 1 Field SO0 1 2 SO1 1 3 1 SO2 SO3 1 4 5 6 7 8 SO4 SO5 SO6 SO7 SO8 Reset 9 10 11 12 13 14 15 SO9 SO10 SO11 SO12 SO13 SO14 SO15 0000_0000_0000_0000 R/W R/W Addr 0x0x10D08 (PSORA), 0x0x10D28 (PSORB), 0x0x10D48 (PSORC), 0x0x10D68 (PSORD) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24 SO25 SO26 SO27 SO28 SO29 SO30 SO31 Reset 0000_0000_0000_0000 R/W R/W Addr 0x10D0A (PSORA), 0x10D2A (PS
PAGE 1284
Parallel I/O Ports Read To/from internal bus PDATx Write PDATx Read PDATx Latch 0 Open Drain Control 0 From DED OUT1 EN 1 PDIR 1 From DED OUT2 PODR PPAR PSOR Pin Default Input IN1 0 To DED IN1 1 PPAR & PSOR & PDIR Default Input IN2 0 To DED IN2 1 PPAR & PSOR & PDIR 1 Register Name 0 1 Description PPAR x General purpose Dedicated Port pin assignment PSORx Dedicated 1 Dedicated 2 Special operation PDIR x Input Output Direction1 PODRx Regular Open drain PDATx 0 1 Data B
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Parallel I/O Ports 40.4.1 General Purpose I/O Pins Each one of the port pins is independently configured as a general-purpose I/O pin if the corresponding port pin assignment register (PPAR) bit is cleared. Each pin is configured as a dedicated on-chip peripheral pin if the corresponding PPAR bit is set.When the port pin is configured as a general-purpose I/O pin, the signal direction for that pin is determined by the corresponding control bit in the port data direction register (PDIR).
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Parallel I/O Ports PD4 Secondary option for SMC2 RxD GND PA8 Primary option for SMC2 RxD 0 MUX 0 MUX Pin PD4 1 1 Pin PA8 PPARD[4] == 1 & PSORD[4] == 1 & PDIRD[4] == 0 to SMC2 RxD PPARA[8] == 1 & PSORA[8] == 0 & PDIRA[8] == 0 Figure 40-7. Primary and Secondary Option Programming In the tables below, the default value for a primary option is simply a reference to the secondary option. In the secondary option, the programming is relevant only if the primary option is not used for the function.
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Parallel I/O Ports Table 40-5.
PAGE 1288
Parallel I/O Ports Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued) Pin Function Pin PSORA = 0 PDIRA = 1 (Output) PDIRA = 0 (Input) PSORA = 1 Defaul PDIRA = 0 (Input, or PDIRA = 1 (Output) t Input Inout if Specified) PA17 FCC1: RxD[7]1 UTOPIA 8 FCC1: RxD[15]1 UTOPIA 16 FCC1: RxD[0] MII/HDLC nibble FCC1: RxD HDLC/transp.
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Parallel I/O Ports Table 40-5.
PAGE 1290
Parallel I/O Ports Table 40-6.
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Parallel I/O Ports Table 40-6.
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Parallel I/O Ports Table 40-6.
PAGE 1293
Parallel I/O Ports Table 40-7.
PAGE 1294
Parallel I/O Ports Table 40-7.
PAGE 1295
Parallel I/O Ports 1 Not available on the MPC8250. .25µm (HiP4) devices only: available only when the primary option for this function is not used. 3 MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”) 2 Table 40-8 shows the port D pin assignments. Table 40-8.
PAGE 1296
Parallel I/O Ports Table 40-8.
PAGE 1297
Parallel I/O Ports Table 40-8.
PAGE 1298
Parallel I/O Ports and/or CD to automatically control operation. This lets the user fully implement protocols V.24, X.21, and X.21 bis (with the assistance of other general-purpose I/O lines). To configure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates interrupts, these steps should be followed: 1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0. 2. Write the corresponding PDIRC bit with a zero. 3.
PAGE 1299
Appendix A Register Quick Reference Guide A0 This section provides a brief guide to the core registers. A.1 PowerPC Registers—User Registers The implements the user-level registers defined by the PowerPC architecture except those required for supporting floating-point operations (the floating-point register file (FPRs) and the floating-point status and control register (FPSCR)). User-level PowerPC registers are listed in Table A-1 and Table A-2.
PAGE 1300
Register Quick Reference Guide Table A-3. Supervisor-Level PowerPC Registers Description Name Machine state register MSR Comments Serialize Access See the Programming Environments Manual and Write fetch sync MPC603e RISC Microprocessor User’s Manual Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture. Table A-4.
PAGE 1301
Register Quick Reference Guide A.3 MPC8260-Specific SPRs Table A-2 and Table A-5 list SPRs specific to the MPC8260. Supervisor-level registers are described in Table A-5. Table A-5.
PAGE 1302
Register Quick Reference Guide MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1303
Appendix B Reference Manual (Rev 1) Errata This appendix lists errata to revision 1 of the MPC8260 PowerQUICC II™ User’s Manual. It is intended solely as a quick reference for users who are familiar with revision 1. These errata have been incorporated into the current manual. Therefore, the following information is redundant. This appendix contains the last published version of the errata document (rev 2.1, 04/2004). NOTE All numbering corresponds to revision 1 of the MPC8260 PowerQUICC II™ User’s Manual.
PAGE 1304
Reference Manual (Rev 1) Errata 4.3.2.1, 4-28 The bit definitions should be reversed for BCR[DAM] in Table 4-9. They should appear as follows: 10 4.3.2.2, 4-31 4.3.2.8, 4-38 5.3, 5-6 5.4.1, 5-10 7.2.8.1.1, 7-17 Timing Comments 7.2.8.1.2, 7-17 Timing Comments DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM). This bit is similar to BCR[EXDD] but with opposite polarity.
PAGE 1305
Reference Manual (Rev 1) Errata 8.4.4.1. 8-24 8.4.4.1. 8-24 9.11, 9-30 9.11.1.11, 9-42 9.11.1.14, 9-45 PCI controller can initiate global transactions—Assertion must occur at least one clock cycle following AACK for the current transaction and at least one clock cycle after ARTRY can be asserted.
PAGE 1306
Reference Manual (Rev 1) Errata 9.11.2.22, 9-62 10.8, 10-8 10.8, 10-9 10.10, 10-11 11.3.1, 11-16 11.3.3, 11-23 11.3.3, 11-24 11.6.4.2, 11-81 14.3.5, 14-7 In Figure 9-54, the reset value row has a misplaced set bit. It currently shows bit 4 as reset to 1 (0000_0000_0001_0000). It should show bit 5—CFG_LOCK—as reset to 1 (0000_0000_0010_0000). In Figure 10-5, the access of SCCR[PCI_MODE, PCI_MODCK] (bits 23 and 24) should be shown as read/write (R/W).
PAGE 1307
Reference Manual (Rev 1) Errata #24 as shown). IDMA option 3 is shown correctly as the last request in prioritization of CPM peripherals. The table should appear as follows: Priority 1-3 Request Unchanged 4 IDMA[1–4] emulation (default—option 1)1 5 Emergency (from FCCs, MCCs, and SCCs) 6 IDMA[1–4] emulation (option 2)1 7-33 34 Same relative priority IDMA[1–4] emulation (option 3)1 1 The priority of each IDMA channel is programmed independently. See the RCCR[DRxQP] description in Section 14.3.
PAGE 1308
Reference Manual (Rev 1) Errata Also, replace the description of REV_NUM in Table 14-15 with the following (changes or additions appear in boldface): RAM Base + 0x8AF0 REV_NUM Hword 15.4.5, 15-15 15.5.2, 15-19 19.7.1, 19-15 19.7.1.1, 19-16 Microcode revision number. If working with newer silicon than what is shown below, consult the product page on the web. For .29-µm (HiP3) devices: Rev A.1—0x0001 Rev B.2—0x003B Rev C.2—0x007B For .25-µm (HiP4) devices: Rev A.0—0x000D Rev B.1—0x002D Rev C.
PAGE 1309
Reference Manual (Rev 1) Errata must be negated no later than 15 ns after the first rising edge of the bus clock after CS negation for the peripheral. 19.7.2, 19-17 19.8.2, 19-19 19.8.5, 19-25 20.3.6, 20-22 29.5, 29-8 Add the following note: When DREQ is level-sensitive and DONE is an input to the PowerQUICC II, the system design must ensure that DONE is not asserted while DREQ is also asserted. In other words, the system must not request IDMA service and termination at the same time.
PAGE 1310
Reference Manual (Rev 1) Errata occurs every 256 serial transmit clocks. The polling algorithm depends on the FCC configuration, as shown in the following equations: 256 clocks / 25 MHz = 10 µs Fast Ethernet: 256 clocks / 2.5 MHz = 100 µs 10BaseT: The user, however, can request that the CP begin processing the new frame/buffer without waiting the normal polling time.
PAGE 1311
Reference Manual (Rev 1) Errata 30.10.7, 30-84 In Table 30-41, change the description of UTOPIAE to the following: 0x00 UTOPIAE 30.12.1, 30-87 Hword Counts cells dropped as a result of UTOPIA/ATM protocol violations. Violations include the following: 1. Parity error 2. HEC error 3. Invalid timing of RxSOC. If RxClav is asserted for the selected PHY, RxSOC should be asserted the cycle immediately following the assertion of RXENB.
PAGE 1312
Reference Manual (Rev 1) Errata 30.13.2, 30-92 In Table 30-47, replace the description of TPRI, TUDC, RUDC, and UPLM with the following (changes appear in boldface): 18 TPRI Transmitter priority. Used to adjust the default priority of the FCC transmitter. It is strongly recommended to set TPRI when in multi-PHY mode, or in single-PHY mode if the maximal bit rate (either internal or external rate) is higher than that of the other FCCs; for other modes, it should remain cleared.
PAGE 1313
Reference Manual (Rev 1) Errata 30.13.4, 30-95, -96 seven, TIRU event is reported, see Section 30.13.3, “ATM Event Register (FCCE)/Mask Register (FCCM)”. Note that a mismatch occurs if the PHY rate or the CPM performance are lower then the internal rate. FTIRRx, shown in Figure 30-61, includes the initial value of the internal rate timer. The source clock of the internal rate timers is supplied by one of four baud-rate generators selected in CMXUAR; see Section 16.4.
PAGE 1314
Reference Manual (Rev 1) Errata 33.4.1.1, 33-29 Add the following two rows to the bottom of Table 33-5: 0x0E IASNCCTR Byte Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells Counter - Number of cells passed to the groups links upon request. Initialize to IASNC. 0x0F IASNC Byte Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells - reset for IASNCtr. Number of cells passed to the groups links upon request.
PAGE 1315
Reference Manual (Rev 1) Errata 33.4.7.1, 33- 47 OFFSET + 0 Add DSL to Offset + 0 in Figure 33-29 and Table 33-23, as shown in the following: 0 1 2 V — W 3 5 — 6 7 TQU TQO OFFSET + 2 L/G 9 8 9 10 — DSL LS 11 12 13 14 15 DCBO LDS GDS IFSD IFSW NUM DSL DCB synchronization lost. This interrupt is issued when a link in a group with IGRSTATE[GDSS] = 11 loses synchronization, and the link enters HUNT state at the IFSM. 33.4.10, 33-54 Add the following new section: 33.4.
PAGE 1316
Reference Manual (Rev 1) Errata 33.5.4.5.1, 33-65 The order of steps is incorrect. Current step #2 (“Use the new group order table...”) should immediately follow current step # 6 (“Software should wait...”). Therefore, current step # 6 becomes the new step #5 and current step #2 becomes the new step #6. 33.5.4.10, 33-70 Replace #4 and #7 with the following: 4. GDS (Group Delay Synchronized)—Group delay synchronized achieved or group delay synchronized not achieved.
PAGE 1317
Reference Manual (Rev 1) Errata and transmitted a byte at a time with lsb first: first r_stuv_ghij_klmn 39.4.3, 39-8 0–7 last In Table 39-3, the description of DIV should read as follows (changes appear in boldface): DIV 40-5, 40-10 Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I2C clock generator. The output of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty cycle.
PAGE 1318
Reference Manual (Rev 1) Errata MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1319
Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of Electrical and Electronics Engineers, Inc. with the permission of the IEEE. Note that some terms are defined in the context of how they are used in this book. A Architecture.
PAGE 1320
Although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined, the results of executing instructions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction. Breakpoint.
PAGE 1321
Critical-data first. An aspect of burst accesses that allow the requested data (typically a word or double word) in a cache block to be transferred first. D Denormalized number. A nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose explicit or implicit leading significand bit is zero. Direct-mapped cache.
PAGE 1322
F Fetch. Retrieving instructions from either the cache or main memory and placing them into the instruction queue. Fully-associative. Addressing scheme where every cache location (every byte) can have any possible address. G General-purpose register (GPR). Any of the 32 registers in the general-purpose register file. These registers provide the source operands and destination results for all integer data manipulation instructions.
PAGE 1323
Interrupt. An asynchronous exception. On PowerPC processors, interrupts are a special case of exceptions. See also asynchronous exception. L Latency. The time an operation requires. For example, execution latency is the number of processor clocks an instruction takes to execute. Memory latency is the number of bus clocks needed to perform a memory operation. Least-significant bit (lsb). The bit of least value in an address, register, data element, or instruction encoding. Least-significant byte (LSB).
PAGE 1324
Munging. A modification performed on an effective address that allows it to appear to the processor that individual aligned scalars are stored as little-endian values, when in fact it is stored in big-endian order, but at different byte addresses within double words. Note that munging affects only the effective address and not the byte order. Note also that this term is not used by the PowerPC architecture. Most-significant bit (msb).
PAGE 1325
Physical memory. The actual memory that can be accessed through the system’s memory bus. Pipelining. A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed. Precise exceptions.
PAGE 1326
Reservation. The processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a memory semaphore into a GPR. Reserved field. In a register, a reserved field is one that is not assigned a function. A reserved field may be a single bit. The handling of reserved bits is implementation-dependent. Software is permitted to write any value to such a bit.
PAGE 1327
Supervisor mode. The privileged operation state of a processor. In supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. Synchronization. A process to ensure that operations occur strictly in order. See Context synchronization and Execution synchronization. Synchronous exception. An exception that is generated by the execution of a particular instruction or instruction sequence.
PAGE 1328
Write-back. A cache memory update policy in which processor write cycles are directly written only to the cache. External memory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data. Write-through. A cache memory update policy in which all processor write cycles are written to both the cache and memory. MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1329
Index Numerics 603e features list, 2-3 60x bus 60x-compatible mode 60x-compatible bus mode, 8-3 address latch enable (ALE), 11-10 BUFCMD, 11-42 EAMUX signal, 11-42 MAR, 11-77 overview, 11-101 size calculation, 8-18 60x-to-local bus transaction priority, 11-7 address arbitration, 8-7 ARTRY, 8-22 operations, 8-7 pipelining, 8-8 timing configuration, 8-24 transfer attribute signals, 8-9 transfer termination, 8-22 bandwidth control on the IDMA channel, 19-11 bus protocol address pipelining, 8-6 arbitration phas
PAGE 1330
A–A Index internal statistics tables, 31-43 interworking functions automatic data forwarding, 31-6 ATM-to-TDM, 31-7 TDM-to-ATM, 31-7 channel associated signaling support, 31-10 clock synchronization, 31-9 mapping ATM-to-TDM CAS support, 31-14 CAS mapping, 31-14 CAS routing table, 31-12 CAS updates, 31-15 TDM-to-ATM support, 31-13 VC signaling to CAS blocks, 31-11 mapping TDM time slots, 31-9 timing issues, 31-7, 31-8 trunk condition, 31-10 memory structure, 31-22 parameter RAM, 31-22 OCASSR, 31-35 overvie
PAGE 1331
Index B–B interrupt queues, 30-81 maximum performance configuration, 30-95 OAM performance monitoring, 30-29, 30-62 OAM support, 30-27 operations and maintenance (OAM) support, 30-27 overview, 30-4 parameter RAM, 30-36 performance monitoring, 30-8 performance, maximum (configuration), 30-95 programming model, 30-87 receive connection table (RCT) AALn protocol-specific RCTs, 30-45 ATM channel code, 30-41 overview, 30-41 raw cell queue, 30-18 RCT entry format, 30-43 registers, 30-87 RxBD, 30-71 RxBD extensi
PAGE 1332
C–C Index BISYNC mode, 23-12 definition, 31-22 fast communications controllers (FCCs) Fast Ethernet mode receive, 35-22 transmit, 35-25 HDLC mode receive, 36-9 transmit, 36-12 overview receive, 29-10 transmit, 29-10 GCI mode monitor channel, 27-32 HDLC mode, 22-8 I2C controller receive, 39-12 transmit, 39-13 IDMA emulation auto buffer, 19-16 IDMA buffers, 19-24 multi-channel controllers (MCCs) receive, 28-43 transmit, 28-45 overview, 20-10, 31-36 serial management controllers (SMCs), 27-4 serial periphera
PAGE 1333
Index C–C ATM controller AAL1 sequence number protection table, 30-80 AALn RxBD, 30-6, 30-71 AALn TxBD, 30-5, 30-76 ABR flow control, 30-8, 30-19 address compression, 30-15 ATM layer statistics, 30-33 ATM memory structure, 30-36 ATM pace control (APC) unit ATM service types, 30-8 configuration, 30-96 data structure, 30-63 modes, 30-8 overview, 30-8 parameter tables, 30-64 priority table, 30-65 scheduling mechanism, 30-9 scheduling tables, 30-65 traffic type, 30-11 UBR+ traffic, 30-13 VBR traffic, 30-12 AT
PAGE 1334
C–C Index block diagram, 16-2 overview, 16-1 dual-port RAM accessing dual-port RAM, 14-18 block diagram, 14-18 buffer descriptors, 14-20 memory map, 14-19 overview, 14-17 parameter RAM, 14-20 fast communications controllers (FCCs) Fast Ethernet mode address recognition, 35-14 block diagram, 35-2 CAM interface, 35-7 collision handling, 35-17 connecting to the MPC8260, 35-4 error handling, 35-17 FCCE, 35-20 FCCM, 35-20 features list, 35-2 FPSMR, 35-18 frame reception, 35-6 frame transmission, 35-5 hash tabl
PAGE 1335
Index C–C buffer chaining, 19-16 buffers, 19-24 bus exceptions, 19-28 commands, 19-27 controlling 60x bus bandwidth, 19-11 DACKx, 19-13 DCM, 19-19 DONEx, 19-15 DREQx, 19-13 DTS/STS programming, 19-22 dual-address transfers, 19-10 edge-sensitive mode, 19-15 exceptions, bus, 19-28 external request mode, 19-8 features list, 19-5 IDMR, 19-24 IDSR, 19-24 level-sensitive mode, 19-14 normal mode, 19-9 operand transfers, recognizing, 19-29 operation, 19-16 overview, 19-5 parallel I/O register programming, 19-29 p
PAGE 1336
D–D Index master mode, 38-3 maximum receive buffer length (MRBLR), 38-11 multi-master operation, 38-4 parameter RAM, 38-10 programming example master, 38-16 slave, 38-17 programming model, 38-6 RxBD, 38-14 slave mode, 38-4 SPCOM, 38-10 SPIE, 38-9 SPIM, 38-9 SPMODE, 38-6 TxBD, 38-15 system interface unit (SIU) 60x bus monitor function, 4-2 add flexibility to CPM interrupt priorities, 4-12 BCR, 4-26 block diagram, 4-1 bus monitor, 4-3 clocks, 4-3 configuration functions, 4-2 configuration/protection logic b
PAGE 1337
Index E–F block diagram, 14-18 buffer descriptors, 14-20 memory map, 14-19 overview, 14-17 parameter RAM, 14-20 E EAMUX (external address multiplexing) signal, 11-42 EDO interface connection, MPC8260 to 60x bus, 11-92 Ethernet mode fast communications controller (FCC) address recognition, 35-14 block diagram, 35-2 CAM interface, 35-7 collision handling, 35-17 connecting to the MPC8260, 35-4 error handling, 35-17 FCCE, 35-20 FCCM, 35-20 features list, 35-2 FPSMR, 35-18 frame reception, 35-6 frame transmis
PAGE 1338
G–H Index saving power, 29-22 switching protocols, 29-22 timing control, 29-17 TxBD, 29-9 switching protocols, 29-22 transparent mode features list, 37-1 receive operation, 37-2 synchronization achieving, 37-2 example, 37-3 external signals, 37-3 in-line pattern, 37-2 transmit operation, 37-2 FCCE register ATM, 30-90 Ethernet, 35-20 FCC overview, 29-14 HDLC, 36-14 FCCM register ATM, 30-90 Ethernet, 35-20 FCC overview, 29-15 HDLC, 36-14 FCCS (FCC status) register, 29-15, 36-16 FCRx (function code registers
PAGE 1339
Index I–I accessing the bus, 22-18 bus controller, 22-16 collision detection, 22-16, 22-19 commands, 22-5 delayed RTS mode, 22-20 error handling, 22-5 fast communications controllers (FCCs) bit stuffing, 36-1 error control, 36-1 error handling, 36-6 FCCE, 36-14 FCCM, 36-14 FCCS, 36-16 features list, 36-1 FPSMR, 36-7 frame reception, 36-3 frame transmission, 36-2 overview, 36-1 parameter RAM, 36-3 programming model, 36-5 receive commands, 36-6 reception errors, 36-6 RxBD, 36-9 transmission errors, 36-6 tra
PAGE 1340
I–I Index IDMR (IDMA mask registers), 19-24 IDSR (IDMA event (status) register), 19-24 IEEE 1149.
PAGE 1341
Index J–M IDCR mode group activation, 33-74 start-up, 33-73 link addition, 33-65 Rx steps, 33-65 TX parameters, 33-66 link receive deactivation procedure, 33-68 link receive reactivation, 33-69 link removal, 33-67 Rx steps, 33-67 TX parameters, 33-68 receive event response, 33-70 receive link start-up procedure, 33-62 test pattern, 33-72 as initiator (NE), 33-72 as responder (FE), 33-72 transmit event response, 33-70 transmit ICP cell signalling, 33-62 TRL on-the-fly change, 33-69 software responsibilitie
PAGE 1342
M–M Index interface signals, 11-52 MPC8xx versus MPC8260, 11-63 OE timing, 11-58 overview, 11-51 programmable wait state configuration, 11-58 PSDVAL, 11-58 read access extended hold time, 11-59 relaxed timing, 11-56 SRAM configuration, 11-52 strobe signal behavior, 11-53 terminating external accesses, 11-61 timing configuration, 11-53 write enable deassertion timing, 11-54 GPLn timing example, 11-69 implementation differences between machines, 11-6 machine selection, 11-5 MAR in 60x-compatible mode, 11-77
PAGE 1343
Index N–P address latch enable (ALE), 11-10 data streaming mode, 8-26 extended transfer mode, 8-19 no-pipeline mode, 8-24 one-level pipeline mode, 8-24 single-MPC8260 bus mode, 8-2 ATM controller APC modes, 30-8 external rate mode, 30-6 internal rate mode, 30-6 transmit rate modes, 30-6 BISYNC mode, 23-1 cascaded mode, 18-3 echo mode, 27-1 HDLC mode, 22-1 hunt mode, 21-9 IDMA emulation edge-sensitive mode, 19-15 external request mode, 19-8 level-sensitive mode, 19-14 normal mode, 19-9 loopback mode, 27-1
PAGE 1344
P–P Index overview, 20-13 UART mode, 21-3 serial management controllers (SMCs) GCI mode, 27-31 overview, 27-5, 27-30 transparent mode, 27-6 UART mode, 27-6 serial peripheral interface (SPI), 38-10 Parity byte select (PBSE), 11-10 PCI bridge, 9-1 60x bus arbitration priority, 9-4 60x bus masters, 9-4 address map, 9-21 address decode flow chart, 9-21, 9-22, 9-23 address translation, 9-24 PCI inbound, 9-25 PCI outbound, 9-26 example, 9-24 programming, 9-24 SIU registers, 9-26 arbitration example, 9-20 burst
PAGE 1345
Index P–P inbound door bell machine check, 9-100 inbound post queue overflow, 9-100 outbound free queue overflow, 9-100 illegal register access error, 9-98 PCI bus error signals, 9-97 error reporting, 9-98 parity error (PERR), 9-98 system error (SERR), 9-98 PCI interface, 9-98 address parity error, 9-99 data parity error, 9-99 master-abort transaction termination, 9-99 nmi, 9-100 target-abort error, 9-100 in PowerQUICC II, 9-2 initialization, 9-3 interface, 9-5 bus arbitration, 9-19 alogrithm, 9-19 master
PAGE 1346
R–R Index HDLC bus protocol, 22-22 PSMR (protocol-specific mode register) AppleTalk mode, 26-4 TODR (transmit-on-demand register) AppleTalk mode, 26-4 transparent mode, 24-12 UART mode, 21-22 transparent mode NMSI programming example, 27-29 Promiscuous mode, see Transparent mode Promiscuous operation, 37-1 PSDMR (60x SDRAM mode register), 11-20 PSMR (protocol-specific mode register) AppleTalk mode, 26-4 BISYNC mode, 23-10 Ethernet mode, 25-14 HDLC bus protocol, programming, 22-22 HDLC mode, 22-7 overview,
PAGE 1347
Index R–R I2COM, 39-8 I2MOD, 39-6 IDMA emulation DCM, 19-19 IDMR, 19-24 IDSR, 19-24 IEEE 1149.
PAGE 1348
R–R Index I2O unit I2O registers inbound FIFO queue port register (IFQPR), 9-77 inbound message interrupt status register (IMISR), 9-80 messaging unit control register (MUCR), 9-83 outbound FIFO queue port register (OFQPR), 9-78 outbound message interrupt mask register (OMIMR), 9-79 outbound message interrupt status register (OMISR), 9-78 queue base address register (QBAR), 9-84 inbound FIFOs post_FIFL tail pointer register, 9-72 post_FIFO head pointer register (IPHPR), 9-72 outbound FIFOs free_FIFO tail
PAGE 1349
Index R–R serial management controllers(SMCs) GCI mode TxBD, 27-34 serial peripheral interface (SPI) SPCOM, 38-10 SPIE, 38-9 SPIM, 38-9 SPMODE, 38-6 system interface unit (SIU) BCR, 4-26 IMMR, 4-36 L_TESCR1, 4-42 L_TESCR2, 4-43 LCL_ACR, 4-31 LCL_ALRH, 4-32 LCL_ALRL, 4-32 PISCR, 4-46 PITC, 4-46 PITR, 4-47 PPC_ACR, 4-29 PPC_ALRH, 4-30 PPC_ALRL, 4-31 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-25 SIMR_H, 4-22 SIMR_L, 4-23 SIPNR_H, 4-21 SIPNR_L, 4-21 SIPRR, 4-18 SIUMCR, 4-33 SIVEC, 4-24 SWR, 4-7 SWSR, 4-3
PAGE 1350
S–S Index RSR (reset status) register, 5-4 RSTATE (internal receiver state) register, 28-10 RTMR (RISC timer mask register), 14-24 RTSCR (RISC time-stamp control register), 14-11 RTSR (RISC time-stamp register), 14-11 S SCC memory map, 3-17 SCCE (SCC event) register BISYNC mode, 23-15 HDLC mode, 22-12 transparent mode, 24-11 UART mode, 21-19 SCCE register Ethernet mode, 25-20 SCCM (SCC mask) register BISYNC mode, 23-15 HDLC mode, 22-12 transparent mode, 24-11 UART mode, 21-19 SCCM register Ethernet mode,
PAGE 1351
Index S–S controlling SCC timing, 20-17 DPLL operation, 20-21 features, 20-2 initialization, 20-17 interrupt handling, 20-16 parameter RAM, 20-13 reconfiguration, 20-24 reset sequence, 20-25 switching protocols, 20-25 transparent mode achieving synchronization, 24-3 commands, 24-6 DSR receiver SYNC pattern lengths, 24-3 end of frame detection, 24-5 error handling, 24-7 frame reception, 24-2 frame transmission, 24-2 inherent synchronization, 24-5 in-line synchronization, 24-5 overview, 24-1 programming exa
PAGE 1352
S–S Index TxBD, 27-27 UART mode character mode, 27-11 commands, 27-12 data handling, 27-11 error handling, 27-13 features list, 27-11 features not supported by SMCs, 27-10 frame format, 27-10 message-oriented mode, 27-11 overview, 27-10 parameter RAM, 27-6 programming example, 27-19 reception process, 27-11 RxBD, 27-13 transmission process, 27-11 TxBD, 27-17 Serial mode parameter RAM configuration, 33-26 Serial peripheral interface (SPI) block diagram, 38-1 clocking and pin functions, 38-2 commands, 38-12
PAGE 1353
Index T–T BCR, 4-26 block diagram, 4-1 bus monitor, 4-3 clocks, 4-3 configuration functions, 4-2 configuration/protection logic block diagram, 4-3 encoding the interrupt vector, 4-14 FCC relative priority, 4-12 highest priority interrupt, 4-13 IMMR, 4-36 interrupt controller features list, 4-7 interrupt source priorities, 4-9 interrupt vector calculation, 4-14 interrupt vector encoding, 4-14 interrupt vector generation, 4-14 L_TESCR1, 4-42 L_TESCR2, 4-43 LCL_ACR, 4-31 LCL_ALRH, 4-32 LCL_ALRL, 4-32 local b
PAGE 1354
U–U Index TESCRx (60x bus error status and control registers), 4-38, 11-33 TFCR (Tx buffer function code register) overview, 20-15 TGCR (timer global configuration registers), 18-3 Timers block diagram, 18-1 bus monitoring, 18-3 cascaded mode block diagram, 18-3 features, 18-1 general-purpose units, 18-2 pulse measurement, 18-3 Time-slot assigner connecting to the TSA, 15-7 Time-slot assigner (TSA) synchronization in transparent mode, 24-5 Timing SCC timing, controlling, 20-17 TM_CMD (RISC timer command)
PAGE 1355
Index U–U data sample control, 11-77 data valid, 11-77 differences between MPC8xx and MPC8260, 11-80 DRAM configuration example, 11-79 EDO interface example, 11-92 exception requests, 11-67 hierarchical bus interface example, 11-101 implementation differences with SDRAM machine and GPCM, 11-6 loop control, 11-76 memory access requests, 11-66 memory system interface example, 11-81 MPC8xx versus MPC8260, 11-80 overview, 11-63 programming the UPM, 11-67 RAM array, 11-69 RAM word, 11-70 refresh timer requests
PAGE 1356
U–U Index MPC8260 PowerQUICC II Family Reference Manual, Rev.
PAGE 1357
Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
PAGE 1358
I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.
PAGE 1359
Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports 35 36 37 38 39 40 Register Quick Reference Guide Reference Manual (Rev 1) Errata A B Glossary of Terms and Abbreviations Index GLO IND
PAGE 1360
35 36 37 38 39 40 Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports A B Register Quick Reference Guide Reference Manual (Rev 1) Errata GLO IND Glossary of Terms and Abbreviations Index