User manual

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 34-3
• Cell counters for performance monitoring:
— 16-bit counters count:
– HEC errored cells
– HEC single bit errored and corrected cells
– Idle/unassigned cells filtered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
— Maskable interrupt sent to the host when a counter expires
• Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
• May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported.
34.2 Functionality
The TC layer block is shown in Figure 34-2. The transmit and the receive parts are independent; the only
case in which they are synchronized is in cell echo mode.