User manual

FCC HDLC Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 36-17
Table 36-10 describes FCCS bits.
Table 36-10. FCCS Register Field Descriptions
Bits Name Description
0–4 — Reserved, should be cleared.
5 FG Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are
examined to see if a flag is present. FG is set as soon as an HDLC flag (0x7E) is received on the
line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are
examined. If another flag occurs, FG stays set for at least another eight bits. Otherwise, FG is
cleared and the search begins again.
• 0HDLC flags are not currently being received.
• 1HDLC flags are currently being received.
6 — Reserved, should be cleared.
7 ID Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is
cleared after a logic zero is received.
• 0The line is busy.
• 1The line is idle.