User manual

Memory Map
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 3-13
TC Layer 1
4
0x11400 TC1 mode register (TCMODE1)
4
R/W 16 bits 0x0000 34.4.1.1/34-7
0x11402 TC1 cell delineation state machine register (CDSMR1)
4
R/W 16 bits 0x0000 34.4.1.2/34-9
0x11404 TC1 event register (TCER1)
4
R/W 16 bits 0x0000 34.4.1.3/34-10
0x11406 TC1 received cells counter (TC_RCC1)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x11408 TC1 mask register (TCMR1)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x1140A TC1 filtered cells counter (TC_FCC1)
4
R/W 16 bits 0x0000 34.4.3.6/34-13
0x1140C TC1 corrected cells counter (TC_CCC1)
4
R/W 16 bits 0x0000 34.4.3.4/34-12
0x1140E TC1 idle cells counter (TC_ICC1)
4
R/W 16 bits 0x0000 34.4.3.5/34-12
0x11410 TC1 transmitted cells counter (TC_TCC1)
4
R/W 16 bits 0x0000 34.4.3.2/34-12
0x11412 TC1 error cells counter (TC_ECC1)
4
R/W 16 bits 0x0000 34.4.3.3/34-12
0x11414 Reserved — 12 bytes — —
TC Layer 2
4
0x11420 TC2 mode register (TCMODE2)
4
R/W 16 bits 0x0000 34.4.1.1/34-7
0x11422 TC2 cell delineation state machine register (CDSMR2)
4
R/W 16 bits 0x0000 34.4.1.2/34-9
0x11424 TC2 event register (TCER2)
4
R/W 16 bits 0x0000 34.4.1.3/34-10
0x11426 TC2 received cells counter (TC_RCC2)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x11428 TC2 mask register (TCMR2)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x1142A TC2 filtered cells counter (TC_FCC2)
4
R/W 16 bits 0x0000 34.4.3.6/34-13
0x1142C TC2 corrected cells counter (TC_CCC2)
4
R/W 16 bits 0x0000 34.4.3.4/34-12
0x1142E TC2 idle cells counter (TC_ICC2)
4
R/W 16 bits 0x0000 34.4.3.5/34-12
0x11430 TC2 transmitted cells counter (TC_TCC2)
4
R/W 16 bits 0x0000 34.4.3.2/34-12
0x11432 TC2 error cells counter (TC_ECC2)
4
R/W 16 bits 0x0000 34.4.3.3/34-12
0x11434 Reserved — 12 bytes — —
TC Layer 3
4
0x11440 TC3 mode register (TCMODE3)
4
R/W 16 bits 0x0000 34.4.1.1/34-7
0x11442 TC3 cell delineation state machine register (CDSMR3)
4
R/W 16 bits 0x0000 34.4.1.2/34-9
0x11444 TC3 event register (TCER3)
4
R/W 16 bits 0x0000 34.4.1.3/34-10
0x11446 TC3 received cells counter (TC_RCC3)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x11448 TC3 mask register (TCMR3)
4
R/W 16 bits 0x0000 34.4.1.4/34-11
0x1144A TC3 filtered cells counter (TC_FCC3)
4
R/W 16 bits 0x0000 34.4.3.6/34-13
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register R/W Size Reset Section/Page