User manual

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-16 Freescale Semiconductor
Note that the interrupt vector table differs from the interrupt priority table in only two ways:
• FCC, SCC, and MCC vectors are fixed; they are not affected by the SCC group mode, spread mode,
or the relative priority order of the FCCs, SCCs, and MCC.
• An error vector exists as the last entry in Table 4-3. The error vector is issued when no interrupt is
requesting service.
4.2.4.1 Port C External Interrupts
There are 16 external interrupts, coming from the parallel I/O port C pins, PC[0–15]. When ones of these
pins is configured as an input, a change according to the SIU external interrupt control register (SIEXR)
causes an interrupt request signal to be sent to the interrupt controller. PC[0–15] lines can be programmed
to assert an interrupt request upon any change. Each port C line asserts a unique interrupt request to the
interrupt pending register and has a different internal interrupt priority level within the interrupt controller.
44 TC Layer
3
0b10_1100
45–47 Reserved 0b10_11xx
48 PC15 0b11_0000
49 PC14 0b11_0001
50 PC13 0b11_0010
51 PC12 0b11_0011
52 PC11 0b11_0100
53 PC10 0b11_0101
54 PC9 0b11_0110
55 PC8 0b11_0111
56 PC7 0b11_1000
57 PC6 0b11_1001
58 PC5 0b11_1010
59 PC4 0b11_1011
60 PC3 0b11_1100
61 PC2 0b11_1101
62 PC1 0b11_1110
63 PC0 0b11_1111
1
On MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices.
2
Reserved on MPC8250 and MPC8255.
3
On MPC8264 and MPC8266 only. Reserved on all other devices.
Table 4-3. Encoding the Interrupt Vector (continued)
Interrupt Number Interrupt Source Description Interrupt Vector