User manual

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-47
Table 4-22 describes PITC fields.
4.3.3.3 Periodic Interrupt Timer Register (PITR)
The periodic interrupt timer register (PITR), shown in Figure 4-40, is a read-only register that shows the
current value in the periodic interrupt down counter. The PITR counter is not affected by reads or writes
to it.
0 15
Field PITC
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x10244
16 31
Field —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10246
Figure 4-39. Periodic interrupt Timer Count Register (PITC)
Table 4-22. PITC Field Descriptions
Bits Name Description
0–15 PITC Periodic interrupt timing count. Bits 0–15 are defined as the PITC, which contains the count for the
periodic timer. Setting PITC to 0xFFFF selects the maximum count period.
16–31 — Reserved, should be cleared.
0 15
Field PIT
Reset 0000_0000_0000_0000
R/W Read Only
Addr 0x0x10248
16 31
Field —
Reset 0000_0000_0000_0000
R/W Read Only
Addr 0x1024A
Figure 4-40. Periodic Interrupt Timer Register (PITR)