User manual

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
8-10 Freescale Semiconductor
Table 8-2. Trans fer Type Encoding
TT[0–4]
1
60x Bus Specification
2
PowerQUICC II as Bus Master
PowerQUICC I
I as Snooper
PowerQUICC II
as Slave
Command Transaction Bus Trans. Transaction Source Action on Hit Action on Slave Hit
00000 Clean block Address
only
Address only
(if enabled)
dcbst (if enabled) Not applicable AACK
asserted;
PowerQUICC II takes
no further action.
00100 Flush block Address
only
Address only
(if enabled)
dcbf (if enabled) Not applicable AACK
is asserted;
PowerQUICC II takes
no further action.
01000 sync Address
only
Address only
(if enabled)
sync (if enabled) Not applicable Assert AACK
. BG is
negated until
PowerQUICC II
buffers are flushed.
01100 Kill block Address
only
Address only dcbz or dcbi (if
enabled)
Flush, cancel
reservation
AACK
is asserted.
10000 eieio Address
only
Address only
(if enabled)
eieio (if enabled) Not applicable Assert AACK
. BG is
negated until
PowerQUICC II
buffers are flushed.
101 00 Graphics
write
Single-beat
write
Single-beat
write
(non-GLB)
ecowx Not applicable No action.
11000 TLB
invalidate
Address
only
Not applicable Not applicable Not applicable AACK
is asserted;
PowerQUICC II takes
no further action.
11100 Graphics
read
Single-beat
read
Single-beat
read
(non-GBL)
eciwx Not applicable PowerQUICC II takes
no action.
00001 lwarx
reservation
set
Address
only
Not applicable Not applicable Not applicable Address-only
operation. AACK
is
asserted;
PowerQUICC II takes
no further action.
00101 Reserved — Not applicable Not applicable Not applicable Illegal
01001 tlbsync Address
only
Not applicable Not applicable Not applicable Address-only
operation. AACK
is
asserted;
PowerQUICC II takes
no further action.
01101 icbi Address
only
Not applicable Not applicable Not applicable Address-only
operation. AACK
is
asserted;
PowerQUICC II takes
no further action.