User manual

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-33
Figure 9-20. Discard Timer Control register (PTCR)
Table 9-7. describes PTCR fields.
9.11.1.7 General Purpose Control Register (GPCR)
The general purpose control register (GPCR), shown in Figure 9-21, contains control bits for rerouting
interrupts and adjusting the DMA controller’s 60x bandwidth.
31 30 24 23 16
Field EN — PTV
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x1087A
15 0
Field PTV
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10878
Table 9-7. PTCR Field Descriptions
Bits Name Description
31 Enable Discard timer enable.
0 Disable the discard timer
1 Enable the discard timer
30–24 — Reserved
23–0 Preload timer value Preload value for 24-bit discard timer. Delayed PCI read transactions to a
non-prefetchable address space remain valid within the PCI bridge
a minimum of
(2
24
- Preload Timer Value) internal clock cycles. The discard timer is used to
discard delayed reads from non-prefetchable address space if the master has not
repeated the transaction in
n internal clock cycles, where n = (2
24
- Preload Timer
Value). Valid Preload Timer Values are in the range 0x000000–0xFFFFFE.
Example: To discard a delayed completion if the PCI master has not repeated the
transaction in 2
15
PCI clocks and the internal frequency is 2 to 1 to the PCI bus. The
Preload Timer Value should equal 2
24
-2
16
(0xFF0000).