User manual

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-39
9.11.1.12 PCI Error Address Capture Register (PCI_EACR)
The PCI error address capture register (PCI_EACR), shown in Figure 9-26, stores the address associated
with the first PCI error captured.
Figure 9-26. PCI Error Address Capture Register (PCI_EACR)
Table 9-13. describes PCI_EACR fields.
Table 9-12. ECR Field Descriptions
Bits Name Description
31–13 — Reserved, should be cleared.
12 I2O_DBMC I
2
O doorbell machine check
0 ESR[I2O_DBMC] causes an interrupt.
1 ESR[I2O_DBMC] (if enabled) causes a machine check.
11 NMI General error/interrupt indication.
10 IRA Illegal register access with incorrect size.
9 I2O_IPQO I2O inbound post queue overflow.
8 I2O_OFQO I2O outbound free queue overflow.
7 PCI_PERR_WR PCI parity error received on a write.
6 PCI_PERR_RD PCI parity error received on a read.
5 PCI_SERR PCI SERR
received.
4 PCI_TAR_ABT PCI Target Abort
3 PCI_NO_RSP PCI no response (no DEVSEL
; master abort).
2 PCI_DATA_PAR_RD PCI read data parity error.
1 PCI_DATA_PAR_WR PCI write data parity error.
0 PCI_ADDR_PAR PCI address parity error (read or write).
31 16
Field PCI_EAR
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10892
15 0
Field PCI_EAR
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10890