User manual

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-46 Freescale Semiconductor
Figure 9-32. PCI Bridge PCI Configuration Registers
The PCI configuration registers are accessible from the core through an indirect method discussed in
“Section 9.11.2.26, PCI Configuration Register Access from the Core” on page 62. The registers are
accessible from the PCI bus through the PCI configuration transaction when the PCI bridge is in agent
mode.
The following sections describe the individual PCI configuration registers.
9.11.2.1 Vendor ID Register
Figure 9-33 and Table 9-20 describe the vendor ID register.
3E MIN GNT R 0x00 9.11.2.20/9-57
3F MAX LAT R 0x00 9.11.2.21/9-58
40 Reserved — — —
44 PCI function R/W 0x0000 9.11.2.22/9-58
46 PCI arbiter control register R/W Mode-dependent 9.11.2.23/9-59
48 Hot swap register block R/W 0x00nn_0006 9.11.2.24/9-60
9.11.2.25/9-61
Address offset
(Hex)
00 Device ID (0x18C0) Vendor ID (0x1057)
04 PCI status PCI command
08 Class code Subclass code Standard programming Revision ID
0C BIST control Header type Latency timer Cache line size
10 PIMMR base address register
14 GPLA base address register 0
18 GPLA base address register 1
•
•
—
•
•
2C Subsystem ID Subsystem vendor ID
•
•
—
•
•
34 — Capabilities pointer
38 —
3C MAX LAT MIN GNT Interrupt pin Interrupt line
40 —
44 PCI arbiter control PCI function
48 Hot swap CSR Hot swap capability ID
Table 9-19. PCI Bridge PCI Configuration Registers (continued)
Address
(offset)
Register Access Reset Section/Page