User manual

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-68 Freescale Semiconductor
Figure 9-62. Outbound Doorbell Register (ODR)
9.12.2.2 Inbound Doorbell Register (IDR)
IDR, described in Figure 9-63 and Table 9-49, is accessible from the PCI bus and the 60x bus in both host
and agent modes.
Figure 9-63. Inbound Doorbell Register (IDR)
31 29 28 16
Field — ODR x
Reset 0000_0000_0000_0000
R/W Refer to Tab l e 9 -4 8 .
Addr 0x10462
15 0
Field ODR x
Reset 0000_0000_0000_0000
R/W Refer to Tab l e 9 -4 8 .
Addr 0x10460
Table 9-48. ODR Field Descriptions
Bits Name Access Description
31–29 — R Reserved, should be cleared.
28–0 ODR
x Write 1 to set from local processor.
Write 1 to clear from PCI.
Outbound door bell x , where x is each bit. Writing a bit in
this register from the local processor causes an interrupt
(INTA
) to be generated.
31 30 16
Field IMC IDR x
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x1046A
15 0
Field IDR x
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10468