User manual

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-83
9.12.3.4.7 Messaging Unit Control Register (MUCR)
This register allows software to enable and setup the size of the inbound and outbound FIFOs. MUCR
should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from
the PCI bus have undefined results.
Figure 9-79. Messaging Unit Control Register (MUCR)
Table 9-64 describes MUCR fields.
1 IM1IM Inbound message 1 interrupt mask
0 Inbound doorbell interrupt is allowed.
1 Inbound doorbell interrupt is masked.
0 IM0IM Inbound message 0 interrupt mask
0 Inbound message 0 interrupt is allowed.
1 Inbound message 0 interrupt is masked.
31 16
Field —
Reset 0000_0000_0000_0002
R/W R/W
Addr 0x104E6
15 65 10
Field — CQS CQE
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x104E4
Table 9-64. MUCR Field Descriptions
Bits Name Access Description
31–6 — R Reserved, should be cleared.
Table 9-63. IMIMR Field Descriptions (continued)
Bits Name Description