User manual

Memory Controller

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor 11-43

P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory controller to add one cycle for

each SDRAM command. Figure 11-27 illustrates the timing when BUFCMD equals 1.

Figure 11-27. BUFCMD = 1

11.4.7 SDRAM Interface Timing

Figure 11-28 through Figure 11-36 show SDRAM timing for various types of accesses.

Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3

CLK

SDAMUX

CMD strobes

MA[0–11] Row Column

Activate Read NOPNOP

(without cs)

ALE

Command setup cycle Command setup cycle

CLK

ALE

SDRAS

SDCAS

MA[0–11]

Row Column

DQM

Data