User manual

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-56 Freescale Semiconductor
Figure 11-45. GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)
11.5.1.3 Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When
TRLX = 1 and ACS ≠ 00, an additional cycle between the address and strobes is inserted by the
PowerQUICC II memory controller. See Figure 11-46 and Figure 11-47.
Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
Clock
Address
PSDVAL
CS
WE
Data
CSNT = 1
ACS = 11
ACS = 10
Clock
Address
PSDVAL
CS
BCTL x
WE
OE
Data
ACS = 10
ACS = 11