User manual

Secondary (L2) Cache Support
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
12-6 Freescale Semiconductor
Figure 12-3. External L2 Cache in ECC/Parity Mode
12.2 L2 Cache Interface Parameters
The L2 cache interface parameters in the bus configuration register (BCR) control the configuration and
operation of the PowerQUICC II’s L2 interface. The parameters should be configured as follows:
• BCR[EBM] = 1—PowerQUICC II in 60x-compatible mode.
• BCR[L2C] = 1—L2 cache is present.
TS, TT[0–4], TBST
A[0–31]
CI
, GBL, TA, DBB, TEA
CPU_BR, CPU_BG, CPU_DBG
D[0–63],DP[0–7]
PowerQUICC II
TS
, TT[0–4], TBST
CI, GBL, TA, DBB, TEA
AACK, ARTRY AACK, ARTRY
CPU_BR,CPU_BG,CPU_DBG
L2_CLAIML2_HIT
A[0–28]
D[0–63], DP[0–7]
Memory Controller
SDRAM Main Memory
Latch
MUX
I/O Devices
MPC2605
TSIZE[0]
(pull down)
WT
(pull down)
TSIZ[0–2]
(pull downs)
A[29–31]
(pull downs)
BR
DBG
L2BR
L2DBG
BG L2BG
(pull up)(pull up)