User manual

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-8 Freescale Semiconductor
14.3.6 Execution from RAM
The CP has an option to execute microcode from a portion of user RAM located in the dual-port RAM. In
this mode, the CP fetches instructions from both the dual-port RAM and its own private ROM. This mode
allows Freescale to add new protocols or enhancements to the PowerQUICC II in the form of RAM
microcode packages. If preferred, the user can obtain binary microcode from Freescale and load it into the
dual-port RAM.
14.3.7 RISC Controller Configuration Register (RCCR)
The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures the CP to run
microcode from ROM or RAM and controls the CP’s internal timer.
16 FCC3 transmit
3
17 SCC1 receive
18 SCC1 transmit
19 SCC2 receive
20 SCC2 transmit
21 SCC3 receive
22 SCC3 transmit
23 SCC4 receive
24 SCC4 transmit
25 SMC1 receive
26 SMC1 transmit
27 SMC2 receive
28 SMC2 transmit
29 SPI receive
30 SPI transmit
31 I
2
C receive
32 I
2
C transmit
33 RISC timer table
34 IDMA[1–4] emulation (option 3)
1
1
The priority of each IDMA channel is programmed independently. See the
RCCR[DR
x QP] description in Section 14.3.7, “RISC Controller Configuration
Register (RCCR).”
2
Not on MPC8250 and MPC8255.
3
Not on MPC8255.
Table 14-2. Peripheral Prioritization (continued)
Priority Request