User manual

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-14 Freescale Semiconductor
14.4.1.1 CP Commands
The CP command opcodes are shown in Table 14-7.
6–10 SBC Sub-block code. Set by the core to specify the sub-block on which the command is to operate. Set
according to OPCODE[28-31]. Refer to Table 13-7.
Sub-block Code Page Sub-block Code Page
FCC1
1
01110: ATM transmit
(OPCODE = 1010)
10000: all other commands
00100 SPI 01010 01001
FCC2
1
01110: ATM transmit
(OPCODE = 1010)
10001: all other commands
00101 I
2
C 01011 01010
FCC3 10010 00110 Timer 01111 01010
SCC1 00100 00000 MCC1
2
11100 00111
SCC2 00101 00001 MCC2 11101 01000
SCC3 00110 00010 IDMA1 10100 00111
SCC4 00111 00011 IDMA2 10101 01000
SMC1 01000 00111 IDMA3 10110 01001
SMC2 01001 01000 IDMA4 10111 01010
RAND 01110 01010
11–14 — Reserved
15 FLG Command semaphore flag. Set by the core and cleared by the CP.
0 The CP is ready to receive a new command.
1 The CPCR contains a command that the CP is currently processing. The CP clears this bit at
the end of command execution or after reset.
16–17 — Reserved
18–25 MCN MCC channel number. Specifies the channel number in the case of an MCC command.
In FCC protocols, this field contains the protocol code as follows:
0x00 HDLC/transparent
0x0A ATM
3
0x0C Ethernet
26-27 — Reserved
28–31 OPCODE Operation code. Settings are listed in Table 14-7.
1
Set according to OPCODE[28-31]. If OPCODE is 1010, SBC must be 01110. Refer to Table 14-7. ATM functionality
not available on the MPC8250.
2
Not available on the MPC8250 and the MPC8255.
3
Not available on the MPC8250.
Table 14-6. CP Command Register Field Descriptions (continued)
Bit Name Description