User manual

Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 29-3
Figure 29-1. FCC Block Diagram
29.2 General FCC Mode Registers (GFMR x )
Each FCC contains a general FCC mode register (GFMRx) that defines common FCC options and selects
the protocol to be run. The GFMRx are read/write registers cleared at reset. Figure 29-2 shows the GFMR
format.
Table 29-1. Internal Clocks to CPM Clock Frequency Ratio
Mode Internal Clock: CPM clock frequency ratio
HDLC 1 bit 1:4
Transparent 1 bit 1:4
HDLC nibble 1:6
Fast Ethernet 1:3 (1:3.5 preferred)
ATM 1:3 (1:3.5 preferred)
Control
Registers
ShifterShifter Delimiter
Clock
Generator
Delimiter
Decoder
Encoder
Receive
Control
Unit
Transmit
Control
Unit
Receive
Data
FIFO
Transmit
Data
FIFO
Modem Lines
Modem Lines
60x Bus
Peripheral Bus
TCLK
RCLK
Internal Clocks
RXD
TXD