Computer Accessories User Manual

Block Guide — S12EETX4KV0 V00.04
27
Figure 4-1 Determination Procedure for PRDIV8 and EDIV Bits
PRDIV8=1
yes
no
PRDIV8=0 (reset)
12.8MHz?
EECLK=(PRDCLK)/(1+EDIV[5:0])
PRDCLK=oscillator_clock
PRDCLK=oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[µs])
no
EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1
yes
START
Tbus < 1µs?
an integer?
EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))
1/EECLK[MHz] + Tbus[µs] > 5
AND
EECLK
> 0.15MHz
?
END
yes
no
EDIV[5:0] > 4?
ALL COMMANDS IMPOSSIBLE
yes
no
ALL COMMANDS IMPOSSIBLE
no
TRY TO DECREASE Tbus
yes
oscillator_clock
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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