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MC9S12XDP512

Data Sheet

MC9S12XDP512

Rev. 2.11

5/2005

Summary of content (986 pages)

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MC9S12XDP512 Data Sheet HCS12X Microcontrollers MC9S12XDP512 Rev. 2.11 5/2005 freescale.
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MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision History Date Revision Level April, 2005 02.07 New Book May, 2005 02.08 Minor corrections May, 2005 02.
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Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) . . . . . . . . . . . . . . . . . . . 23 Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2). . . . . . . . . . . . . 101 Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) . . . . . . . . . . . . . 145 Chapter 4 Port Integration Module (S12XDP512PIMV2) . . . . . . . . . . . . . 177 Chapter 5 Clocks and Reset Generator (S12CRGV6) . . . . . . . . . . . . . . . 271 Chapter 6 Pierce Oscillator (S12XOSCLCPV1) . . . . . . . . .
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Section Number Chapter 23 Title Page Memory Mapping Control (S12XMMCV2) . . . . . . . . . . . . . . . . 881 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 Appendix C Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Section Number Title Page Chapter 1 Device Overview (MC9S12XDP512V2) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 2.4 2.5 2.6 2.7 2.8 Title Page 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.4.2 Flash Commands . . . . . . . . . . . . . . . . . .
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Section Number 3.8 Title Page Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.1 4.2 4.3 4.4 4.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 5.6 Title Page 5.5.4 Power On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 5.6.1 Real Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 5.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 7.5 7.6 Title Page Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 9.6 9.7 9.8 9.9 Title Page Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.6.2 Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 9.6.3 Leaving Debug Mode . . . . . . . . . . . . . . .
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Section Number Title Page 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 13.4 13.5 13.6 13.7 Title Page 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 13.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 16.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 16.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 16.4.3 Transmission Formats . . . . . . . . . . . . . . . . .
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Section Number Title Page 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 20.3 Memory Map and Register Definition . . . . . . . . . . . . . . .
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Section Number Title Page 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number A.2 A.3 A.4 A.5 A.6 A.7 A.8 Title Page A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 A.1.7 Operating Conditions . . . . . . . . . . . . . . . .
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Section Number Title Page Appendix C Recommended PCB Layout Appendix D Derivative Differences D.1 D.2 D.3 D.4 D.5 D.6 Memory Sizes and Package Options S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 Memory Sizes and Package Options S12XA - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 MC9S12XD-Family Flash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 Peripheral Sets S12XD - Family .
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Section Number Title Page MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1 Introduction The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family. Based around an enhanced S12 core, the MC9S12XD-Family will deliver 2 to 5 times the performance of a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12. The MC9S12XD-Family introduces the performance boosting XGATE module.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.
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Chapter 1 Device Overview (MC9S12XDP512V2) • • • • • • • Five 1 M bit per second, CAN 2.
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Chapter 1 Device Overview (MC9S12XDP512V2) • 1.1.
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Chapter 1 Device Overview (MC9S12XDP512V2) SCI1 SPI0 DDRA PTA Timer 4-Channel 16-Bit with Prescaler for Internal Timebases Non-Multiplexed External Bus Interface (EBI) DDRB DDRC DDRD PTB SCI3 RXD TXD Digital Supply 2.5 V VDD1,2 VSS1,2 PLL Supply 2.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.4 Device Memory Map Table 1-1shows the device register memory map of the MC9S12XDP512. Table 1-1.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-1.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.5 1.1.5.
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Chapter 1 Device Overview (MC9S12XDP512V2) XGATE Local Memory Map Device Global Memory Map $00_0000 2K Registers $00_0800 $00_1000 $0000 2K Registers $0F_8000 $0800 RAM $0F_FFFF $10_0000 FLASH $7FFF $8000 RAM $78_0800 30KB FLASH $FFFF $78_7FFF $78_8000 Not Used by XGATE $7F_FFFF Figure 1-3. Local-to-Global Address Mapping XGATE MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.5.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.6 Detailed Register Map The following tables show the detailed register map of the MC9S12XDP512.
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4 Address Name 0x0010 GPAGE 0x0011 DIRECT 0x0012 Reserved 0x0013 MMCCTL1 0x0014 Reserved 0x0015 Reserved 0x0016 RPAGE 0x0017 EPAGE Bit 7 R W R W R W R W R W R W R W R W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 0 0 0 0 0 EROMON ROMHM ROMON 0 0 0 0 0 0 0 0 0 0 0
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0020–0x0027 Debug Module (S12XDBG) Map Address Name 0x0020 DBGC1 0x0021 DBGSR 0x0022 DBGTCR 0x0023 DBGC2 0x0024 DBGTBH 0x0025 DBGTBL 0x0026 DBGCNT 0x0027 DBGSCRX 0x00281 DBGXCTL (COMPA/C) 0x00282 DBGXCTL (COMPB/D) 0x0029 DBGXAH 0x002A DBGXAM 0x002B DBGXAL 0x002C DBGXDH 0x002D DBGXDL 0x002E DBGXDHM 0x002F DBGXDLM 1 2 Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ARM TBF Bit 6 0 TRIG EXTF Bit 5 B
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4 Address Name 0x0030 PPAGE 0x0031 Reserved R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5 Address Name 0x0032 PORTK 0x0033 DDRK R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address Name 0x0040 TIOS 0x0041 CFORC 0x0042 OC7M 0x0043 OC7D 0x0044 TCNT (hi) 0x0045 TCNT (lo) 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 TCTL2 0x004A TCTL3 0x004B TCTL4 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 TC0 (hi) 0x0051 TC0 (lo) 0x0052 TC1 (hi) 0x0053 TC1 (lo) 0x0054 TC2 (hi) 0x0055 TC2 (lo) R W R W R W R W R W R W
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3) Address Name 0x0056 TC3 (hi) 0x0057 TC3 (lo) 0x0058 TC4 (hi) 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACN3 (hi) 0x0063 PACN2 (lo) 0x0064 PACN1 (hi) 0x0065 PACN0 (lo) 0x0066 MCCTL 0x0067 MCFLG 0x0068 ICPAR 0x0069 DLYCT 0x006A ICOVW 0x006B
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3) Address Name 0x006D TIMTST 0x006E PTPSR 0x006F PTMCPSR 0x0070 PBCTL 0x0071 PBFLG 0x0072 PA3H 0x0073 PA2H 0x0074 PA1H 0x0075 PA0H 0x0076 MCCNT (hi) 0x0077 MCCNT (lo) 0x0078 TC0H (hi) 0x0079 TC0H (lo) 0x007A TC1H (hi) 0x007B TC1H (lo) 0x007C TC2H (hi) 0x007D TC2H (lo) 0x007E TC3H (hi) 0x007F TC3H (lo) Bit 7 R 0 W R PTPS7 W R PTMPS7 W R 0 W R 0 W R
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Address Name 0x0080 ATD1CTL0 0x0081 ATD1CTL1 0x0082 ATD1CTL2 0x0083 ATD1CTL3 0x0084 ATD1CTL4 0x0085 ATD1CTL5 0x0086 ATD1STAT0 0x0087 Reserved 0x0088 ATD1TEST0 0x0089 ATD1TEST1 0x008A ATD1STAT2 0x008B ATD1STAT1 0x008C ATD1DIEN0 0x008D ATD1DIEN 0x008E ATD1PTAD0 0x008F ATD1PTAD1 0x0090 ATD1DR0H 0x0091 ATD1DR0L 0x0092 ATD1DR1H 0x0093 ATD1DR1L
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 2 of 3) Address Name 0x0096 ATD1DR3H 0x0097 ATD1DR3L 0x0098 ATD1DR4H 0x0099 ATD1DR4L 0x009A ATD1DR5H 0x009B ATD1DR5L 0x009C ATD1DR6H 0x009D ATD1DR6L 0x009E ATD1DR7H 0x009F ATD1DR7L 0x00A0 ATD1DR8H 0x00A1 ATD1DR8L 0x00A2 ATD1DR9H 0x00A3 ATD1DR9L 0x00A4 ATD1DR10H 0x00A5 ATD1DR10L 0x00A6 ATD1DR11H 0x00A7 ATD1DR11L 0x00A8 ATD1DR12H 0x00A9 ATD1DR12L
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 3 of 3) Address Name 0x00AC ATD1DR14H 0x00AD 0x00AE 0x00AF R W R ATD1DR14L W R ATD1DR15H W R ATD1DR15L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit 0 0x00B0–0x00B7 Inter IC Bus (IIC1) Map Address Name 0x00B0 IBAD 0x00B1 IBFD 0x
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map (continued) Address Name 0x00BB SCI2CR2 0x00BC SCI2SR1 0x00BD SCI2SR2 0x00BE SCI2DRH 0x00BF SCI2DRL 1 2 R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 AMAP R8 R7 T7 T8 R6 T6 RAF Those registers a
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name 0x00C8 SCI0BDH1 0x00C9 SCI0BDL1 0x00CA SCI0CR11 0x00C8 SCI0ASR12 0x00C9 SCI0ACR12 0x00CA SCI0ACR22 0x00CB SCI0CR2 0x00CC SCI0SR1 0x00CD SCI0SR2 0x00CE SCI0DRH 0x00CF SCI0DRL 1 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address 1 2 Name 0x00D5 SCI1SR2 0x00D6 SCI1DRH 0x00D7 SCI1DRL Bit 7 R W R W R W AMAP R8 R7 T7 Bit 6 Bit 5 0 0 T8 R6 T6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero Those registers are accessible if the AMAP bit in th
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00E0–0x00E7 Inter IC Bus (IIC0) Map (continued) Address Name 0x00E5 Reserved 0x00E6 Reserved 0x00E7 Reserved R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address Name 0x00F8 SPI2CR1 0x00F9 SPI2CR2 0x00FA SPI2BR 0x00FB SPI2SR 0x00FC Reserved 0x00FD SPI2DR 0x00FE Reserved 0x00FF Reserved R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 MODFEN BIDIROE SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0100–0x010F Flash Control Register (FTX512K4) Map (continued) Address Name 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0110–0x011B EEPROM Control Register (EETX4K) Map Address Name 0x0110 ECLKDIV 0x0111 Reserved 0x0112 Reserved 0x0113 ECNFG 0x0114 EPROT
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4 Address Name 0x011C RAMWPC 0x011D RAMXGU 0x011E RAMSHL 0x011F RAMSHU Bit 7 R W R W R W R W RPWE 1 1 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 AVIE AVIF XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 SHL6 SHL5 SHL4 SHL3 SHL2 SHL1 SHL0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 0x0120–0x012F Interrupt Module (S12XINT) Map Address Name 0x0120 Reserved 0x0121 IVBR 0x0122
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address Name 0x0130 SCI4BDH1 0x0131 SCI4BDL1 0x0132 SCI4CR11 0x0130 SCI4ASR12 0x0131 SCI4ACR12 0x0132 SCI4ACR22 0x0133 SCI4CR2 0x0134 SCI4SR1 0x0135 SCI4SR2 0x0136 SCI4DRH 0x0137 SCI4DRL 1 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SB
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued) Address 1 2 Name 0x013D SCI5SR2 0x013E SCI5DRH 0x013F SCI5DRL Bit 7 R W R W R W AMAP R8 R7 T7 Bit 6 Bit 5 0 0 T8 R6 T6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK RAF Those registers are accessible if the AMAP bit in the SCI5SR2 regist
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued) Address Name 0x0150– CAN0IDAR0– 0x0153 CAN0IDAR3 0x0154– CAN0IDMR0– 0x0157 CAN0IDMR3 0x0158– CAN0IDAR4– 0x015B CAN0IDAR7 0x015C CAN0IDMR4– – CAN0IDMR7 0x015F R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 R 0x0
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Chapter 1 Device Overview (MC9S12XDP512V2) Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name 0xXX0x XX10 Extended ID CANxTIDR1 Standard ID 0xXX12 0xXX13 0xXX14 – 0xXX1B 0xXX1C 0xXX1D 0xXX1E 0xXX1F R W R W Extended ID R CANxTIDR2 W Standard ID R W Extended ID R CANxTIDR3 W Standard ID R W R CANxTDSR0– CANxTDSR7 W R W R CANxTTBPR W R CANxTTSRH W R CANxTTSRL W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 I
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 2 of 3) Address Name 0x0189 CAN1TAAK 0x018A CAN1TBSEL 0x018B CAN1IDAC 0x018C Reserved 0x018D CAN1MISC 0x018E CAN1RXERR 0x018F CAN1TXERR 0x0190 CAN1IDAR0 0x0191 CAN1IDAR1 0x0192 CAN1IDAR2 0x0193 CAN1IDAR3 0x0194 CAN1IDMR0 0x0195 CAN1IDMR1 0x0196 CAN1IDMR2 0x0197 CAN1IDMR3 0x0198 CAN1IDAR4 0x0199 CAN1IDAR5 0x019A CAN1IDAR6 0x019B CAN1IDAR7 0x019C CAN1IDMR4 0x019D
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 3 of 3) Address Name R 0x019F CAN1IDMR7 W R 0x01A0– CAN1RXFG 0x01AF W R 0x01B0– CAN1TXFG 0x01BF W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) 0x01C0–0x01FF Freesc
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map (continued) Address Name 0x01D1 CAN2IDAR1 0x01D2 CAN2IDAR2 0x01D3 CAN2IDAR3 0x01D4 CAN2IDMR0 0x01D5 CAN2IDMR1 0x01D6 CAN2IDMR2 0x01D7 CAN2IDMR3 0x01D8 CAN2IDAR4 0x01D9 CAN2IDAR5 0x01DA CAN2IDAR6 0x01DB CAN2IDAR7 0x01DC CAN2IDMR4 0x01DD CAN2IDMR5 0x01DE CAN2IDMR6 0x01DF CAN2IDMR7 0x01E0– 0x01EF CAN2RXFG 0x01F0– 0x01FF CAN2TXFG R W R W R W R W R W R W R W R W R W R W R W R W
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) Address Name 0x0200 CAN3CTL0 0x0201 CAN3CTL1 0x0202 CAN3BTR0 0x0203 CAN3BTR1 0x0204 CAN3RFLG 0x0205 CAN3RIER 0x0206 CAN3TFLG 0x0207 CAN3TIER 0x0208 CAN3TARQ 0x0209 CAN3TAAK 0x020A CAN3TBSEL 0x020B CAN3IDAC 0x020C Reserved 0x020D Reserved 0x020E CAN3RXERR 0x020F CAN3TXERR 0x0210 CAN3IDAR0 0x0211 CAN3IDAR1 0x0212 CAN3IDAR2 0x0213 CAN3IDAR3 0x0214 CAN3IDMR0 0x0215 CAN3IDM
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) (continued) Address Name 0x0216 CAN3IDMR2 0x0217 CAN3IDMR3 0x0218 CAN3IDAR4 0x0219 CAN3IDAR5 0x021A CAN3IDAR6 0x021B CAN3IDAR7 0x021C CAN3IDMR4 0x021D CAN3IDMR5 0x021E CAN3IDMR6 0x021F CAN3IDMR7 0x0220– 0x022F CAN3RXFG 0x0230– 0x023F CAN3TXFG R W R W R W R W R W R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AM7 AM6
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 2 of 4) Address Name 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 MODRR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP R W R W R W R W R W R W R W R W R W R W R W
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 3 of 4) Address Name 0x0260 PTH 0x0261 PTIH 0x0262 DDRH 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 Reserved 0x0271 PT1AD0 0x0272 Reserved 0x0273 DDR1AD0 0x0274 Reserved 0x0275 RDR1AD0 0x0276 Reserved 0x0277 PER1AD0 R W R W R W R W R W R
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 4 of 4) Address Name 0x0278 PT0AD1 0x0279 PT1AD1 0x027A DDR0AD1 0x027B DDR1AD1 0x027C RDR0AD1 0x027D RDR1AD1 0x027E PER0AD1 0x027F PER1AD1 R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT0AD1 23 PT0AD1 22 PT0AD1 21 PT0AD1 20 PT0AD1 19 PT0AD1 18 PT0AD1 17 PT0AD1 16 PT1AD1 15 PT1AD1 14 PT1AD1 13 PT1AD1 12 PT1AD1 11 PT1AD1 10 PT1AD
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map (continued) Address Name 0x028D CAN4MISC 0x028E CAN4RXERR 0x028F CAN4TXERR 0x0290 CAN4IDAR0 0x0291 CAN4IDAR1 0x0292 CAN4IDAR2 0x0293 CAN4IDAR3 0x0294 CAN4IDMR0 0x0295 CAN4IDMR1 0x0296 CAN4IDMR2 0x0297 CAN4IDMR3 0x0298 CAN4IDAR4 0x0299 CAN4IDAR5 0x029A CAN4IDAR6 0x029B CAN4IDAR7 0x029C CAN4IDMR4 0x029D CAN4IDMR5 0x029E CAN4IDMR6 0x029F CAN4IDMR7 0x02A0– 0x02AF CAN4RXFG
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map Address Name 0x02C0 ATD0CTL0 0x02C1 ATD0CTL1 0x02C2 ATD0CTL2 0x02C3 ATD0CTL3 0x02C4 ATD0CTL4 0x02C5 ATD0CTL5 0x02C6 ATD0STAT0 0x02C7 Reserved 0x02C8 ATD0TEST0 0x02C9 ATD0TEST1 0x02CA Reserved 0x02CB ATD0STAT1 0x02CC Reserved 0x02CD ATD0DIEN 0x02CE Reserved 0x02CF ATD0PTAD0 0x02D0 ATD0DR0H 0x02D1 ATD0DR0L 0x02D2 ATD0DR1H 0x02D3 ATD0DR1L 0x02D4 ATD0DR2H
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map (continued) Address Name 0x02D6 ATD0DR3H 0x02D7 ATD0DR3L 0x02D8 ATD0DR4H 0x02D9 ATD0DR4L 0x02DA ATD0DR5H 0x02DB ATD0DR5L 0x02DC ATD0DR6H 0x02DD ATD0DR6L 0x02DE ATD0DR7H 0x02DF ATD0DR7L R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x02F8–0x02FF Reserved Address 0x02F8– 0x02FF Name Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 Name Bit 7 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 P
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name 0x0314 PWMPER0 0x0315 PWMPER1 0x0316 PWMPER2 0x0317 PWMPER3 0x0318 PWMPER4 0x0319 PWMPER5 0x031A PWMPER6 0x031B PWMPER7 0x031C PWMDTY0 0x031D PWMDTY1 0x031E PWMDTY2 0x031F PWMDTY3 0x0320 PWMDTY4 0x0321 PWMDTY5 0x0322 PWMDTY6 0x0323 PWMDTY7 0x0324 PWMSDN 0x0325 Reserved 0x0326 Reserved 0x0327 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0328–0x033F Reserved Address 0x0328– 0x033F Name Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 PFLT3 0 PFLT2 0 PFLMT1 0 PFLT1 0 PFLMT0 0 PFLT0 PCE3 PCE2 PCE1 PCE0 PMUX3 PMUX2 PMUX1 PMUX0 PINTE3 PINTE2 PINTE1 PINTE0 PTF3 PTF2 PTF1 PTF0 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map Address Name 0x0340 PITCFLMT 0x0341 PITFLT 0x0342 PITCE 0x
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R 0x0354 PITLD3 (hi) PLD15 W R 0x0355 PITLD
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0380–0x03BF XGATE Map (Sheet 2 of 3) Address Name 0x038D XGIF 0x038E XGIF 0x038F XGIF 0x0390 XGIF 0x0391 XGIF 0x0392 XGIF 0x0393 XGIF 0x0394 XGIF 0x0395 XGIF 0x0396 XGIF 0x0397 XGIF 0x0398 XGSWT (hi) 0x0399 XGSWT (lo) 0x039A XGSEM (hi) 0x039B XGSEM (lo) 0x039C Reserved 0x039D XGCCR 0x039E XGPC (hi) 0x039F XGPC (lo) 0x03A0 Reserved 0x03A1 Reserved 0x03A2 XGR1 (hi) 0x03A3 XGR1 (lo) R W R W R W R W R W R W R W R W R W
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Chapter 1 Device Overview (MC9S12XDP512V2) 0x0380–0x03BF XGATE Map (Sheet 3 of 3) Address Name 0x03A4 XGR2 (hi) 0x03A5 XGR2 (lo) 0x03A6 XGR3 (hi) 0x03A7 XGR3 (lo) 0x03A8 XGR4 (hi) 0x03A9 XGR4 (lo) 0x03AA XGR5 (hi) 0x03AB XGR5(lo) 0x03AC XGR6 (hi) 0x03AD XGR6 (lo) 0x03AE XGR7 (hi) 0x03AF XGR7 (lo) 0x03B0– 0x03BF Reserved Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XGR2[15:8] XGR2[7:0] XGR3[15:8] XGR3[7:0] XGR4[15:8]
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID number and Mask Set number. Table 1-2. Assigned Part ID Numbers 1 1.
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144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MI
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MC9S12XD-Family 112-Pin LQFP Pins shown in BOLD are not available on the 80-Pin QFP package option 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12XD-Family 80-Pin QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.2 Signal Properties Summary Table 1-3 summarizes the pin functionality. Table 1-3. Signal Properties Summary (Sheet 1 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 Internal Pull Resistor Description CTRL Reset State EXTAL — — — — VDDPLL NA NA XTAL — — — — VDDPLL NA NA RESET — — — — VDDR TEST — — — — N.A.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-3.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-3.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-3.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.5 XFC — PLL Loop Filter Pin Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. VDDPLL VDDPLL CS MCU R0 CP XFC Figure 1-8. PLL Loop Filter Connections 1.2.3.6 BKGD / MODC — Background Debug and Mode Pin The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.11 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0 PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation, this pin is used for external address bus ADDR0 and internal visibility read data IVD0. 1.2.3.12 PC[7:0] / DATA [15:8] — Port C I/O Pins PC[7:0] are general-purpose input or output pins.
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Chapter 1 Device Overview (MC9S12XDP512V2) EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 1-9. Loop Controlled Pierce Oscillator Connections (PE7 = 1) EXTAL C1 MCU RB RS Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 1-10. Full Swing Pierce Oscillator Connections (PE7 = 0) EXTAL CMOS-Compatible External Oscillator MCU XTAL Not Connected Figure 1-11. External Clock Connections (PE7 = 0) 1.2.3.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.16 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5 PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the read enable RE output. This pin is an input with a pull-down device which is only active when RESET is low.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.23 PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6 PH6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as serial clock pin SCK of the serial peripheral interface 2 (SPI2). It can be configured as the receive pin (RXD) of serial communication interface 5 (SCI5). 1.2.3.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 PJ7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the transmit pin TXCAN for the scalable controller area network controller 0 or 4 (CAN0 or CAN4) or as the serial clock pin SCL of the IIC0 module. 1.2.3.
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Chapter 1 Device Overview (MC9S12XDP512V2) maintains the external bus access until the external device is ready to capture data (write) or provide data (read). The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PK7 is configured to reduced levels out of reset in expanded and emulation modes. 1.2.3.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.44 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the serial peripheral interface 0 (SPI0). 1.2.3.45 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 PM2 is a general-purpose input or output pin.
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Chapter 1 Device Overview (MC9S12XDP512V2) be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). 1.2.3.52 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 PP3 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 3 output.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.3.59 PS4 / MISO0 — Port S I/O Pin 4 PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0). 1.2.3.60 PS3 / TXD1 — Port S I/O Pin 3 PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 1 (SCI1). 1.2.3.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 — Power and Ground Pins for I/O Drivers and for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-4. MC9S12XDP512 Power and Ground Connection Summary Pin Number Mnemonic Nominal Voltage 144-Pin LQFP 112-Pin LQFP 80-Pin QFP VDD1, 2 15, 87 13, 65 9, 49 2.5 V VSS1, 2 16, 88 14, 66 10, 50 0V VDDR1 53 41 29 5.0 V VSSR1 52 40 28 0V VDDX1 139 107 77 5.0 V VSSX1 138 106 76 0V VDDX2 26 N.A. N.A. 5.0 V VSSX2 27 N.A. N.A. 0V VDDR2 82 N.A. N.A. 5.0 V VSSR2 81 N.A. N.A. 0V VDDA 107 83 59 5.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. SCI0 . . SCI 5 CAN0 . . CAN4 SPI0 . . SPI2 IIC0 & IIC1 ATD0 & ATD1 Bus Clock PIT EXTAL Oscillator Clock ECT CRG PIM XTAL Core Clock RAM S12X XGATE FLASH EEPROM Figure 1-12.
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Chapter 1 Device Overview (MC9S12XDP512V2) The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the FTX512k4 Block Guide and the EETX4K Block Guide for more details on the operation of the NVM’s. The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-5.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.5 1.5.1 1.5.1.1 Modes of Operation User Modes Normal Expanded Mode Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate. 1.5.1.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.5.2.1 System Stop Modes The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to CRG Block Guide. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes. 1.5.2.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-8.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-8.
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Chapter 1 Device Overview (MC9S12XDP512V2) Table 1-8.
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Chapter 1 Device Overview (MC9S12XDP512V2) 1.7 COP Configuration The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See Table 1-9 and Table 1-10 for coding.
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Chapter 1 Device Overview (MC9S12XDP512V2) Consult the ATD_10B8C Block Guide for information about the analog-to-digital converter module. When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode. 1.9 ATD1 External Trigger Input Connection The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events.
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Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2) 2.1 Introduction This document describes the FTX512K4 module that includes a 512K Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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512 Kbyte Flash Module (S12XFTX512K4V2) • • 2.1.3 Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 2.4.1, “Flash Command Operations” for details). 2.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 2-1. BookTitle, Rev. 2.
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512 Kbyte Flash Module (S12XFTX512K4V2) FTX512K4 Flash Block 0 64K * 16 Bits sector 0 sector 1 Flash Interface Command Interrupt Request sector 127 Command Pipeline cmd2 addr2 data2_0 data2_1 data2_2 data2_3 cmd1 addr1 data1_0 data1_1 data1_2 data1_3 Flash Block 1 64K * 16 Bits sector 0 sector 1 Registers Protection sector 127 Flash Block 2 64K * 16 Bits sector 0 sector 1 Security sector 127 Oscillator Clock Clock Divider FCLK Flash Block 3 64K * 16 Bits sector 0 sector 1 sector 127 Figure 2-
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 2.3.1 Module Memory Map The Flash memory map is shown in Figure 2-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 2.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory from accidental program or erase.
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512 Kbyte Flash Module (S12XFTX512K4V2) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH START = 0x78_0000 Flash Protected/Unprotected Region 480 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF
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512 Kbyte Flash Module (S12XFTX512K4V2) The Flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Table 2-2 while their accessibility is detailed in Section 2.3.2, “Register Descriptions”. Table 2-2.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.
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512 Kbyte Flash Module (S12XFTX512K4V2) Register Name 0x000D RESERVED2 0x000E RESERVED3 0x000F RESERVED4 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W Figure 2-3. FTX512K4 Register Summary (continued) 2.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 R 6 KEYEN 5 4 3 2 RNV5 RNV4 RNV3 RNV2 F F F F 1 0 SEC W Reset F F F F = Unimplemented or Reserved Figure 2-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.2.3 Flash Test Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. Module Base + 0x0002 7 R 6 5 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MRDS W Reset 0 0 0 = Unimplemented or Reserved Figure 2-6. Flash Test Mode Register (FTSTMOD —Normal Mode) Module Base + 0x0002 7 R 6 5 4 0 MRDS 3 2 1 0 0 0 0 0 0 0 0 0 WRALL W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-7.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 W Reset = Unimplemented or Reserved Figure 2-8.
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512 Kbyte Flash Module (S12XFTX512K4V2) Table 2-10. Flash Register Bank Selects 2.3.2.5 BKSEL[1:0] Selected Block 00 Flash Block 0 01 Flash Block 1 10 Flash Block 2 11 Flash Block 3 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. Module Base + 0x0004 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS FPLDIS FPLS W Reset F F F F F F F F = Unimplemented or Reserved Figure 2-10.
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512 Kbyte Flash Module (S12XFTX512K4V2) Table 2-11. FPROT Field Descriptions (continued) Field 5 FPHDIS Description Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled.
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512 Kbyte Flash Module (S12XFTX512K4V2) All possible Flash protection scenarios are shown in Figure 2-11. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required. BookTitle, Rev. 2.
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512 Kbyte Flash Module (S12XFTX512K4V2) FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS=0 FPLDIS=0 7 6 5 4 0x78_0000 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 2 Scenario 1 0 0x78_0000 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 2-11. Flash Protection Scenarios BookTitle, Rev. 2.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 2-15 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions.
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512 Kbyte Flash Module (S12XFTX512K4V2) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 2-16.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. Module Base + 0x0006 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 1 1 0 0 0 = Unimplemented or Reserved Figure 2-14. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 2-17.
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512 Kbyte Flash Module (S12XFTX512K4V2) All bits in the FCTL register are readable but are not writable. The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 2-15. Table 2-19. FCTL Field Descriptions Field Description 7-0 NV[7:0] Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 2.3.2.
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512 Kbyte Flash Module (S12XFTX512K4V2) Module Base + 0x000A 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATAHI W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-18. Flash Data High Register (FDATAHI) Module Base + 0x000B 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATALO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-19. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable.
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512 Kbyte Flash Module (S12XFTX512K4V2) Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-21. RESERVED2 All bits read 0 and are not writable. 2.3.2.13 RESERVED3 This register is reserved for factory testing and is not accessible. Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-22.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4 2.4.1 Functional Description Flash Command Operations Write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider.
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512 Kbyte Flash Module (S12XFTX512K4V2) 182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) yes FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? yes END no yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 2-24.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 2.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers.
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512 Kbyte Flash Module (S12XFTX512K4V2) Table 2-20. Flash Command Description NVM Command Function on Flash Memory 0x06 Data Compress Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. 0x20 Program 0x40 Sector Erase Erase all memory bytes in a sector of the Flash block. 0x41 Mass Erase Erase all memory bytes in the Flash block.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 2-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 2-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address to start compression and number of word addresses to compress 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 2-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address and program Data 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 2-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 2-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored.
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512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 2-31. The sector erase abort command write sequence is as follows: 1.
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512 Kbyte Flash Module (S12XFTX512K4V2) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy Flash Address and Dummy Data 2. Write: FCMD register Sector Erase Abort Cmd 0x47 3.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4.
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512 Kbyte Flash Module (S12XFTX512K4V2) If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 2.3.2.6, “Flash Status Register (FSTAT)”). 2.5 2.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 2.
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512 Kbyte Flash Module (S12XFTX512K4V2) 2.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.
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512 Kbyte Flash Module (S12XFTX512K4V2) unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). 2.6.
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512 Kbyte Flash Module (S12XFTX512K4V2) Table 2-21. Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask Flash Address, Data and Command Buffers empty CBEIF (FSTAT register) CBEIE (FCNFG register) I Bit All Flash commands completed CCIF (FSTAT register) CCIE (FCNFG register) I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 2.8.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.1 Introduction This document describes the module which includes a Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The EEPROM memory is ideal for data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.1.4 Block Diagram A block diagram of the EEPROM module is shown in . 3.2 External Signal Description The EEPROM module contains no signals that connect off-chip. 3.3 Memory Map and Register Definition This section describes the memory map and registers for the EEPROM module. 3.3.1 Module Memory Map The EEPROM memory map is shown in . The HCS12X architecture places the EEPROM memory addresses between global addresses .
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Table 3-2 while their accessibility is detailed in Section 3.3.2, “Register Descriptions”. Table 3-2.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 EDIVLD W Reset 0 = Unimplemented or Reserved Figure 3-2. EEPROM Clock Divider Register (ECLKDIV) All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 3-3. ECLKDIV Field Descriptions Field Description 7 EDIVLD Clock Divider Loaded 0 Register has not been written.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Module Base + 0x0002 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 3-4. RESERVED2 All bits read 0 and are not writable. 3.3.2.4 EEPROM Configuration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. Module Base + 0x0003 7 6 R CBEIE CCIE 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 3-5.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.3.2.5 EEPROM Protection Register (EPROT) The EPROT register defines which EEPROM sectors are protected against program or erase operations. Module Base + 0x0004 7 R 6 5 4 RNV6 RNV5 RNV4 EPOPEN 3 2 1 0 EPDIS EPS2 EPS1 EPS0 F F F F W Reset F F F F = Unimplemented or Reserved Figure 3-6.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 3-6. EEPROM Protection Address Range 3.3.2.6 EPS[2:0] Address Offset Range Protected Size 000 0x0FC0 – 0x0FFF 64 bytes 001 0x0F80 – 0x0FFF 128 bytes 010 0x0F40 – 0x0FFF 192 bytes 011 0x0F00 – 0x0FFF 256 bytes 100 0x0EC0 – 0x0FFF 320 bytes 101 0x0E80 – 0x0FFF 384 bytes 110 0x0E40 – 0x0FFF 448 bytes 111 0x0E00 – 0x0FFF 512 bytes EEPROM Status Register (ESTAT) The ESTAT register defines the operational status of the module.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 3-7. ESTAT Field Descriptions Field Description 7 CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.3.2.7 EEPROM Command Register (ECMD) The ECMD register is the EEPROM command register. Module Base + 0x0006 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 3-9. EEPROM Command Register (ECMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 3-8.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) All bits read 0 and are not writable. EEPROM Address Registers (EADDR) The EADDRHI and EADDRLO registers are the EEPROM address registers. Module Base + 0x0009 7 6 5 4 R 3 2 1 0 0 0 0 0 EABLO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 3-11. EEPROM Address Low Register (EADDRLO) All EABHI and EABLO bits read 0 and are not writable in normal modes. All EABHI and EABLO bits are readable and writable in special modes.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4 3.4.1 Functional Description EEPROM Command Operations Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the EEPROM memory with EECLK < 150 kHz should be avoided.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8 = 0 (reset) oscillator_clock >12.8 MHz? no yes PRDIV8 = 1 PRDCLK = oscillator_clock/8 PRDCLK = oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1 TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0]) 1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 3.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 3-10. EEPROM Command Description ECMDB Command Function on EEPROM Memory 0x41 Mass Erase Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. 0x47 Sector Erase Abort Abort the sector erase operation. The sector erase operation will terminate according to a set procedure.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 3-15. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Erase Verify Command 0x05 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 3-16. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check 1. Write: EEPROM Address and program Data 2. Write: ECMD register Program Command 0x20 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 3-17. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Sector Address and Dummy Data 2. Write: ECMD register Sector Erase Command 0x40 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 3-18. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the ECMD register.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Mass Erase Command 0x41 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 3-19. The sector erase abort command write sequence is as follows: 1.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Execute Sector Erase/Modify Command Flow Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy EEPROM Address and Dummy Data NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 2. Write: ECMD register Sector Erase Abort Cmd 0x47 NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 3-20. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Word Address and program Data 2. Write: ECMD register Sector Modify Command 0x60 3.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.4.3 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.5 3.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 3.8, “Interrupts”). 3.5.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory.
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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.8.1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 3-21. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 3-21. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 3.3.2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.1 Introduction The S12XD family port integration module (below referred to as PIM) establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Port D DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Port AD1 Port AD0 Port T Port P SCK SS MOSI MISO SS SPI1 SCK MOSI MISO SPI2 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 SS SPI0 SCK MOSI MISO TXD SCI1 RXD TXD SCI0 RXD BKGD/MODC ECLKX2/XCLKS TAGHI/MODB TAGLO/RE/MODA ECLK S12X_EBI LDS/LSTRB S12X_BDM WE/R/W S12X_DBG IRQ XIRQ S12X_INT EWAIT/ROMCTL NOACC/ADDR22 ADDR21 ADRR20 A
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.2 External Signal Description This section lists and describes the signals that do connect off-chip. 4.2.1 Signal Properties Table 4-1 shows all the pins and their functions that are controlled by the MC9S12XDP512. Refer to Section 4.4, “Functional Description” for the availability of the individual pins in the different package options.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-1.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3 Memory Map and Register Definition This section provides a detailed description of all MC9S12XDP512 registers. 4.3.1 Module Memory Map Table 4-2 shows the register map of the port integration module. Table 4-2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2 Register Descriptions Table 4-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. Table 4-3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name 0x0000 PORTA 0x0001 PORTB 0x0002 DDRA 0x0003 DDRB 0x0004 PORTC R W R W R W R W R W 0x0005 PORTD W 0x0006 DDRC W 0x0007 DDRD R R R W 0x0008 PORTE R W 0x0009 DDRE W R Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name Bit 7 6 5 0x000E– R 0x001B W Non-PIM Address Range 0x001C R ECLKCTL W 0x001D R Reserved W 0x001E IRQCR R W 0x001F R Reserved W 0x0033 DDRK R W R W NECLK NCLKX2 W 0x0241 PTIT W 0x0242 DDRT 0x0243 RDRT R R R W R W 2 1 Bit 0 EDIV1 EDIV0 0 0 IRQE IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Non-PIM Address Range PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0x0246 R Reserved W 0 0 0 0 0 0 0 0 0x0247 R Reserved W 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RD
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM R W R W R W R W 0x0257 MODRR W 0x0258 PTP W 0x0259 PTIP R R R W 0x025B RDRP W 0x025D PPSP 0x025E PIEP 0x025F PIFP 0x0260 PTH 0x0261 PTIH 6 5 4 3 2 1 Bit 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name 0x0262 DDRH W 0x0263 RDRH W 0x0264 PERH R R R W 0x0265 PPSH W 0x0266 PIEH W 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ R R R W R W R R W R W W 0x026D PPSJ W 0x026F PIFJ 6 5 4 3 2 1 Bit 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Register Name 0x0271 PT1AD0 R W 0x0272 R Reserved W 0x0273 Name R W 0x0274 R Reserved W Bit 7 6 5 4 3 2 1 Bit 0 PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 0 0 0 0 0 0 0 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 0x0275 R RDR1AD0 W RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0x0276 R Reserved W 0 0 0 0 0 0 0 0 PER1AD0
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.1 Port A Data Register (PORTA) 0x0000 (PRR) 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADDR15 mux IVD15 ADDR14 mux IVD14 ADDR13 mux IVD13 ADDR12 mux IVD12 ADDR11 mux IVD11 ADDR10 mux IVD10 ADDR9 mux IVD9 ADDR8 mux IVD8 0 0 0 0 0 0 0 0 R W Alt. Function Reset Figure 4-3. Port A Data Register (PORTA) Read: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 4-5. PORTB Field Descriptions Field Description 7–0 PB[7:0] Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data Select (UDS) in normal expanded mode.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.3 Port A Data Direction Register (DDRA) 0x0002 (PRR) 7 6 5 4 3 2 1 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 R W Reset Figure 4-5. Port A Data Direction Register (DDRA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-7. DDRB Field Descriptions Field Description 7–0 DDRB[7:0] Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.5 Port C Data Register (PORTC) 0x0004 (PRR) 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Exp.: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Reset 0 0 0 0 0 0 0 0 R W Figure 4-7. Port C Data Register (PORTC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.7 Port C Data Direction Register (DDRC) 0x0006 (PRR) 7 6 5 4 3 2 1 0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 R W Reset Figure 4-9. Port C Data Direction Register (DDRC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-11. DDRD Field Descriptions Field Description 7–0 DDRD[7:0] Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.9 Port E Data Register (PORTE) 0x0008 (PRR) 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Alt. Func. XCLKS or ECLKX2 MODB or TAGHI MODA or RE or TAGLO ECLK EROMCTL or LSTRB or LDS R/W or WE IRQ XIRQ Reset 0 0 0 0 0 0 —1 —1 R W = Unimplemented or Reserved Figure 4-11. Port E Data Register (PORTE) 1 These registers are reset to zero.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.10 Port E Data Direction Register (DDRE) 0x0009 (PRR) 7 6 5 4 3 2 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-12. Port E Data Direction Register (DDRE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 0x000C (PRR) 7 6 PUPKE BKPUE 1 1 5 R 4 3 2 1 0 PUPEE PUPDE PUPCE PUPBE PUPAE 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.12 S12X_EBI Ports Reduced Drive Register (RDRIV) 0x000D (PRR) 7 R 6 5 0 0 RDPK 4 3 2 1 0 RDPE RDPD RDPC RDPB RDPA 0 0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 4-14. S12X_EBI Ports Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-16. ECLKCTL Field Descriptions (continued) Field Description 6 NCLKX2 No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-18. IRQCR Field Descriptions Field 7 IRQE 6 IRQEN Description IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once. 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.15 Port K Data Register (PORTK) 0x0032 (PRR) 7 6 5 4 3 2 1 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Alt. Func. ROMCTL or EWAIT ADDR22 mux NOACC ADDR21 ADDR20 ADDR19 mux IQSTAT3 ADDR18 mux IQSTAT2 ADDR17 mux IQSTAT1 ADDR16 mux IQSTAT0 Reset 0 0 0 0 0 0 0 0 R W Figure 4-17. Port K Data Register (PORTK) Read: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-20. DDRK Field Descriptions Field Description 7–0 DDRK[7:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTK after changing the DDRK register. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.17 Port T Data Register (PTT) 0x0240 7 6 5 4 3 2 1 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R W ECT Reset Figure 4-19. Port T Data Register (PTT) Read: Anytime. Write: Anytime. Table 4-21. PTT Field Descriptions Field Description 7–0 PTT[7:0] Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section).
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.19 Port T Data Direction Register (DDRT) 0x0242 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 4-21. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.20 Port T Reduced Drive Register (RDRT) 0x0243 7 6 5 4 3 2 1 0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 4-22. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-24. RDRT Field Descriptions Field 7–0 RDRT[7:0] 4.3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.22 Port T Polarity Select Register (PPST) 0x0245 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 R W Reset Figure 4-24. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 4-26.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.24 Port S Input Register (PTIS) 0x0249 R 7 6 5 4 3 2 1 0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 4-26. Port S Input Register (PTIS) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.25 Port S Data Direction Register (DDRS) 0x024A 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 4-27. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.26 Port S Reduced Drive Register (RDRS) 0x024B 7 6 5 4 3 2 1 0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 4-28. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-28. RDRS Field Descriptions Field 7–0 RDRS[7:0] 4.3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.28 Port S Polarity Select Register (PPSS) 0x024D 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 R W Reset Figure 4-30. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 4-30.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.30 Port M Data Register (PTM) 0x0250 7 6 5 4 3 2 1 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 TXCAN3 RXCAN3 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN4 RXCAN4 SCK0 MOSI0 SS0 MISO0 0 0 0 0 0 0 R W CAN Routed CAN0 Routed CAN4 TXCAN4 RXCAN4 Routed SPIO Reset 0 0 Figure 4-32. Port M Data Register (PTM) Read: Anytime. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-32. PTM Field Descriptions (continued) Field Description 3–2 PTM[3:2] The CAN1 function (TXCAN1 and RXCAN1) takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.31 Port M Input Register (PTIM) 0x0251 R 7 6 5 4 3 2 1 0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 4-33. Port M Input Register (PTIM) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.32 Port M Data Direction Register (DDRM) 0x0252 7 6 5 4 3 2 1 0 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 4-34. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output (TXCAN[3:0], TXD3).
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.33 Port M Reduced Drive Register (RDRM) 0x0253 7 6 5 4 3 2 1 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 4-35. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-34. RDRM Field Descriptions Field 7–0 RDRM[7:0] 4.3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.35 Port M Polarity Select Register (PPSM) 0x0255 7 6 5 4 3 2 1 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 0 0 R W Reset Figure 4-37. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN[3:0] inputs, but not a pull-down. Table 4-36.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-37. WOMM Field Descriptions Field Description 7–0 Wired-OR Mode Port M WOMM[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.37 Module Routing Register (MODRR) 0x0257 7 R 6 5 4 3 2 1 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-39. Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 4-38.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.38 Port P Data Register (PTP) 0x0258 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SPI SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Reset Figure 4-40. Port P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.39 Port P Input Register (PTIP) 0x0259 R 7 6 5 4 3 2 1 0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 4-41. Port P Input Register (PTIP) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.40 Port P Data Direction Register (DDRP) 0x025A 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 4-42. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.41 Port P Reduced Drive Register (RDRP) 0x025B 7 6 5 4 3 2 1 0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 4-43. Port P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-40. RDRP Field Descriptions Field 7–0 RDRP[7:0] 4.3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.43 Port P Polarity Select Register (PPSP) 0x025D 7 6 5 4 3 2 1 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 R W Reset Figure 4-45. Port P Polarity Select Register (PPSP) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 4-42.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-43. PIEP Field Descriptions Field 7–0 PIEP[7:0] Description Interrupt Enable Port P 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.45 Port P Interrupt Flag Register (PIFP) 0x025F 7 6 5 4 3 2 1 0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 R W Reset Figure 4-47. Port P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.46 Port H Data Register (PTH) 0x0260 7 6 5 4 3 2 1 0 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 SS2 SCK2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Routed SPI Reset Figure 4-48. Port H Data Register (PTH) Read: Anytime. Write: Anytime. Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.47 Port H Input Register (PTIH) 0x0261 R 7 6 5 4 3 2 1 0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 4-49. Port H Input Register (PTIH) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.48 Port H Data Direction Register (DDRH) 0x0262 7 6 5 4 3 2 1 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 4-50. Port H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output. If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.49 Port H Reduced Drive Register (RDRH) 0x0263 7 6 5 4 3 2 1 0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 4-51. Port H Reduced Drive Register (RDRH) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port H output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-46. RDRH Field Descriptions Field 7–0 RDRH[7:0] 4.3.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.51 Port H Polarity Select Register (PPSH) 0x0265 7 6 5 4 3 2 1 0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 0 0 0 0 0 0 0 0 R W Reset Figure 4-53. Port H Polarity Select Register (PPSH) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 4-48.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-49. PIEH Field Descriptions Field 7–0 PIEH[7:0] Description Interrupt Enable Port H 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.53 Port H Interrupt Flag Register (PIFH) 0x0267 7 6 5 4 3 2 1 0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 0 0 0 0 0 0 0 0 R W Reset Figure 4-55. Port H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.54 Port J Data Register (PTJ) 0x0268 7 6 5 4 PTJ7 PTJ6 PTJ5 PTJ4 TXCAN4 RXCAN4 SCL0 SDA0 R 3 2 1 0 PTJ2 PTJ1 PTJ0 TXD2 RXD2 0 W CAN4/ SCI2 IICO IIC1 Routed CAN0 TXCAN0 0 SDA1 CS2 CS0 0 0 RXCAN0 Alt. Function Reset SCL1 0 CS1 0 0 CS3 0 0 = Unimplemented or Reserved Figure 4-56. Port J Data Register (PTJ) Read: Anytime. Write: Anytime.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-51. PTJ Field Descriptions (continued) Field Description 1 PJ1 The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer to SCI section for details. 0 PJ0 The SCI2 function takes precedence over the chip select (CS3) and the general purpose I/O function if the SCI2 module is enabled. The chip select (CS3) takes precedence over the general purpose I/O function.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.55 Port J Input Register (PTIJ) 0x0269 R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 0 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset1 = Unimplemented or Reserved Figure 4-57. Port J Input Register (PTIJ) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.56 Port J Data Direction Register (DDRJ) 0x026A 7 6 5 4 3 DDRJ7 DDRJ6 DDRJ5 DDRJ4 0 0 0 0 R 2 1 0 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-58. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4).
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.57 Port J Reduced Drive Register (RDRJ) 0x026B 7 6 5 4 3 RDRJ7 RDRJ6 RDRJ5 RDRJ4 0 0 0 0 R 2 1 0 RDRJ2 RDRJ1 RDRJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-59. Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-53.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-54. PERJ Field Descriptions Field 7–0 PERJ[7:4] PERJ[2:0] Description Pull Device Enable Port J 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.59 Port J Polarity Select Register (PPSJ) 0x026D 7 6 5 4 3 PPSJ7 PPSJ6 PPSJ5 PPSJ4 0 0 0 0 R 2 1 0 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-61. Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 4-55.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-56. PIEJ Field Descriptions Field 7–0 PIEJ[7:4] PIEJ[2:0] Description Interrupt Enable Port J 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.61 Port J Interrupt Flag Register (PIFJ) 0x026F 7 6 5 4 PIFJ7 PIFJ6 PIFJ5 PIFJ4 0 0 0 0 3 R 2 1 0 PIFJ2 PIFJ1 PIFJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-63. Port J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0) 0x0273 7 6 5 4 3 2 1 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 4-65. Port AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output. Table 4-58.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0) 0x0275 7 6 5 4 3 2 1 0 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 4-66. Port AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the port is used as input this bit is ignored. Table 4-59.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.66 Port AD1 Data Register 0 (PT0AD1) 0x0278 7 6 5 4 3 2 1 0 PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 0 0 0 0 0 0 0 0 R W Reset Figure 4-68. Port AD1 Data Register 0 (PT0AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1) 0x027A 7 6 5 4 3 2 1 0 R DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 4-70. Port AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output. Table 4-61.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1) 0x027B 7 6 5 4 3 2 1 0 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 W Reset 0 0 0 0 0 0 0 0 Figure 4-71. Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output. Table 4-62.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1) 0x027C 7 6 5 4 3 2 1 0 R RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 4-72. Port AD1 Reduced Drive Register 0 (RDR0AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 4-63.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.3.2.72 Port AD1 Pull Up Enable Register 0 (PER0AD1) 0x027E 7 6 5 4 3 2 1 0 R PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 4-74. Port AD1 Pull Up Enable Register 0 (PER0AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input. This bit has no effect if the port is used as output.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4 Functional Description Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output from the external bus interface module or a peripheral module or an input to the external bus interface module or a peripheral module. A set of configuration registers is common to all ports with exceptions in the expanded bus interface and ATD ports (Table 4-67).
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.1.2 Input Register This is a read-only register and always returns the buffered state of the pin (Figure 4-76). 4.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 4-76). PTI 0 1 PT 0 PIN 1 DDR 0 1 data out Module output enable module enable Figure 4-76.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.1.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 4.4.1.9 Interrupt Flag Register If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 4.4.1.10 Module Routing Register This register supports the re-routing of the CAN0, CAN4, SPI0, SPI1, and SPI2 pins to alternative ports.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.2.3 Port C and D Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port C and port D are associated with the external data bus inputs/outputs DATA15–DATA8 and DATA7–DATA0, respectively. These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI section).
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.2.6 Port T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer. 4.4.2.7 Port S This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for generalpurpose I/O, or with the SCI and SPI subsystems. The SPI0 pins can be re-routed. Refer to Section 4.3.2.37, “Module Routing Register (MODRR)”.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.2.10 Port H This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1 and SPI2 modules. Refer to Section 4.3.2.37, “Module Routing Register (MODRR)”. Port H offers 8 I/O pins with edge triggered interrupt capability (Section 4.4.3, “Pin Interrupts”). NOTE Port H is not available in 80-pin packages. 4.4.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.4.3 Pin Interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is generated by an RC-oscillator in the port integration module.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) Table 4-70.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) • Power consumption will increase the more the voltages on general purpose input pins deviate from the supply voltages towards mid-range because the digital input buffers operate in the linear region. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.1 Introduction This specification describes the function of the clocks and reset generator (MC9S12XDP512). 5.1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. • Wait mode In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL register.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.1.3 Block Diagram Figure 5-1 shows a block diagram of the MC9S12XDP512.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.2 External Signal Description This section lists and describes the signals that connect off chip. 5.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL and VSSPLL must be connected to properly. 5.2.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.1 Module Memory Map Table 5-1 gives an overview on all MC9S12XDP512 registers. Table 5-1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2 Register Descriptions This section describes in address order all the MC9S12XDP512 registers and their individual bits.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (fSCM).
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Chapter 5 Clocks and Reset Generator (S12CRGV6) NOTE Write to this register initializes the lock detector bit and the track detector bit. 5.3.2.3 Reserved Register (CTFLG) This register is reserved for factory testing of the MC9S12XDP512 module and is not available in normal modes. Module Base +0x_02 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 5-6.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-2. CRGFLG Field Descriptions Field Description 7 RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. 6 PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. Module Base +0x_04 R W Reset 7 6 RTIE ILAF 0 1 5 0 0 4 LOCKIE 0 3 2 0 0 0 0 1 SCMIE 0 0 0 0 1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 5-8. CRG Interrupt Enable Register (CRGINT) Read: Anytime Write: Anytime Table 5-3.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 5-17 for more details on the effect of each bit. Module Base +0x_05 R W Reset 7 6 PLLSEL PSTP 0 0 5 4 0 0 0 0 3 PLLWAI 0 2 0 1 0 RTIWAI COPWAI 0 0 0 = Unimplemented or Reserved Figure 5-9. CRG Clock Select Register (CLKSEL) Read: Anytime Write: Refer to each bit for individual write conditions Table 5-4.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.7 CRG PLL Control Register (PLLCTL) This register controls the PLL functionality. Module Base +0x_06 R W Reset 7 6 5 4 3 2 1 0 CME PLLON AUTO ACQ FSTWKP PRE PCE SCME 1 1 1 1 0 0 0 1 Figure 5-10. CRG PLL Control Register (PLLCTL) Read: Anytime Write: Refer to each bit for individual write conditions Table 5-5. PLLCTL Field Descriptions Field Description 7 CME Clock Monitor Enable Bit — CME enables the clock monitor.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-5. PLLCTL Field Descriptions (continued) Field Description 2 PRE RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime. 0 RTI stops running during pseudo stop mode. 1 RTI continues running during pseudo stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-7.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-8.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. Module Base +0x_08 R W 7 6 WCOP RSBCK Reset1 0 5 4 3 0 0 0 0 0 WRTMASK 0 2 1 0 CR2 CR1 CR0 1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0. = Unimplemented or Reserved Figure 5-12. CRG COP Control Register (COPCTL) Read: Anytime Write: 1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-9. COPCTL Field Descriptions (continued) Field Description 5 WRTMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR[2:0]. 0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL 1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. Module Base +0x_09 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 5-13.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base +0x_0B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 5-15. ARMCOP Register Diagram Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.4 Functional Description 5.4.1 Functional Blocks 5.4.1.1 Phase Locked Loop (PLL) The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.4.1.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 5-16.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): • The TRACK bit is a read-only indicator of the mode of the filter. • The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt. • The LOCK bit is a read-only indicator of the locked state of the PLL.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) The clock generator creates the clocks used in the MCU (see Figure 5-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self clock mode (see Section 5.4.2.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 5-19 as an example. check window 1 3 2 50000 49999 VCO Clock 1 2 3 4 5 4096 OSCCLK 4095 osc ok Figure 5-19. Check Window Example The sequence for clock quality check is shown in Figure 5-20.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) NOTE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo stop mode or wait mode. 5.4.1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.4.2.2 Self Clock Mode The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO running at minimum operating frequency; this mode of operation is called self clock mode. This requires CME = 1 and SCME = 1.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) CPU Req’s Wait Mode. PLLWAI=1 ? No Yes Clear PLLSEL, Disable PLL No Enter Wait Mode CME=1 ? Wait Mode left due to external reset No Yes Exit Wait w. ext.RESET CM Fail ? INT ? Yes No Yes Exit Wait w. CMRESET No SCME=1 ? Yes SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait) No Exit Wait Mode Yes Exit Wait Mode SCM=1 ? No Yes Enter SCM Enter SCM Continue w. Normal OP Figure 5-21.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) There are four different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Any interrupt If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-12. Outcome of Clock Loss in Wait Mode CME SCME SCMIE 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET Stop Mode left due to external reset No INT ? Yes No Enter Stop Mode PSTP=1 ? Yes CME=1 ? No Yes SCME=1 & FSTWKP=1 ? No INT ? Yes Yes CM fail ? No No Yes No Exit Stop w. CMRESET No SCME=1 ? Yes Clock OK ? Exit Stop w.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.4.3.3.1 Wake-up from Pseudo Stop Mode (PSTP=1) Wake-up from pseudo stop mode is the same as wake-up from wait mode.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-13. Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 0 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.4.3.3.2 Wake-up from Full Stop (PSTP = 0) The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 5.4.1.4, “Clock Quality Checker”).
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Chapter 5 Clocks and Reset Generator (S12CRGV6) CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service STOP IRQ Service IRQ Service STOP Interrupt Interrupt Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 5-23. Fast Wake-up from Full Stop Mode: Example 1 . CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service FSTWKP=0 SCMIE=1 Freq.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.5 Resets This section describes how to reset the MC9S12XDP512, and how the MC9S12XDP512 itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 5.3, “Memory Map and Register Definition”.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Table 5-15.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.5.2 Clock Monitor Reset The MC9S12XDP512 generates a clock monitor reset in case all of the following conditions are true: • Clock monitor is enabled (CME = 1) • Loss of clock is detected • Self-clock mode is disabled (SCME = 0). The reset event asynchronously forces the configuration registers to their default settings (see Section 5.3, “Memory Map and Register Definition”).
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Chapter 5 Clocks and Reset Generator (S12CRGV6) Clock Quality Check (no Self-Clock Mode) RESET )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 5-26. RESET Pin Tied to VDD (by a pull-up resistor) Clock Quality Check (no Self Clock Mode) )( RESET Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 5-27. RESET Pin Held Low Externally 5.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 5-16.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.6.2 PLL Lock Interrupt The MC9S12XDP512 generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. 5.6.
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Chapter 5 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) 6.1 Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (2.5 V nominal) and require the minimum number of external components. It is designed for optimal start-up margin with typical crystal oscillators. 6.1.1 Features The XOSC will contain circuitry to dynamically control current gain in the output amplitude.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) 6.1.3 Block Diagram Figure 6-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Detector Gain Control VDDPLL = 2.5 V Rf XTAL EXTAL Figure 6-1. XOSC Block Diagram 6.2 External Signal Description This section lists and describes the signals that connect off chip 6.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 6-2.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) 6.2.3 XCLKS — Input Signal The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS pin. Table 6-1 lists the state coding of the sampled XCLKS signal. . Table 6-1. Clock Selection Based on XCLKS XCLKS 6.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) 6.4.3 Wait Mode Operation During wait mode, XOSC is not impacted. 6.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.1 Introduction The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy. 7.1.1 • • • • • • • • • • • • • • 7.1.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Bus Clock ATD clock Clock Prescaler Trigger Mux ETRIG0 ETRIG1 ETRIG2 ATD10B16C Sequence Complete Mode and Timing Control Interrupt ETRIG3 (see Device Overview chapter for availability and connectivity) ATDCTL1 ATDDIEN Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 PORTAD VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN15 AN14 AN13 AN12 AN11 + AN10 Sample &
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.2 External Signal Description This section lists all inputs to the ATD10B16C block. 7.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion. 7.2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) . Table 7-1.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Register Name 0x000D ATDDIEN1 R W 0x000E PORTAD0 W R 0x000F PORTAD1 R Bit 7 6 5 4 3 2 1 Bit 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W R BIT 9 MSB BIT 7 MSB 0x0010–0x002F W ATDDRxH– ATDD
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-3. Multi-Channel Wrap Around Coding 7.3.2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-5. External Trigger Channel Select Coding 1 7.3.2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Module Base + 0x0002 7 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 R 0 ASCIF W Reset 0 = Unimplemented or Reserved Figure 7-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 7-6. ATDCTL2 Field Descriptions Field Description 7 ADPU ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-6. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 7.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0003 7 R 6 5 4 3 2 1 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 1 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 7-6.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-9. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 7-10.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0004 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0 0 0 0 0 1 0 1 R W Reset Figure 7-7.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-13. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-14. ATDCTL5 Field Descriptions (continued) Field Description 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 7-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R 6 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 7-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on CC[3:0]) Table 7-18.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.8 Reserved Register 0 (ATDTEST0) Module Base + 0x0008 R 7 6 5 4 3 2 1 0 u u u u u u u u 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved u = Unaffected Figure 7-10. Reserved Register 0 (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 7.3.2.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-20. Special Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 X X Reserved 1 0 1 0 0 VRH 1 0 1 0 1 VRL 1 0 1 1 0 (VRH+VRL) / 2 1 0 1 1 1 Reserved 1 1 X X X Reserved 7.3.2.10 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 Module Base + 0x000B R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-13. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 7-22.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) Module Base + 0x000C 7 6 5 4 3 2 1 0 IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 0 0 0 0 0 0 0 0 R W Reset Figure 7-14. ATD Input Enable Register 0 (ATDDIEN0) Read: Anytime Write: anytime Table 7-23.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.14 Port Data Register 0 (PORTAD0) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. Module Base + 0x000E R 7 6 5 4 3 2 1 0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 1 1 1 1 1 1 1 1 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 W Reset Pin Function = Unimplemented or Reserved Figure 7-16.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.15 Port Data Register 1 (PORTAD1) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. Module Base + 0x000F R 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 1 1 1 1 1 1 1 AN 7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 W Reset Pin Function = Unimplemented or Reserved Figure 7-17.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.3.2.16.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. 7.4.1.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Table 7-27. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Falling edge triggered. Performs one conversion sequence per trigger. 0 1 1 X Rising edge triggered. Performs one conversion sequence per trigger. 1 0 1 X Trigger active low.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) • Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AWAIT bit. Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. NOTE The reset value for the ADPU bit is zero.
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.1 Introduction The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 8.1.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.1.2.2 • • • 8.1.3 MCU Operating Modes Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Bus Clock ETRIG0 ETRIG1 ETRIG2 Clock Prescaler ATD clock Trigger Mux ATD10B8C Sequence Complete Mode and Timing Control Interrupt ETRIG3 (See Device Overview chapter for availability and connectivity) ATDDIEN ATDCTL1 PORTAD Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN7 AN6 + AN5 Sample & Hold AN4 1 1 AN3 Analog AN2 – Comparator MUX AN1 AN0 Figure 8-1.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ATD. 8.3.1 Module Memory Map Figure 8-2 gives an overview of all ATD registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 8.3.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Register Name 0x000A Unimplemente d R W 0x000B ATDSTAT1 R W 0x000C Unimplemente d R W 0x000D ATDDIEN R W 0x000E Unimplemente d R W 0x000F PORTAD R W Bit 7 6 5 4 3 2 1 Bit 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 Left Justified Result Data Note: The read portion of the left justified result data registers has been divided to s
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0016 ATDDR3H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 0x0017 ATDDR3L 10-BIT 8-BIT W BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 0x0018 ATDDR4H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 0x0019 ATDDR4L 10-BIT 8-BIT W BIT 0 U 0 0 0 0 0 0
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Register Name Bit 7 0x0011 ATDDR0L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x0012 ATDDR1H 10-BIT 8-BIT W 0x0013 ATDDR1L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x0014 ATDDR2H 10-BIT 8-BIT W 0x0015 ATDDR2L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x0016 ATDDR3H 10-BIT 8-BIT W 0x0017 ATDDR3L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x0018 ATDDR4H 10-BIT 8-BIT W 0x0019 ATDDR4L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x001A ATDD45H 10-BIT 8-BIT W 0x001B ATDD45L 10-BIT BIT 7 8-BIT BIT
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Register Name Bit 7 6 5 4 3 2 1 Bit 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0x001D ATDDR6L 10-BIT BIT 7 8-BIT BIT 7 MSB W 0x001E ATDD47H 10-BIT 8-BIT W 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 0x001F ATDD47L 10-BIT BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 8-BIT = Unimplemented or Reserved Figure 8-2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-2. Multi-Channel Wrap Around Coding WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting 1 1 0 AN6 1 1 1 AN7 MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0001 7 R W ETRIGSEL Reset 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 ETRIGCH2 ETRIGCH1 ETRIGCH0 1 1 1 = Unimplemented or Reserved Figure 8-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 8-3.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0002 7 R W Reset 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 0 ASCIF 0 = Unimplemented or Reserved Figure 8-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 8-5.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-5. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 8.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-7. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0004 R W Reset 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0 0 0 0 0 1 0 1 Figure 8-7.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-12. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. Module Base + 0x0005 7 R W Reset 6 5 4 DJM DSGN SCAN MULT 0 0 0 0 3 0 0 2 1 0 CC CB CA 0 0 0 = Unimplemented or Reserved Figure 8-8.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-14. Available Result Data Formats SRES8 DJM DSGN Result Data Formats Description and Bus Bit Mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 X 0 1 X 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed — bits 8–15 8-bit / right justified / unsigned — bits 0–7 10-bit / left justified / unsigned — bits 6–15 10-bit / left justified / signed — bits 6–15 10-bit / right justified / unsigned — bits 0–9 Table 8-15.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R W Reset SCF 0 6 0 0 5 4 ETORF FIFOR 0 0 3 2 1 0 0 CC2 CC1 CC0 0 0 0 0 = Unimplemented or Reserved Figure 8-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC2, CC1, CC0)) Table 8-17.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.8 Reserved Register (ATDTEST0) Module Base + 0x0008 R 7 6 5 4 3 2 1 0 U U U U U U U U 1 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-10. Reserved Register (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 8.3.2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-19. Special Channel Select Coding 8.3.2.10 SC CC CB CA Analog Input Channel 1 0 X X Reserved 1 1 0 0 VRH 1 1 0 1 VRL 1 1 1 0 (VRH+VRL) / 2 1 1 1 1 Reserved ATD Status Register 1 (ATDSTAT1) This read-only register contains the conversion complete flags.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.11 ATD Input Enable Register (ATDDIEN) Module Base + 0x000D R W Reset 7 6 5 4 3 2 1 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 0 0 0 0 0 0 0 0 Figure 8-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 8-21.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-22. PORTAD Field Descriptions Field Description 7–0 PTAD[7:0] A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value).
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.3.2.13.2 Right Justified Result Data Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 0 0 0 0 0 0 0 10-bit data 8-bit data W Reset 0 = Unimplemented or Reserved Figure 8-17.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine. 8.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 8.4.1.4 Analog-to-Digital (A/D) Machine The A/D Machine performs analog to digital conversions.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Table 8-23. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Falling edge triggered. Performs one conversion sequence per trigger. 0 1 1 X Rising edge triggered. Performs one conversion sequence per trigger. 1 0 1 X Trigger active low.
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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.4.2.3 Low Power Modes The ATD can be configured for lower MCU power consumption in 3 different ways: 1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 3.
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Chapter 9 XGATE (S12XGATEV2) 9.1 Introduction The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 9-1 gives an overview on the XGATE architecture.
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Chapter 9 XGATE (S12XGATEV2) 9.1.2 Modes of Operation There are four run modes on S12X devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active) In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 9.3.2.1, “XGATE Control Register (XGMCTL)”). 9.1.
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Chapter 9 XGATE (S12XGATEV2) 9.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Table 9-1.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved registers have no effect.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 9 XGATE (S12XGATEV2) Register Name 0x0010 XGIF 63 W 59 58 57 56 55 54 53 52 51 50 49 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 R W XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 15 0x0016 XG
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Chapter 9 XGATE (S12XGATEV2) Register Name 15 0x0026 XGR3 W 0x0028 XGR4 W 0x002A XGR5 14 13 12 11 10 R W 6 5 4 3 2 1 0 XGR5 W 0x002E XGR7 7 XGR4 R W 8 XGR3 R 0x002C XGR6 9 R XGR6 R XGR7 = Unimplemented or Reserved Figure 9-2. XGATE Register Summary (Sheet 3 of 3) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.1 XGATE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 9-3. Module Base +0x00000 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 XG SSM XG FACTM 0 0 R W XGEM Reset 0 XG XG FRZM DBGM 0 0 7 0 0 5 4 3 2 0 XG XGIEM SWEIFM 0 6 XGE XGFRZ XGDBG XGSS XGFACT 0 0 0 0 0 0 1 0 XG SWEIF XGIE 0 0 = Unimplemented or Reserved Figure 9-3.
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Chapter 9 XGATE (S12XGATEV2) Table 9-2. XGMCTL Field Descriptions (Sheet 2 of 3) Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0".
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Chapter 9 XGATE (S12XGATEV2) Table 9-2. XGMCTL Field Descriptions (Sheet 3 of 3) Field Description 4 XGSS XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.2 XGATE Channel ID Register (XGCHID) The XGATE channel ID register (Figure 9-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads (see Section 9.6.1, “Debug Features”). Module Base +0x0002 7 R 6 5 4 3 0 2 1 0 0 0 0 XGCHID[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 9-4.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.4 XGATE Channel Interrupt Flag Vector (XGIF) The interrupt flag vector (Figure 9-6) provides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location.
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Chapter 9 XGATE (S12XGATEV2) Write: Anytime Table 9-5. XGIV Field Descriptions Field Description 127–9 XGIF[78:9] Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core. Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Refer to Section “Interrupts” of the SoC Guide for a list of implemented Interrupts.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.5 XGATE Software Trigger Register (XGSWT) The eight software triggers of the XGATE module can be set and cleared through the XGATE software trigger register (Figure 9-7). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.6 XGATE Semaphore Register (XGSEM) The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register (Figure 9-8). Refer to section Section 9.4.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.7 XGATE Condition Code Register (XGCCR) The XGCCR register (Figure 9-9) provides access to the RISC core’s condition code register. Module Base +0x001D R 7 6 5 4 0 0 0 0 0 0 0 W Reset 0 3 2 1 0 XGN XGZ XGV XGC 0 0 0 0 = Unimplemented or Reserved Figure 9-9. XGATE Condition Code Register (XGCCR) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 9-8.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.8 XGATE Program Counter Register (XGPC) The XGPC register (Figure 9-10) provides access to the RISC core’s program counter. Module Base +0x0001E 15 14 13 12 11 10 9 8 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGPC W Reset 0 0 0 0 0 0 0 0 Figure 9-10. XGATE Program Counter Register (XGPC) Figure 9-11. Read: In debug mode if unsecured Write: In debug mode if unsecured Table 9-9. XGPC Field Descriptions Field 15–0 XGPC[15:0] 9.3.2.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.10 XGATE Register 2 (XGR2) The XGR2 register (Figure 9-13) provides access to the RISC core’s register 2. Module Base +0x00024 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR2 W Reset 7 0 0 0 0 0 0 0 0 Figure 9-13. XGATE Register 2 (XGR2) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 9-11. XGR2 Field Descriptions Field 15–0 XGR2[15:0] 9.3.2.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.12 XGATE Register 4 (XGR4) The XGR4 register (Figure 9-15) provides access to the RISC core’s register 4. Module Base +0x00028 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR4 W Reset 7 0 0 0 0 0 0 0 0 Figure 9-15. XGATE Register 4 (XGR4) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 9-13. XGR4 Field Descriptions Field 15–0 XGR4[15:0] 9.3.2.
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Chapter 9 XGATE (S12XGATEV2) 9.3.2.14 XGATE Register 6 (XGR6) The XGR6 register (Figure 9-17) provides access to the RISC core’s register 6. Module Base +0x0002C 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR6 W Reset 7 0 0 0 0 0 0 0 0 Figure 9-17. XGATE Register 6 (XGR6) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 9-15. XGR6 Field Descriptions Field 15–0 XGR6[15:0] 9.3.2.
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Chapter 9 XGATE (S12XGATEV2) 9.4 Functional Description The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 9-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible.
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Chapter 9 XGATE (S12XGATEV2) 9.4.2 Programmer’s Model Register Block 15 15 R7 R6 Program Counter 0 0 R5 15 R4 15 R3 15 R2 15 R1(Variable Pointer) 0 PC 0 15 15 15 0 0 Condition Code Register NZVC 3 2 1 0 0 0 R0 = 0 0 Figure 9-19. Programmer’s Model The programmer’s model of the XGATE RISC core is shown in Figure 9-19. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers.
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Chapter 9 XGATE (S12XGATEV2) XGVBR +$0000 unused Code +$0024 Channel $09 Initial Program Counter Channel $09 Initial Variable Pointer +$0028 Channel $0A Initial Program Counter Variables Channel $0A Initial Variable Pointer +$002C Channel $0B Initial Program Counter Channel $0B Initial Variable Pointer +$0030 Channel $0C Initial Program Counter Code Channel $0C Initial Variable Pointer +$01E0 Channel $78 Initial Program Counter Variables Channel $78 Initial Variable Pointer Figure 9-20.
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Chapter 9 XGATE (S12XGATEV2) %1 ⇒ XGSEM %0 ⇒ XGSEM SSEM Instruction LOCKED BY S12X_CPU LOCKED BY XGATE M SE XG EM ⇒ 0 . GS % EM str X r ⇒ o GS In X M 1 % ⇒ E 1 SS % nd a In CS st E ru M ct In SS io st E n ru M ct io n %1 ⇒ XGSEM SSEM Instruction CSEM Instruction UNLOCKED %0 ⇒ XGSEM CSEM Instruction Figure 9-21. Semaphore State Transitions MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) Figure 9-22 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown. S12X_CPU .........
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Chapter 9 XGATE (S12XGATEV2) 9.5 9.5.1 Interrupts Incoming Interrupt Requests XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide. 9.5.
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Chapter 9 XGATE (S12XGATEV2) • • 9.6.2 Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly.
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Chapter 9 XGATE (S12XGATEV2) 3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.
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Chapter 9 XGATE (S12XGATEV2) 9.8.1.1 Naming Conventions RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.
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Chapter 9 XGATE (S12XGATEV2) 9.8.1.4 Immediate 4-Bit Wide (IMM4) The 4-bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples: LSL LSR 9.8.1.5 R4,#1 R4,#3 ; R4 = R4 << 1; shift register R4 by 1 bit to the left ; R4 = R4 >> 3; shift register R4 by 3 bits to the right Immediate 8-Bit Wide (IMM8) The 8-bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples: ADDL SUBL LDH CMPL 9.8.1.
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Chapter 9 XGATE (S12XGATEV2) 9.8.1.8 Dyadic Addressing (DYA) In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated.
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Chapter 9 XGATE (S12XGATEV2) 9.8.1.13 Index Register plus Register Offset (IDR) For load and store instructions (RS, RI) provides a variable offset in a register. Examples: LDB STW 9.8.1.14 R4,(R1,R2) R4,(R1,R2) ; loads a byte from R1+R2 into R4 ; stores R4 as a word to R1+R2 Index Register plus Register Offset with Post-increment (IDR+) [RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory.
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Chapter 9 XGATE (S12XGATEV2) 9.8.2.2 Logic and Arithmetic Instructions All logic and arithmetic instructions support the 8-bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2). All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will not be affected for logical operations. ADDL ANDH R2,#1 R4,#$FE ; increment R2 ; R4.H = R4.
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Chapter 9 XGATE (S12XGATEV2) 9.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.
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Chapter 9 XGATE (S12XGATEV2) 9.8.3 Cycle Notation Table 9-17 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16-bit operations. Lowercase letters denote 8-bit operations.
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Chapter 9 XGATE (S12XGATEV2) ADC ADC Add with Carry Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions.
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Chapter 9 XGATE (S12XGATEV2) ADD ADD Add without Carry Operation RS1 + RS2 ⇒ RDRD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16-bit addition and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 9 XGATE (S12XGATEV2) ADDH ADDH Add Immediate 8-Bit Constant (High Byte) Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8-Bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16-bit immediate addition.
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Chapter 9 XGATE (S12XGATEV2) ADDL Add Immediate 8-Bit Constant (Low Byte) ADDL Operation RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8-Bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16-bit immediate addition in conjunction with the ADDH instruction. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise.
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Chapter 9 XGATE (S12XGATEV2) AND AND Logical AND Operation RS1 & RS2 ⇒ RDRD & IMM16 ⇒ RD (translates to ANDL RD, #IMM[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16-bit values and stores the result in the destination register RD. Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.
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Chapter 9 XGATE (S12XGATEV2) ANDH Logical AND Immediate 8-Bit Constant (High Byte) ANDH Operation RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8-bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 9 XGATE (S12XGATEV2) ANDL Logical AND Immediate 8-Bit Constant (Low Byte) ANDL Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the low byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8-Bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 9 XGATE (S12XGATEV2) ASR ASR Arithmetic Shift Right Operation n b15 RD C n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 9 XGATE (S12XGATEV2) BCC BCC Branch if Carry Cleared (Same as BHS) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCC REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BCS BCS Branch if Carry Set (Same as BLO) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BEQ BEQ Branch if Equal Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BEQ REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 418
Chapter 9 XGATE (S12XGATEV2) BFEXT BFEXT Bit Field Extract Operation RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD. The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
PAGE 419
Chapter 9 XGATE (S12XGATEV2) BFFO BFFO Bit Field Find First One Operation FirstOne (RS) ⇒ RD; Searches the first “1” beginning from the MSB=15 down to LSB=0 in register RS and places the result into the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the whole RS register at all.
PAGE 420
Chapter 9 XGATE (S12XGATEV2) BFINS BFINS Bit Field Insert Operation RS1[w:0] ⇒ RD[(w+o):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to clear bits.
PAGE 421
Chapter 9 XGATE (S12XGATEV2) BFINSI BFINSI Bit Field Insert and Invert Operation !RS1[w:0] ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits.
PAGE 422
Chapter 9 XGATE (S12XGATEV2) BFINSX BFINSX Bit Field Insert and XNOR Operation !(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits.
PAGE 423
Chapter 9 XGATE (S12XGATEV2) BGE BGE Branch if Greater than or Equal to Zero Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≥ RS2: SUB BGE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGE REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 424
Chapter 9 XGATE (S12XGATEV2) BGT BGT Branch if Greater than Zero Operation If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 > RS2: SUB BGE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGT REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 425
Chapter 9 XGATE (S12XGATEV2) BHI BHI Branch if Higher Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 > RS2: SUB BHI R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHI REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 426
Chapter 9 XGATE (S12XGATEV2) BHS BHS Branch if Higher or Same (Same as BCC) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≥ RS2: SUB BHS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 427
Chapter 9 XGATE (S12XGATEV2) BITH BITH Bit Test Immediate 8-Bit Constant (High Byte) Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant. Only the condition code flags get updated, but no result is written back CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8-bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 428
Chapter 9 XGATE (S12XGATEV2) BITL BITL Bit Test Immediate 8-Bit Constant (Low Byte) Operation RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the low byte of register RD and an immediate 8-Bit constant. Only the condition code flags get updated, but no result is written back. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8-bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 429
Chapter 9 XGATE (S12XGATEV2) BLE BLE Branch if Less or Equal to Zero Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≤ RS2: SUB BLE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLE REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BLO BLO Branch if Carry Set (Same as BCS) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 < RS2: SUB BLO R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLO REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 431
Chapter 9 XGATE (S12XGATEV2) BLS BLS Branch if Lower or Same Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≤ RS2: SUB BLS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLS REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BLT BLT Branch if Lower than Zero Operation If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 < RS2: SUB BLT R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLT REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 433
Chapter 9 XGATE (S12XGATEV2) BMI BMI Branch if Minus Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BMI REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 434
Chapter 9 XGATE (S12XGATEV2) BNE BNE Branch if Not Equal Operation If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BNE REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 435
Chapter 9 XGATE (S12XGATEV2) BPL BPL Branch if Plus Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BPL REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BRA BRA Branch Always Operation PC + $0002 + (REL10 << 1) ⇒ PC Branches always CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BRA REL10 Address Mode REL10 Machine Code 0 0 1 1 1 1 Cycles REL10 PP MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BRK BRK Break Operation Put XGATE into Debug Mode (see Section 9.6.2, “Entering Debug Mode”)and signals a Software breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BRK Address Mode INH Machine Code 0 0 0 0 0 0 0 0 0 0 Cycles 0 0 0 0 0 0 PAff MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BVC BVC Branch if Overflow Cleared Operation If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVC REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) BVS BVS Branch if Overflow Set Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVS REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) CMP CMP Compare Operation RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16-bit values and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 441
Chapter 9 XGATE (S12XGATEV2) CMPL Compare Immediate 8-Bit Constant (Low Byte) CMPL Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8-Bit constant IMM8 contained in the instruction code from the low byte of the source register RS.L using binary subtraction and updates the condition code register accordingly. Remark: There is no equivalent operation using triadic addressing.
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Chapter 9 XGATE (S12XGATEV2) COM COM One’s Complement Operation ~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
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Chapter 9 XGATE (S12XGATEV2) CPC CPC Compare with Carry Operation RS2 – RS1 − Χ ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 444
Chapter 9 XGATE (S12XGATEV2) CPCH CPCH Compare Immediate 8-Bit Constant with Carry (High Byte) Operation RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and the 8-Bit constant IMM8 contained in the instruction code from the high byte of the source register RD using binary subtraction and updates the condition code register accordingly.
PAGE 445
Chapter 9 XGATE (S12XGATEV2) CSEM CSEM Clear Semaphore Operation Unlocks a semaphore that was locked by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 9 XGATE (S12XGATEV2) CSL CSL Logical Shift Left with Carry Operation n C RD C C C C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
PAGE 447
Chapter 9 XGATE (S12XGATEV2) CSR CSR Logical Shift Right with Carry Operation n C C C C RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
PAGE 448
Chapter 9 XGATE (S12XGATEV2) JAL JAL Jump and Link Operation PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and saves the return address in RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form JAL RD Address Mode MON Machine Code 0 0 0 0 0 RD 1 1 Cycles 1 1 0 1 1 0 PP MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) LDB LDB Load Byte from Memory (Low Byte) Operation M[RB, #OFFS5] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H Loads a byte from memory into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 450
Chapter 9 XGATE (S12XGATEV2) LDH LDH Load Immediate 8-Bit Constant (High Byte) Operation IMM8 ⇒ RD.H; Loads an eight bit immediate constant into the high byte of register RD. The low byte is not affected. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDH RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 1 RD Cycles IMM8 P MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 451
Chapter 9 XGATE (S12XGATEV2) LDL LDL Load Immediate 8-Bit Constant (Low Byte) Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an eight bit immediate constant into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDL RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 0 RD Cycles IMM8 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) LDW LDW Load Word from Memory Operation M[RB, #OFFS5] ⇒ RD M[RB, RI] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16-bit value into the register RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 453
Chapter 9 XGATE (S12XGATEV2) LSL LSL Logical Shift Left Operation n C RD 0 0 0 0 n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 9 XGATE (S12XGATEV2) LSR LSR Logical Shift Right Operation n 0 0 0 0 RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
PAGE 455
Chapter 9 XGATE (S12XGATEV2) MOV MOV Move Register Content Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form MOV RD, RS Address Mode TRI Machine Code 0 0 0 1 0 RD 0 0 Cycles 0 RS 1 0 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) NEG NEG Two’s Complement Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 457
Chapter 9 XGATE (S12XGATEV2) NOP NOP No Operation Operation No Operation for one cycle. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form NOP Address Mode INH Machine Code 0 0 0 0 0 0 0 1 0 0 Cycles 0 0 0 0 0 0 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) OR OR Logical OR Operation RS1 | RS2 ⇒ RDRD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16-bit values and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
PAGE 459
Chapter 9 XGATE (S12XGATEV2) ORH ORH Logical OR Immediate 8-Bit Constant (High Byte) Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8-Bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 460
Chapter 9 XGATE (S12XGATEV2) ORL ORL Logical OR Immediate 8-Bit Constant (Low Byte) Operation RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the low byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8-Bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 461
Chapter 9 XGATE (S12XGATEV2) PAR PAR Calculate Parity Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects N Z V C 0 ∆ 0 ∆ N: Z: V: C: 0; cleared. Set if RD is $0000; cleared otherwise. 0; cleared. Set if there the number of ones in the register RD is odd; cleared otherwise.
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Chapter 9 XGATE (S12XGATEV2) ROL ROL Rotate Left Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the left. The lower n bits of the register RD are filled with the upper n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
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Chapter 9 XGATE (S12XGATEV2) ROR ROR Rotate Right Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
PAGE 464
Chapter 9 XGATE (S12XGATEV2) RTS RTS Return to Scheduler Operation Terminates the current thread of program execution and remains idle until a new thread is started by the hardware scheduler. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form RTS Address Mode INH Machine Code 0 0 0 0 0 0 1 0 0 0 Cycles 0 0 0 0 0 0 PA MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 465
Chapter 9 XGATE (S12XGATEV2) SBC SBC Subtract with Carry Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward from the previous operation allowing 32 and more bit subtractions.
PAGE 466
Chapter 9 XGATE (S12XGATEV2) SSEM SSEM Set Semaphore Operation Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set. CCR Effects N Z V C — — — ∆ N: Z: V: C: Not affected. Not affected. Not affected. Set if semaphore is locked by the RISC core; cleared otherwise.
PAGE 467
Chapter 9 XGATE (S12XGATEV2) SEX SEX Sign Extend Byte to Word Operation The result in RD is the 16-bit sign extended representation of the original two’s complement number in the low byte of RD.L. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
PAGE 468
Chapter 9 XGATE (S12XGATEV2) SIF SIF Set Interrupt Flag Operation Sets the Interrupt Flag of an XGATE Channel. This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic address form is used, the interrupt flag associated with the channel id number contained in RS[6:0] is set. The content of RS[15:7] is ignored. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected.
PAGE 469
Chapter 9 XGATE (S12XGATEV2) STB STB Store Byte to Memory (Low Byte) Operation RS.L⇒ M[RB, #OFFS5] RS.L⇒ M[RB, RI] RS.L⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]1 Stores the low byte of register RD to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 470
Chapter 9 XGATE (S12XGATEV2) STW STW Store Word to Memory Operation RS ⇒ M[RB, #OFFS5] RS ⇒ M[RB, RI] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI]1 Stores the content of register RS to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 471
Chapter 9 XGATE (S12XGATEV2) SUB SUB Subtract without Carry Operation RS1 – RS2 ⇒ RDRD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM[15:8]) Subtracts two 16-bit values and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 472
Chapter 9 XGATE (S12XGATEV2) SUBH SUBH Subtract Immediate 8-Bit Constant (High Byte) Operation RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8-Bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD. This instruction can be used after an SUBL for a 16-bit immediate subtraction.
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Chapter 9 XGATE (S12XGATEV2) SUBL Subtract Immediate 8-Bit Constant (Low Byte) SUBL Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 Bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8-bit operation; cleared otherwise.
PAGE 474
Chapter 9 XGATE (S12XGATEV2) TFR TFR Transfer from and to Special Registers Operation TFR RD,CCR: CCR ⇒ RD[3:0], 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD Transfers the content of one RISC core register to another. The TFR RD,PC instruction can be used to implement relative subroutine calls. Example: RETADDR SUBR TFR BRA ... ...
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Chapter 9 XGATE (S12XGATEV2) TST TST Test Register Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 9 XGATE (S12XGATEV2) XNOR XNOR Logical Exclusive NOR Operation ~(RS1 ^ RS2) ⇒ RD~(RD ^ IMM16) ⇒ RD (translates to XNOR RD, #IMM[15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusive NOR between two 16-bit values and stores the result in the destination register RD. Remark: Using R0 as a source registers will calculate the one’s complement of the other source register. Using R0 as both source operands will fill RD with $FFFF.
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Chapter 9 XGATE (S12XGATEV2) XNORH Logical Exclusive NOR Immediate 8-Bit Constant (High Byte) XNORH Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8-bit result is $00; cleared otherwise. 0; cleared.
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Chapter 9 XGATE (S12XGATEV2) XNORL Logical Exclusive NOR Immediate 8-Bit Constant (Low Byte) XNORL Operation ~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8-Bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8-bit result is $00; cleared otherwise. 0; cleared.
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Chapter 9 XGATE (S12XGATEV2) 9.8.6 Instruction Coding Table 9-18 summarizes all XGATE instructions in the order of their machine coding. Table 9-18.
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Chapter 9 XGATE (S12XGATEV2) Table 9-18.
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Chapter 9 XGATE (S12XGATEV2) Table 9-18.
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Chapter 9 XGATE (S12XGATEV2) 9.9 Initialization and Application Information 9.9.1 Initialization The recommended initialization of the XGATE is as follows: 1. Clear the XGE bit to suppress any incoming service requests. 2. Make sure that no thread is running on the XGATE. This can be done in several ways: a) Poll the XGCHID register until it reads $00. Also poll XGDBG and XGSWEIF to make sure that the XGATE has not been stopped. b) Enter Debug Mode by setting the XGDBG bit. Clear the XGCHID register.
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Chapter 9 XGATE (S12XGATEV2) XGCHID XGVBR XGIF XGSWT XGSEM EQU EQU EQU EQU EQU XGATE_REGS+$02 XGATE_REGS+$06 XGATE_REGS+$08 XGATE_REGS+$18 XGATE_REGS+$1A ;XGATE ;XGATE ;XGATE ;XGATE ;XGATE Channel ID Register Vector Base Register Interrupt Flag Vector Software Trigger Register Semaphore Register RPAGE EQU $0016 RAM_SIZE RAM_START_GLOBAL RAM_START_XGATE RAM_START_S12 RPAGE_VALUE EQU EQU EQU EQU EQU 20*$400 ;20k RAM $10_0000-RAM_SIZE $1_0000-RAM_SIZE $1000 RAM_START_GLOBAL>>12 XGATE_VECTORS XGATE_
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Chapter 9 XGATE (S12XGATEV2) STD STD 2,X+ 2,X+ MOVW #$FF00, XGSWT ;clear all software triggers ;########################################### ;# INITIALIZE XGATE VECTOR SPACE # ;########################################### INIT_XGATE_VECTOR_SPACE MOVB #(RAM_START_GLOBAL>>12), RPAGE ;set all vectors to dummy service routine LDX #128 LDY #RAM_START_S12 LDD #XGATE_DUMMY+XGATE_OFFSET INIT_XGATE_VECTOR_SPACE_LOOP STD 4,Y+ DBNE X,INIT_XGATE_VECTOR_SPACE_LOOP ;set SCI INTERRUPT VECTOR MOVW #XGATE_CODE_BEGIN+XGA
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Chapter 9 XGATE (S12XGATEV2) XGATE_CODE_DONE XGATE_CODE_END XGATE_DUMMY STB CMPL BEQ RTS LDL STB LDL STB RTS EQU R4,(R2,#(SCIDRL-SCI_REGS)) R4,#$0D XGATE_CODE_DONE ;initiate SCI transmit R4,#$00 ;disable SCI interrupts R4,(R2,#(SCICR2-SCI_REGS)) R3,#(XGATE_DATA_MSG-XGATE_DATA_BEGIN);reset R3 R3,(R1,#(XGATE_DATA_MSG_IDX-XGATE_DATA_BEGIN)) XGATE_CODE_END MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 10 Security (S12X9SECV2) 10.1 Introduction This specification describes the function of the security mechanism in the S12X chip family (MC9S12XDP512). 10.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program.
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Chapter 10 Security (S12X9SECV2) Table 10-1.
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Chapter 10 Security (S12X9SECV2) The meaning of the bits KEYEN[1:0] is shown in Table 10-2. Please refer to Section 10.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 10-2. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 10-3. For security reasons, the state of device security is controlled by two bits.
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Chapter 10 Security (S12X9SECV2) 10.1.4.1 • • • • Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. 10.1.4.2 • • • • • Normal Single Chip Mode (NS) Special Single Chip Mode (SS) BDM firmware commands are disabled.
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Chapter 10 Security (S12X9SECV2) 10.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 10.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method.
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Chapter 10 Security (S12X9SECV2) If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below.
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Chapter 10 Security (S12X9SECV2) Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate value to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPROT register to disable protection. 4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits. 5. Write 0x0000 to the EDATA register (0x011A–0x011B). 6. Write 0x0000 to the EADDR register (0x0118–0x0119). 7. Write 0x41 (mass erase) to the ECMD register. 8.
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Chapter 10 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.1 Introduction The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.1.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.2 External Signal Description The ECT module has a total of eight external pins. 11.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7. 11.2.2 IOC6 — Input Capture and Output Compare Channel 6 This pin serves as input capture or output compare for channel 6. 11.2.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 11.3.1 Module Memory Map The memory map for the ECT module is given below in Table 11-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register. Table 11-1.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-1.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Register Name Bit 7 0x000D TSCR2 W 0x000E TFLG1 W 0x000F TFLG2 R R R W TOI C7F TOF 6 5 4 3 2 1 Bit 0 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0x0010 R TC0 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0011 TC0 (Low) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0012 R TC1 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x001C R TC6 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x001D TC6 (Low) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001E R TC7 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x001F TC7 (Low) W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 PACTL W PAEN PAMOD PEDGE CLK1 CLK0 PA0VI PAI 0 0 0 0 0 PA0VF P
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Register Name 0x002B ICSYS W 0x002C Reserved W 0x002D TIMTST 0x002E PTPSR R 0x0031 PBFLG 6 5 4 3 2 1 Bit 0 SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ R Reserved R Timer Test Register W R W 0x002F R PTMCPSR W 0x0030 PBCTL Bit 7 R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 0 0 0 0 0 W PBOVI 0 0 0 0 0 0 0 PA3H7 PA3H6 PA3H5 PA3H4
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x003A R TC1H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003B R TC1H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0x003C R TC2H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003D R TC2H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0x003E R TC3H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003F R TC3H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 = Unim
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Reset Figure 11-4. Timer Compare Force Register (CFORC) Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero. Table 11-3.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 Figure 11-6. Output Compare 7 Data Register (OC7D) Read or write: Anytime All bits reset to zero. Table 11-5.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.5 Timer Count Register (TCNT) Module Base + 0x0004 R W Reset 15 14 13 12 11 10 9 8 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 Figure 11-7. Timer Count Register High (TCNT) Module Base + 0x0005 R W Reset 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 Figure 11-8.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.6 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 7 R W Reset 6 5 4 3 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 0 0 2 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-9. Timer System Control Register 1 (TSCR1) Read or write: Anytime except PRNT bit is write once All bits reset to zero. Table 11-7.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.7 Timer Toggle On Overflow Register 1 (TTOV) Module Base + 0x0007 R W Reset 7 6 5 4 3 2 1 0 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0 0 0 0 0 0 0 0 Figure 11-10. Timer Toggle On Overflow Register 1 (TTOV) Read or write: Anytime All bits reset to zero. Table 11-8. TTOV Field Descriptions Field Description 7:0 TOV[7:0] Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 Figure 11-11. Timer Control Register 1 (TCTL1) Module Base + 0x0009 R W Reset 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 Figure 11-12.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4) Module Base + 0x000A R W Reset 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 Figure 11-13. Timer Control Register 3 (TCTL3) Module Base + 0x000B R W Reset 7 6 5 4 3 2 1 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 Figure 11-14.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.10 Timer Interrupt Enable Register (TIE) Module Base + 0x000C R W Reset 7 6 5 4 3 2 1 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 Figure 11-15. Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register. Table 11-13.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R W Reset TOI 0 6 5 4 0 0 0 0 0 0 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 = Unimplemented or Reserved Figure 11-16. Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. Table 11-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E R W Reset 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 11-17. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) Module Base + 0x000F 7 R W Reset TOF 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-18. Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.14 Timer Input Capture/Output Compare Registers 0–7 Module Base + 0x0010 R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 11-19. Timer Input Capture/Output Compare Register 0 High (TC0) Module Base + 0x0011 R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 11-20.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Module Base + 0x0016 R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 11-25. Timer Input Capture/Output Compare Register 3 High (TC3) Module Base + 0x0017 R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 11-26.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Module Base + 0x001C R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 11-31. Timer Input Capture/Output Compare Register 6 High (TC6) Module Base + 0x001D R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 11-32.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL) Module Base + 0x0020 7 R 0 W Reset 0 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-35. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime All bits reset to zero. Table 11-18.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-18. PACTL Field Descriptions (continued) Field 0 PAI Description Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAIF is set . Table 11-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Divide by 64 clock enabled with pin high level 1 1 Divide by 64 clock enabled with pin low level Table 11-20.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”). Table 11-21.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. 11.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0) Module Base + 0x0024 7 R W Reset 6 5 4 3 2 PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) 0 0 0 0 0 0 1 0 PACNT1(9) PACNT0(8) 0 0 Figure 11-39.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL) Module Base + 0x0026 7 R W Reset 6 5 MCZI MODMC RDMCL 0 0 0 4 3 0 0 ICLAT FLMC 0 0 2 1 0 MCEN MCPR1 MCPR0 0 0 0 Figure 11-41. 16-Bit Modulus Down-Counter Control Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero. Table 11-22.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-23. Modulus Counter Prescaler Select MCPR1 MCPR0 Prescaler Division 0 0 1 0 1 4 1 0 8 1 1 16 11.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG) Module Base + 0x0027 7 R W Reset MCZF 0 6 5 4 3 2 1 0 0 0 0 POLF3 POLF2 POLF1 POLF0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-42.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR) Module Base + 0x0028 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PA3EN PA2EN PA1EN PA0EN 0 0 0 0 = Unimplemented or Reserved Figure 11-43. Input Control Pulse Accumulators Register (ICPAR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.22 Delay Counter Control Register (DLYCT) Module Base + 0x0029 R W Reset 7 6 5 4 3 2 1 0 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 0 0 0 0 0 0 0 0 Figure 11-44. Delay Counter Control Register (DLYCT) Read: Anytime Write: Anytime All bits reset to zero. Table 11-26.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-28. Delay Counter Select Examples when PRNT = 1 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 Delay 1 1 1 1 1 1 1 1 1024 bus clock cycles 11.3.2.23 Input Control Overwrite Register (ICOVW) Module Base + 0x002A R W Reset 7 6 5 4 3 2 1 0 NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 0 0 0 0 0 0 0 0 Figure 11-45.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.24 Input Control System Control Register (ICSYS) Module Base + 0x002B R W Reset 7 6 5 4 3 2 1 0 SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ 0 0 0 0 0 0 0 0 Figure 11-46. Input Control System Register (ICSYS) Read: Anytime Write: Once in normal modes All bits reset to zero. Table 11-30.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-30. ICSYS Field Descriptions (continued) Field Description 0 LATQ Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-32. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 0 0 0 0 0 1 1 0 7 0 0 0 0 0 1 1 1 8 0 0 0 0 1 1 1 1 16 0 0 0 1 1 1 1 1 32 0 0 1 1 1 1 1 1 64 0 1 1 1 1 1 1 1 128 1 1 1 1 1 1 1 1 256 11.3.2.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Table 11-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued) PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 Prescaler Division Rate 0 0 0 0 0 1 0 1 6 0 0 0 0 0 1 1 0 7 0 0 0 0 0 1 1 1 8 0 0 0 0 1 1 1 1 16 0 0 0 1 1 1 1 1 32 0 0 1 1 1 1 1 1 64 0 1 1 1 1 1 1 1 128 1 1 1 1 1 1 1 1 256 11.3.2.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.28 Pulse Accumulator B Flag Register (PBFLG) Module Base + 0x0031 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 PBOVF 0 0 0 0 = Unimplemented or Reserved Figure 11-50. Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.29 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) Module Base + 0x0032 R 7 6 5 4 3 2 1 0 PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-51.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.30 Modulus Down-Counter Count Register (MCCNT) Module Base + 0x0036 R W Reset 15 14 13 12 11 10 9 8 MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10 MCCNT9 MCCNT8 1 1 1 1 1 1 1 1 Figure 11-55. Modulus Down-Counter Count Register High (MCCNT) Module Base + 0x0037 R W Reset 7 6 5 4 3 2 1 0 MCCNT7 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT9 1 1 1 1 1 1 1 1 Figure 11-56.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.3.2.31 Timer Input Capture Holding Registers 0–3 (TCxH) Module Base + 0x0038 R 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-57. Timer Input Capture Holding Register 0 High (TC0H) Module Base + 0x0039 R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-58.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Module Base + 0x003D R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 11-62. Timer Input Capture Holding Register 2 Low (TC2H) Module Base + 0x003E R 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 11-63.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Bus Clock ÷ 1, 4, 8, 16 Bus Clock Timer Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 P0 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Bus Clock ÷ 1, 2,3, ..., 256 Bus Clock Timer Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 P0 RESET Underflow 16-Bit Free-Running 16 BITMain MAINTimer TIMER ÷ 1, 2,3, ..., 256 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 8, 12, 16, ..., 1024 0 P1 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 16-Bit Free-Running 16 BITMain MAIN TIMER Timer ÷ 1, 4, 8, 16 Bus Clock 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. 0 P2 P4 Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) ÷1, 2, 3, ... 256 Bus Clock 16-Bit Free-Running 16 BITMain MAIN TIMER Timer Timer Prescaler ÷ 1, 2, 3, ... 256 16-Bit Load Register Modulus Prescaler 16-Bit Modulus Down Counter Bus Clock 0 P0 RESET Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 LATCH0 8, 12, 16, ... 1024 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Load Holding Register and Reset Pulse Accumulator 0 8, 12,16, ..., 1024 8-Bit PAC0 (PACN0) EDG0 P0 Edge Detector Delay Counter PA0H Holding Register Interrupt 0 8, 12,16, ..., 1024 EDG1 P1 Edge Detector 8-Bit PAC1 (PACN1) Delay Counter PA1H Holding Register 0 8, 12,16, ..., 1024 EDG2 P2 Edge Detector 8-Bit PAC2 (PACN2) Delay Counter PA2H Holding Register Interrupt 8, 12,16, ...
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) TIMCLK (Timer Clock) CLK1 CLK0 PACLK / 256 Clock Select (PAMOD) PACLK PACLK / 65536 Prescaled Clock (PCLK) 4:1 MUX Edge Detector P7 Interrupt 8-Bit PAC3 (PACN3) 8-Bit PAC2 (PACN2) MUX PACA Bus Clock Divide by 64 Interrupt 8-Bit PAC1 (PACN1) 8-Bit PAC0 (PACN0) Delay Counter PACB Edge Detector P0 Figure 11-70.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called input capture (IC) channels.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 11.4.1.1, “IC Channels”). This will prevent the captured value from being overwritten until it is read or latched in the holding register. 2.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.4.1.2 OC Channel Initialization Internal register whose output drives OCx when TIOS is set, can be force loaded with a desired data by writing to CFORC register before OCx is configured for output compare action. This allows a glitch free switch over of port from general purpose I/O to timer output once the output compare is enabled. 11.4.1.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.4.1.6 Flag Clearing Mechanisms The flags in the ECT can be cleared one of two ways: 1. Normal flag clearing mechanism (TFFCA = 0) Any of the ECT flags can be cleared by writing a one to the flag. 2. Fast flag clearing mechanism (TFFCA = 1) With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing the various registers associated with the ECT modes of operation as described below.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. Table 11-37 lists the interrupts generated by the ECT to communicate with the MCU. Table 11-37.
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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.1 Introduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel. Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.1.3 Block Diagram Figure 12-1 shows the block diagram for the 8-bit 8-channel PWM block.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.2.3 PWM5 — PWM Channel 5 This pin serves as waveform output of PWM channel 5. 12.2.4 PWM4 — PWM Channel 4 This pin serves as waveform output of PWM channel 4. 12.2.5 PWM3 — PWM Channel 3 This pin serves as waveform output of PWM channel 3. 12.2.6 PWM3 — PWM Channel 2 This pin serves as waveform output of PWM channel 2. 12.2.7 PWM3 — PWM Channel 1 This pin serves as waveform output of PWM channel 1. 12.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 12.3.2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 R 0x000B PWMSCNTB W 1 0 0 0 0 0 0 0 0 0x000C R PWMCNT0 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000D R PWMCNT1 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000E R PWMCNT2 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000F R PWMCNT3 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x0010 R PWMCNT4 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x001A R PWMPER6 W Bit 7 6 5 4 3 2 1 Bit 0 0x001B R PWMPER7 W Bit 7 6 5 4 3 2 1 Bit 0 0x001C R PWMDTY0 W Bit 7 6 5 4 3 2 1 Bit 0 0x001D R PWMDTY1 W Bit 7 6 5 4 3 2 1 Bit 0 0x001E R PWMDTY2 W Bit 7 6 5 4 3 2 1 Bit 0 0x001F R PWMDTY3 W Bit 7 6 5 4 3 2 1 Bit 0 0x0010 R PWMDTY4 W Bit 7 6 5 4 3 2 1 Bit 0 0x0021 R PWMDTY5 W Bit 7 6 5 4 3 2 1 Bit 0
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts off for power savings.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Table 12-1. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0 0 0 0 0 0 0 0 Figure 12-5. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 12-3.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0003 7 R 0 W Reset 0 6 5 4 3 PCKB2 PCKB1 PCKB0 0 0 0 0 2 1 0 PCKA2 PCKA1 PCKA0 0 0 0 0 = Unimplemented or Reserved Figure 12-6. PWM Prescale Clock Select Register (PWMPRCLK) Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 12-4.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See Section 12.4.2.5, “Left Aligned Outputs” and Section 12.4.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 12.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. Table 12-8.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 12-9.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 12-11. PWM Scale A Register (PWMSCLA) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value) 12.3.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x000A, 0x000B R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 12-13. Reserved Registers (PWMSCNTx) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality. 12.3.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime (any value written causes PWM counter to be reset to $00). 12.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime 12.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. Module Base + 0x0024 R W Reset 7 6 PWMIF PWMIE 0 0 5 0 PWMRSTRT 0 4 PWMLVL 0 3 2 0 PWM7IN 0 0 1 0 PWM7INL PWM7ENA 0 0 = Unimplemented or Reserved Figure 12-17.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.4 Functional Description 12.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Clock A PCKA2 PCKA1 PCKA0 Clock A/2, A/4, A/6,....A/512 8-Bit Down Counter Clock to PWM Ch 0 PCLK0 Count = 1 M U X Load PWMSCLA M U X Clock SA DIV 2 PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 M U X 2 4 8 16 32 64 128 Divide by Prescaler Taps: X PCLK3 Clock B Clock B/2, B/4, B/6,....
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 12.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 12-20.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 12-21. PWM Left Aligned Output Example Waveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 12-23 is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 12-23. PWM Center Aligned Output Example Waveform 12.4.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High Low PWMCNT6 PWCNT7 Period/Duty Compare PWM7 Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 12-24.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 12-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 12-11. 16-bit Concatenation Mode Summary 12.4.2.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active.
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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 13.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 13-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 13-1. IIC Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.2 External Signal Description The MC9S12XDP512 module has two external pins. 13.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 13.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 13.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-2. IBAD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. 0 Reserved Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0. 13.3.2.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description IBC5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 010 2 9 6 4 011 6 9 6 8 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 Table 13-5.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description SDA SCL Hold(stop) SCL Hold(start) SCL START condition STOP condition Figure 13-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 13-6.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-6.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-6.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-6.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-6.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.3.2.3 IIC Control Register (IBCR) Offset Module Base + 0x0002 7 6 5 4 3 IBEN IBIE MS/SL Tx/Rx TXAK R 1 0 0 0 IBSWAI RSTA W Reset 2 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. IIC Bus Control Register (IBCR) Read and write anytime Table 13-7. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-7. IBCR Field Descriptions (continued) Field Description 2 RSTA Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Table 13-8. IBSR Field Descriptions (continued) Field Description 6 IAAS Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.3.2.5 IIC Data I/O Register (IBDR) Offset Module Base + 0x0004 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 R W Reset Figure 13-8. IIC Bus Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description MSB SCL SDA 1 LSB 2 3 4 5 6 7 Calling Address Read/ Write MSB SDA Start Signal MSB 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal SCL 8 1 XXX 3 4 5 6 7 8 Read/ Write 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 1 XX Ack Bit 9 No Stop Ack Signal Bit MSB 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Calling Address 2 Ack Bit LSB 2 LSB 1 LSB 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.4.1.5 Repeated START Signal As shown in Figure 13-9, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine. 13.7 Initialization/Application Information 13.7.1 13.7.1.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.7.1.3 Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description MASR DEC BEQ MOVB DEC BNE BSET RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 ENMASR NXMAR BRA BCLR MOVB RTI NXMAR IBCR,#$20 IBDR,RXBUF 13.7.1.
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Clear IBIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear IBAL Y RXAK=0 ? N Last Byte To Be Read ? N Y N Y Y IAAS=1 ? IAAS=1 ? Y N Address Transfer End Of Addr Cycle (Master Rx) ? N Y Y (Read) 2nd Last Y Byte To Be Read ? SRW=1 ? Write Next Byte To IBDR Generate Stop Signal Set TXAK =1 Generate Stop Signal Read Data From IBDR And Store ACK From Receiver ? N Read Dat
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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.1 Introduction Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.1.2 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Message Filtering and Buffering Control and Status Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 14-1. MSCAN Block Diagram 14.1.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • Three low-power modes: sleep, power down, and MSCAN enable Global initialization of configuration registers 14.1.4 Modes of Operation The following modes of operation are specific to the MSCAN. See Section 14.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode 14.2 External Signal Description The MSCAN uses two external pins: 14.2.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN node 2 CAN node 1 CAN node n MCU CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 14-2. CAN System 14.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 14.3.1 Module Memory Map Table 14-1 gives an overview on all registers and their individual bits in the MSCAN memory map.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-1.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2 Register Descriptions This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. 14.3.2.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-2. CANCTL0 Register Field Descriptions (continued) Field Description 3 TIME Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. Module Base 0x0001 + 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 14-4.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-3. CANCTL1 Register Field Descriptions (continued) Field Description 2 WUPM Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 14.4.6.4, “MSCAN Sleep Mode”).
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0002 7 6 5 4 3 2 1 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 0 R W Reset: Figure 14-5. MSCAN Bus Timing Register 0 (CANBTR0) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 14-4.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0003 7 6 5 4 3 2 1 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 R W Reset: Figure 14-6. MSCAN Bus Timing Register 1 (CANBTR1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 14-7.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-9. Time Segment 1 Values 1 TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle1 0 0 0 1 2 Tq clock cycles1 0 0 1 0 3 Tq clock cycles1 0 0 1 1 4 Tq clock cycles : : : : : 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles This setting is not valid. Please refer to Table 14-36 for valid settings.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-10. CANRFLG Register Field Descriptions Field Description 7 WUPIF Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.4.6.4, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register. Module Base + 0x0005 7 6 5 4 3 2 1 0 WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE 0 0 0 0 0 0 0 0 R W Reset: Figure 14-8.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-11. CANRIER Register Field Descriptions (continued) Field Description 1 OVRIE Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. 0 RXFIE Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-12. CANTFLG Register Field Descriptions Field Description 2:0 TXE[2:0] Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of queued messages as described below. Module Base + 0x0008 R 7 6 5 4 3 0 0 0 0 0 2 1 0 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 W Reset: 0 0 0 0 0 = Unimplemented Figure 14-11.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 14-12.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. Module Base + 0x000A R 7 6 5 4 3 0 0 0 0 0 2 1 0 TX2 TX1 TX0 0 0 0 W Reset: 0 0 0 0 0 = Unimplemented Figure 14-13.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below. Module Base + 0x000B R 7 6 0 0 5 4 IDAM1 IDAM0 0 0 3 2 1 0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 W Reset: 0 0 = Unimplemented Figure 14-14.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. 14.3.2.13 MSCAN Reserved Register This register is reserved for factory testing of the MSCAN module and is not available in normal system operation modes.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-20. CANMISC Register Field Descriptions Field Description 0 BOHOLD Bus-off State Hold Until User Request — If BORM is set in Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 14.5.2, “Bus-Off Recovery,” for details.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.16 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. Module Base + 0x000F R 7 6 5 4 3 2 1 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 14-18.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 14.3.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7) R W Reset R W Reset R W Reset R W Reset 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7) R W Reset R W Reset R W Reset R W Reset 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.3 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x00X0 IDR0 0x00X1 IDR1 0x00X2 IDR2 0x00X3 IDR3 0x00X4 DSR0 R W R W R W R W R W R 0x00X5 DSR1 W 0x00X6 DSR2 W 0x00X7 DSR3 R R W R 0x00X8 DSR4 W 0x00X9 DSR5 W 0x00XA DSR6 0x00XB DSR7 0x00XC DLR R R W R W Bit 7 6 5 4 3 2 1 Bit0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Write: For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X1 7 6 5 4 3 2 1 0 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 x x x x x x x x R W Reset: Figure 14-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 14-27. IDR1 Register Field Descriptions — Extended Field Description 7:5 ID[20:18] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X3 7 6 5 4 3 2 1 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR x x x x x x x x R W Reset: Figure 14-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 14-29. IDR3 Register Field Descriptions — Extended Field Description 7:1 ID[6:0] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X1 7 6 5 4 3 ID2 ID1 ID0 RTR IDE (=0) x x x x x 2 1 0 x x x R W Reset: = Unused; always read ‘x’ Figure 14-30. Identifier Register 1 — Standard Mapping Table 14-31. IDR1 Register Field Descriptions Field Description 7:5 ID[2:0] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X3 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 14-32. Identifier Register 3 — Standard Mapping 14.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XB 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 x x x x R W Reset: x x x x = Unused; always read “x” Figure 14-34. Data Length Register (DLR) — Extended Identifier Mapping Table 14-33.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Module Base + 0xXXXD 7 6 5 4 3 2 1 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 0 0 0 0 0 0 0 0 R W Reset: Figure 14-35. Transmit Buffer Priority Register (TBPR) Read: Anytime when TXEx flag is set (see Section 14.3.2.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 14.4 14.4.1 Functional Description General This section provides a complete functional description of the MSCAN.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 RXF Receiver TxBG Tx0 MSCAN TxFG Tx1 TxBG Tx2 Transmitter CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 14-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 14.4.8.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 14-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 14-40.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-35. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.5 14.4.5.1 Modes of Operation Normal Modes The MSCAN module behaves as described within this specification in all normal system operation modes. 14.4.5.2 Special Modes The MSCAN module behaves as described within this specification in all special system operation modes. 14.4.5.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 14.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 14-37. CPU vs.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.6.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.6.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table 14-37) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.4.8.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see Table 14-38), any of which can be individually masked (for details see sections from Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 14.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 14-38.
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” and Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 14.4.8.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG).
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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) 14.5.2 Bus-Off Recovery The bus-off recovery is user configurable. The bus-off state can either be left automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specification for details).
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.1 Introduction This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 15.1.1 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) • • Hardware parity checking 1/16 bit-time noise detection 15.1.2 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode 15.1.3 Block Diagram Figure 15-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.2 External Signal Description The SCI module has a total of two external pins. 15.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 15.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 R W Reset 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 15-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 0 0 0 Figure 15-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Table 15-3. IRSCI Transmit Pulse Width 15.3.2.2 TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 SCI Control Register 1 (SCICR1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 15-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Table 15-4. SCICR1 Field Descriptions (continued) Field Description 2 ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x000a 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 15-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-6.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x001a 7 R W Reset RXEDGIE 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 BERRIE BKDIE 0 0 = Unimplemented or Reserved Figure 15-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-7.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x002a R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 BERRM1 BERRM0 BKDFE 0 0 0 = Unimplemented or Reserved Figure 15-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 15-8.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.6 SCI Control Register 2 (SCICR2) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 15-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 15-10. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Table 15-11. SCISR1 Field Descriptions (continued) Field Description 3 OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 7 R W Reset AMAP 0 6 5 0 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF 0 = Unimplemented or Reserved Figure 15-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 15-12. SCISR2 Field Descriptions Field Description 7 AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 7 R 6 R8 T8 W Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 15-13.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 15-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 15-15 below.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Figure 15-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 15-18.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 15.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-18 summarizes the results of the data bit samples. Table 15-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) In Figure 15-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) In Figure 15-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Figure 15-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.6.5.2 Fast Data Tolerance Figure 15-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 15-29.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 15.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected.
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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 16.1.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) This is a high level description only, detailed descriptions of operating modes are contained in Section 16.4.7, “Low Power Mode Options”. 16.1.3 Block Diagram Figure 16-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The MC9S12XDP512 module has a total of four external pins. 16.2.1 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. 16.2.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 3 16.3.2 Reading from this register returns all zeros. Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.3.2.1 SPI Control Register 1 (SPICR1) Module Base +0x___0 R W Reset 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 Figure 16-3. SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Table 16-2. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Table 16-3. SS Input / Output Selection 16.3.2.2 MODFEN SSOE Master Mode Slave Mode 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS is slave select output SS input SPI Control Register 2 (SPICR2) Module Base +0x___1 R 7 6 5 0 0 0 0 0 W Reset 0 4 3 MODFEN BIDIROE 0 0 2 0 0 1 0 SPISWAI SPC0 0 0 = Unimplemented or Reserved Figure 16-4.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Table 16-5. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 Bidirectional 1 X Master In Master Out 0 MISO not used by SPI Master In 1 Master I/O Slave Mode of Operation 16.3.2.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32 781.25 kHz 0 0 0 1 0 1 64 390.63 kHz 0 0 0 1 1 0 128 195.31 kHz 0 0 0 1 1 1 256 97.66 kHz 0 0 1 0 0 0 4 6.25 MHz 0 0 1 0 0 1 8 3.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.55 kHz 1 0 1 1 1 1 1536 16.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.3.2.4 SPI Status Register (SPISR) Module Base +0x___3 R 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 16-6. SPI Status Register (SPISR) Read: Anytime Write: Has no effect Table 16-8. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.3.2.5 SPI Data Register (SPIDR) Module Base +0x___5 R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 2 Bit 0 0 0 0 0 0 0 0 0 Figure 16-7. SPI Data Register (SPIDR) Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register = Unspecified Data C Data B Data A = Reception in progress Figure 16-8.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • SCK clock In slave mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. • SS pin The SS pin is the slave select input.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) End of Idle State Begin SCK Edge Number 1 2 3 4 End Transfer 5 6 7 8 9 10 11 12 13 14 Begin of Idle State 15 16 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL tI tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MS
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0).
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 16-9). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.6 Error Conditions The SPI has one error condition: • Mode fault error 16.4.6.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.7.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry.
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Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.4.7.4 Reset The reset values of registers and signals are described in Section 16.3, “Memory Map and Register Definition”, which details the registers and their bit fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. 16.4.7.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.1 Introduction Module VREG_3V3 is a dual output voltage regulator that provides two separate 2.5V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3V up to 5V (typical). 17.1.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.1.3 Block Diagram Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.2 External Signal Description Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 17-1 shows all signals of VREG_3V3 associated with pins. Table 17-1.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator. 17.2.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their individual bits. 17.3.2.1 HT Control Register (VREGHTCL) The VREGHTCL is reserved for test purposes. This register should not be written. Module Base + 0x_00 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 17-2. HT Control Register (VREGHTCL) 17.3.2.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt features. Module Base + 0x_02 7 R W Reset APICLK 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 APIFE APIE APIF 0 0 0 = Unimplemented or Reserved Figure 17-4. Autonomous Periodical Interrupt Control Register (VREGAPICL) Table 17-4.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR) The VREGAPITR register allows to trim the API timeout period. Module Base + 0x_03 R W Reset 7 6 5 4 3 2 APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 01 01 01 01 01 01 1 0 0 0 0 0 1. Reset value is either 0 or preset by factory. See Device User Guide for details. = Unimplemented or Reserved Figure 17-5.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous periodical interrupt rate. Module Base + 0x_04 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 APIR11 APIR10 APIR9 APIR8 0 0 0 0 = Unimplemented or Reserved Figure 17-6.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) Table 17-8. Selectable Autonomous Periodical Interrupt Periods 1 APICLK APIR[11:0] Selected Period 0 000 0.2 ms1 0 001 0.4 ms1 0 002 0.6 ms1 0 003 0.8 ms1 0 004 1.0 ms1 0 005 1.2 ms1 0 ..... ..... 0 FFD 818.8 ms1 0 FFE 819 ms1 0 FFF 819.2 ms1 1 000 2 * bus clock period 1 001 4 * bus clock period 1 002 6 * bus clock period 1 003 8 * bus clock period 1 004 10 * bus clock period 1 005 12 * bus clock period 1 ....
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.3.2.6 Reserved_06 The Reserved_06 is reserved for test purposes. Module Base + 0x_06 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 17-8. Reserved_06 17.3.2.7 Reserved_07 The Reserved_07 is reserved for test purposes. Module Base + 0x_07 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 17-9. Reserved_07 17.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.4.2.2 Reduced Power Mode In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption. 17.4.3 Low-Voltage Detect (LVD) Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA–VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 17-6 for the trimming effect of APITR. NOTE The first period after enabling the counter by APIFE might be reduced. The API internal RC oscillator clock is not available if VREG_3V3 is in Shutdown Mode. 17.4.8 Resets This section describes how VREG_3V3 controls the reset of the MCU.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) Table 17-10. Interrupt Vectors Interrupt Source Local Enable Autonomous periodical interrupt (API) APIE = 1 17.4.10.1 Low-Voltage Interrupt (LVI) In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID.
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Chapter 17 Voltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.1 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 18-1 for a simplified block diagram. 18.1.1 Features The MC9S12XDP512 includes these features: • Four timers implemented as modulus down-counters with independent time-out periods. • Time-out periods selectable between 1 and 224 bus clock cycles.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.1.3 Block Diagram Figure 18-1 shows a block diagram of the PIT. Bus Clock 8-Bit Micro Timer 0 Micro Time Base 0 16-Bit Timer 0 16-Bit Timer 1 8-Bit Micro Timer 1 Micro Time Base 1 16-Bit Timer 2 16-Bit Timer 3 Time-Out 0 Time-Out 1 Time-Out 2 Time-Out 3 Interrupt 0 Interface Trigger 0 Interrupt 1 Interface Trigger 1 Interrupt 2 Interface Trigger 2 Interrupt 3 Interface Trigger 3 Figure 18-1. MC9S12XDP512 Block Diagram 18.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the PIT. 18.3.1 Module Memory Map The memory map for the MC9S12XDP512 is given below in Table 1-1. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x000E R PITCNT1 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 R 0x000F PITCNT1 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0010 PITLD2 (High) W PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 0x0011 PITLD2 (Low) W PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x0012 R PITCNT2 (High) W PCNT15 PCNT14
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) Module Base + 0x0000 7 R W Reset 6 5 PITE PITSWAI PITFRZ 0 0 0 4 3 2 1 0 0 0 0 0 0 PFLMT1 PFLMT0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 18-2.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.2 PIT Force Load Timer Register (PITFLT) Module Base + 0x0001 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PFLT3 PFLT2 PFLT1 PFLT0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 18-4. PIT Force Load Timer Register (PITFLT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 18-3.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.4 PIT Multiplex Register (PITMUX) Module Base + 0x0003 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PMUX3 PMUX2 PMUX1 PMUX0 0 0 0 0 = Unimplemented or Reserved Figure 18-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 18-5.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.6 PIT Time-Out Flag Register (PITTF) Module Base + 0x0005 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTF3 PTF2 PTF1 PTF0 0 0 0 0 = Unimplemented or Reserved Figure 18-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear); writes to the reserved bits have no effect Table 18-7.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) Table 18-8. PITMTLD0–1 Field Descriptions Field Description 7:0 PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers. PMTLD[7:0] Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down to zero, the PMTLD register value will be loaded.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.8 PIT Load Register 0 to 3 (PITLD0–3) Module Base + 0x0008, 0x0009 15 R W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 18-11.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.3.2.9 PIT Count Register 0 to 3 (PITCNT0–3) Module Base + 0x000A, 0x000B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 15 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 18-15.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.4 Functional Description Figure 18-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as shown in Figure 18-20. The time-out period is a function of the timer load (PITLD) and micro timer load (PITMTLD) registers and the bus clock fBUS: time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit. NOTE Be careful when resetting the PITE, PINTE or PITCE bits in case of pending PIT interrupt requests, to avoid spurious interrupt requests. 18.4.
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin.
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Chapter 19 Background Debug Module (S12XBDMV2) • • • • • • • • Software control of BDM operation during wait mode Software selectable clocks Global page access functionality Enabled but not active out of reset in emulation modes CLKSW bit set out of reset in emulation mode. When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash and EEPROM erase tests fail.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.1.2.3 Low-Power Modes The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter a low power mode during BDM active mode.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.2 External Signal Description A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. 19.3 19.3.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.3.2 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 19-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.3.2.
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Chapter 19 Background Debug Module (S12XBDMV2) Table 19-2. BDMSTS Field Descriptions (continued) Field Description 6 BDMACT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map.
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Chapter 19 Background Debug Module (S12XBDMV2) Table 19-3. BDM Clock Sources PLLSEL CLKSW 0 0 Bus clock dependent on oscillator 0 1 Bus clock dependent on oscillator 1 0 Alternate clock (refer to the device specification to determine the alternate clock source) 1 1 Bus clock dependent on the PLL 19.3.2.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH) Register Global Address 0x7FFF07 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 CCR10 CCR9 CCR8 0 0 0 = Unimplemented or Reserved Figure 19-5.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 19.4.3, “BDM Hardware Commands”. Target system memory includes all memory that is accessible by the CPU.
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Chapter 19 Background Debug Module (S12XBDMV2) After being enabled, BDM is activated by one of the following1: • Hardware BACKGROUND command • CPU BGND instruction • External instruction tagging mechanism2 • Breakpoint force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table.
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Chapter 19 Background Debug Module (S12XBDMV2) Table 19-5. Hardware Commands Opcode (hex) Data BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.
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Chapter 19 Background Debug Module (S12XBDMV2) Table 19-6. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT2 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB.
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Chapter 19 Background Debug Module (S12XBDMV2) The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 19.3.2.1, “BDM Status Register (BDMSTS)”.
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Chapter 19 Background Debug Module (S12XBDMV2) BDM Clock (Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time Target Senses Bit Earliest Start of Next Bit 10 Cycles Synchronization Uncertainty Figure 19-8. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 19-9 shows the host receiving a logic 1 from the target system.
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Chapter 19 Background Debug Module (S12XBDMV2) Figure 19-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it.
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Chapter 19 Background Debug Module (S12XBDMV2) compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
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Chapter 19 Background Debug Module (S12XBDMV2) Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 19-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
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Chapter 19 Background Debug Module (S12XBDMV2) GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin.
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Chapter 19 Background Debug Module (S12XBDMV2) Figure 19-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command.
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Chapter 19 Background Debug Module (S12XBDMV2) The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued.
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Chapter 19 Background Debug Module (S12XBDMV2) within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication.
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Chapter 19 Background Debug Module (S12XBDMV2) 19.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse.
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Chapter 19 Background Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 20 Debug (S12XDBGV2) 20.1 Introduction The DBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The DBG module is optimized for the HCS12X 16-bit architecture and allows debugging of both CPU and XGATE module operations. Typically the DBG module is used in conjunction with the BDM module, whereby the user configures the DBG module for a debugging session over the BDM interface.
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Chapter 20 Debug (S12XDBGV2) 20.1.
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Chapter 20 Debug (S12XDBGV2) XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG module armed, the DBG remains armed. The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if the MCU is secure. Table 20-1.
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Chapter 20 Debug (S12XDBGV2) . Table 20-2. External System Pins Associated With DBG Pin Name Pin Functions Description TAGHI (See DUG) TAGHI When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. TAGLO (See DUG) TAGLO When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 20 Debug (S12XDBGV2) 20.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 20-2. Detailed descriptions of the registers and bits are given in the subsections that follow. 20.3.1 Register Descriptions This section consists of the DBG control and trace buffer register descriptions in address order.
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Chapter 20 Debug (S12XDBGV2) Address Register Name 0x0029 DBGXAH Bit 7 6 5 4 3 2 1 Bit 0 Bit 22 21 20 19 18 17 Bit 16 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 R 0 W 0x002A DBGXAM R W 0x002B DBGXAL R W 0x002C DBGXDH R W 0x002D DBGXDL R W 0x002E DBGXDHM R W 0x002F DBGXDLM R W = Unimplemented or Reserved
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Chapter 20 Debug (S12XDBGV2) Table 20-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the DBG module registers that can be written are ARM and TRIG.
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Chapter 20 Debug (S12XDBGV2) Table 20-5. COMRV Encoding 20.3.1.2 COMRV Visible Comparator Visible State Control Register 01 Comparator B DBGSCR2 10 Comparator C DBGSCR3 11 Comparator D DBGSCR3 Debug Status Register (DBGSR) 0x0021 7 6 5 4 3 2 1 0 TBF EXTF 0 0 0 SSF2 SSF1 SSF0 Reset — 0 0 0 0 0 0 0 POR 0 0 0 0 0 0 0 0 R W Unimplemented or Reserved Figure 20-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 20-6.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.3 Debug Trace Control Register (DBGTCR) 0x0022 7 R 5 TSOURCE W Reset 6 0 4 3 TRANGE 0 0 2 1 TRCMOD 0 0 0 TALIGN 0 0 0 Figure 20-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when DBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Table 20-8. DBGTCR Field Descriptions Field Description 7–6 TSOURCE Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session.
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Chapter 20 Debug (S12XDBGV2) Table 20-10. TRANGE Trace Range Encoding TRANGE Tracing Source 11 Trace only in range from comparator C to comparator D Table 20-11. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 NORMAL 01 LOOP1 10 DETAIL 11 Reserved Table 20-12. TALIGN Trace Alignment Encoding 20.3.1.
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Chapter 20 Debug (S12XDBGV2) Table 20-14. CDCM Encoding CDCM Description 00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match. 01 Match2 mapped to comparator C/D inside range....... Match3 disabled. 10 Match2 mapped to comparator C/D outside range....... Match3 disabled. 11 Reserved Table 20-15. ABCM Encoding 20.3.1.5 ABCM Description 00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.6 Debug Count Register (DBGCNT) 0x0026 7 R 6 5 4 0 3 2 1 0 CNT W Reset 0 POR 0 — — — — — — — 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20-9. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 20-17. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.7 Debug State Control Registers Each of the state sequencer states 1 to 3 features a dedicated control register to determine if transitions from that state are allowed depending upon comparator matches or tag hits and to define the next state for the state sequencer following a match. The 3 debug state control registers are located at the same address in the register address map (0x0027).
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Chapter 20 Debug (S12XDBGV2) Table 20-21. State1 Sequencer Next Sate Selection SC[3:0] Description 0000 Any match triggers to state2 0001 Any match triggers to state3 0010 Any match triggers to final state 0011 Match2 triggers to State2....... Other matches have no effect 0100 Match2 triggers to State3....... Other matches have no effect 0101 Match2 triggers to final state....... Other matches have no effect 0110 Match0 triggers to State2....... Match1 triggers to State3.......
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Chapter 20 Debug (S12XDBGV2) Table 20-22. DBGSCR2 Field Descriptions Field 3–0 SC[3:0} Description State Control Bits — These bits select the targeted next state while in State2, based upon the match event. See Table 20-23. The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches. Table 20-23.
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Chapter 20 Debug (S12XDBGV2) (DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 20-24. DBGSCR3 Field Descriptions Field Description 3–0 SC[3:0] State Control Bits — These bits select the targeted next state while in State3, based upon the match event. The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority.
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Chapter 20 Debug (S12XDBGV2) Table 20-26. Comparator Register Layout 0x0029 ADDRESS HIGH Read/Write 0x002A ADDRESS MEDIUM Read/Write 0x002B ADDRESS LOW Read/Write 0x002C DATA HIGH COMPARATOR Read/Write Comparator A and C only 0x002D DATA LOW COMPARATOR Read/Write Comparator A and C only 0x002E DATA HIGH MASK Read/Write Comparator A and C only 0x002F DATA LOW MASK Read/Write Comparator A and C only 20.3.1.11.
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Chapter 20 Debug (S12XDBGV2) Table 20-27. DBGXCTL Field Descriptions (continued) Field Description 6 Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the (COMP B/D) associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.11.2 Debug Comparator Address High Register (DBGXAH) 0x0029 7 R 0 W Reset 0 6 5 4 3 2 1 0 Bit 22 21 20 19 18 17 Bit 16 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20-15. Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when DBG not armed. Table 20-29.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.11.4 Debug Comparator Address Low Register (DBGXAL) 0x002B R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-17. Debug Comparator Address Low Register (DBGXAL) Read: Anytime Write: Anytime when DBG not armed. Table 20-31.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.11.6 Debug Comparator Data Low Register (DBGXDL) 0x002D R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-19. Debug Comparator Data Low Register (DBGXDL) Read: Anytime Write: Anytime when DBG not armed. Table 20-33.
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Chapter 20 Debug (S12XDBGV2) 20.3.1.11.8 Debug Comparator Data Low Mask Register (DBGXDLM) 0x002F R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-21. Debug Comparator Data Low Mask Register (DBGXDLM) Read: Anytime Write: Anytime when DBG not armed. Table 20-35.
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Chapter 20 Debug (S12XDBGV2) TAGS TAGHITS EXTERNAL TAGHI / TAGLO BREAKPOINT REQUESTS CPU & XGATE XGATE BUS COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE XGATE S/W BREAKPOINT REQUEST SECURE MATCH0 MATCH1 MATCH2 TAG & TRIGGER TRIGGER CONTROL LOGIC STATE STATE SEQUENCER MATCH3 TRACE CONTROL TRIGGER READ TRACE DATA (DBG READ DATA BUS) TRACE BUFFER Figure 20-22. DBG Overview 20.4.
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Chapter 20 Debug (S12XDBGV2) If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining.
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Chapter 20 Debug (S12XDBGV2) 20.4.2.2 Exact Address Comparator Match (Comparators B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match.
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Chapter 20 Debug (S12XDBGV2) 20.4.2.3.2 Outside Range (Address < CompAC_Addr or Address > CompBD_Addr) In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range.
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Chapter 20 Debug (S12XDBGV2) 20.4.3.4 Trigger On XGATE S/W Breakpoint Request The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU immediately independent of DBG settings. If the debug module is armed triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun using begintrigger, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits.
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Chapter 20 Debug (S12XDBGV2) 20.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 State2 ARM = 0 Session complete (disarm) Final State State3 ARM=0 Figure 20-23. State Sequencer Diagram The state sequence control allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then State1 of the state sequencer is entered.
PAGE 819
Chapter 20 Debug (S12XDBGV2) 20.4.4.1 Final State On entering final state a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 20.3.1.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request.
PAGE 820
Chapter 20 Debug (S12XDBGV2) is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 20.4.5.1.3 Storing with End-Trigger Storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the DBG module will become disarmed and no more data will be stored.
PAGE 821
Chapter 20 Debug (S12XDBGV2) Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated.
PAGE 822
Chapter 20 Debug (S12XDBGV2) information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the DBGCNT[0] is incremented after each separate entry. In all other modes, DBGCNT[0] remains cleared while the other DBGCNT bits are incremented on each trace buffer entry.
PAGE 823
Chapter 20 Debug (S12XDBGV2) 20.4.5.3.1 Information Byte Organization The format of the control information byte for both CPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In normal mode or loop1 mode, tracing of XGATE activity XINF is used to store control information. In normal mode or loop1 mode, tracing of CPU activity CINF is used to store control information. In detail mode, CXINF contains the control information.
PAGE 824
Chapter 20 Debug (S12XDBGV2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CFREE CSZ CRW COCF XACK XSZ XRW XOCF Figure 20-26. Information Byte CXINF This describes the format of the information byte used only when tracing from CPU or XGATE in detail mode. When tracing from the CPU in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter.
PAGE 825
Chapter 20 Debug (S12XDBGV2) Table 20-42. CXINF Field Descriptions (continued) Field Description 1 XRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in detail mode. 0 Read/Write Access 1 Access 0 XOCF XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.
PAGE 826
Chapter 20 Debug (S12XDBGV2) 20.4.5.3.3 Trace Buffer Reset State The trace buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT.
PAGE 827
Chapter 20 Debug (S12XDBGV2) 20.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into State0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other.
PAGE 828
Chapter 20 Debug (S12XDBGV2) 20.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If an end aligned trigger is selected or no tracing is enabled, breakpoints can be generated immediately, depending on the state of the DBGBRK[n] bits.
PAGE 829
Chapter 20 Debug (S12XDBGV2) 20.4.7.5 DBG Breakpoint Priorities XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG triggers occur after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs.
PAGE 830
Chapter 20 Debug (S12XDBGV2) When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. Thus care must be taken to avoid re triggering a breakpoint at the same location.
PAGE 831
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 832
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 833
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 834
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 835
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 836
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 837
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 838
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 839
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 840
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 841
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 842
Chapter 20 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 843
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1 Introduction The XINT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the CPU or the XGATE module.
PAGE 844
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1.1 Glossary The following terms and abbreviations are used in the document. Table 21-1. Terminology Term CCR DMA INT IPL ISR MCU XGATE IRQ XIRQ 21.1.
PAGE 845
Chapter 21 Interrupt (S12MC9S12XDP512V1) • • • Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 21.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 21.5.
PAGE 846
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1.4 Block Diagram Figure 21-1 shows a block diagram of the XINT module.
PAGE 847
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.2 External Signal Description The XINT module has no external signals. 21.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XINT. MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 848
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.3.1 Register Descriptions This section describes in address order all the XINT registers and their individual bits.
PAGE 849
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.3.1.1 Interrupt Vector Base Register (IVBR) Address: 0x0121 7 6 5 R 3 2 1 0 1 1 1 IVB_ADDR[7:0] W Reset 4 1 1 1 1 1 Figure 21-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 21-2. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e.
PAGE 850
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.3.1.2 XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Address: 0x0126 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 2 0 0 XILVL[2:0] W Reset 1 0 0 1 = Unimplemented or Reserved Figure 21-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Read: Anytime Write: Anytime Table 21-3.
PAGE 851
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.3.1.3 Interrupt Request Configuration Address Register (INT_CFADDR) Address: 0x0127 7 6 R 4 INT_CFADDR[7:4] W Reset 5 0 0 0 1 3 2 1 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 21-5. Interrupt Configuration Address Register (INT_CFADDR) Read: Anytime Write: Anytime Table 21-5.
PAGE 852
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.3.1.4 Interrupt Request Configuration Data Registers (INT_CFDATA0–7) The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order.
PAGE 853
Chapter 21 Interrupt (S12MC9S12XDP512V1) Address: 0x012C 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 11 = Unimplemented or Reserved Figure 21-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012D 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 11 = Unimplemented or Reserved Figure 21-11.
PAGE 854
Chapter 21 Interrupt (S12MC9S12XDP512V1) Table 21-6. INT_CFDATA0–7 Field Descriptions Field Description 7 RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module.
PAGE 855
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.4 Functional Description The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. 21.4.1 S12X Exception Requests The CPU handles both reset requests and interrupt requests.
PAGE 856
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.4.2.1 Interrupt Priority Stack The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched.
PAGE 857
Chapter 21 Interrupt (S12MC9S12XDP512V1) If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector.
PAGE 858
Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.5 21.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module).
PAGE 859
Chapter 21 Interrupt (S12MC9S12XDP512V1) 0 Stacked IPL IPL in CCR 0 0 4 0 0 0 4 7 4 3 1 0 7 6 RTI L7 5 4 RTI Processing Levels 3 L3 (Pending) 2 L4 RTI 1 L1 (Pending) 0 RTI Reset Figure 21-14. Interrupt Processing Example 21.5.3 21.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode.
PAGE 860
Chapter 21 Interrupt (S12MC9S12XDP512V1) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 861
Chapter 22 External Bus Interface (S12XEBIV2) 22.1 Introduction This document describes the functionality of the MC9S12XDP512 block controlling the external bus interface. The MC9S12XDP512 controls the functionality of a non-multiplexed external bus (a.k.a. ‘expansion bus’) in relationship with the chip operation modes.
PAGE 862
Chapter 22 External Bus Interface (S12XEBIV2) 22.1.3 Block Diagram Figure 22-1 is a block diagram of the MC9S12XDP512 with all related I/O signals. ADDR[22:0] DATA[15:0] IVD[15:0] LSTRB R/W EWAIT XEBI UDS LDS RE WE ACC[2:0] IQSTAT[3:0] Figure 22-1. MC9S12XDP512 Block Diagram 22.2 External Signal Description The user is advised to refer to the SoC section for port configuration and location of external bus signals.
PAGE 863
Chapter 22 External Bus Interface (S12XEBIV2) Table 22-1.
PAGE 864
Chapter 22 External Bus Interface (S12XEBIV2) 22.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MC9S12XDP512. 22.3.1 Module Memory Map The registers associated with the MC9S12XDP512 block are shown in Figure 22-2. Register Name 0x0E EBICTL0 0x0F EBICTL1 Bit 7 R W R W ITHRS EWAITE 6 0 5 4 3 2 1 Bit 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 0 0 0 EXSTR2 EXSTR1 EXSTR0 0 = Unimplemented or Reserved Figure 22-2.
PAGE 865
Chapter 22 External Bus Interface (S12XEBIV2) 22.3.2.1 External Bus Interface Control Register 0 (EBICTL0) Module Base +0x000E (PRR) 7 R W Reset 6 0 ITHRS 0 0 5 4 3 2 1 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 1 1 1 1 1 1 = Unimplemented or Reserved Figure 22-3. External Bus Interface Control Register 0 (EBICTL0) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes, the data are read from this register. Write: Anytime.
PAGE 866
Chapter 22 External Bus Interface (S12XEBIV2) Table 22-3. Input Threshold Levels on External Signals ITHRS External Signal NS SS NX Standard Standard Standard DATA[15:8] TAGHI, TAGLO 0 DATA[7:0] EWAIT DATA[15:8] TAGHI, TAGLO 1 Reduced if HDBE = 1 DATA[7:0] Standard Standard EX ST Reduced Reduced Standard Standard Reduced Reduced Reduced Standard Reduced if EWAITE = 1 Standard Standard Reduced Reduced if EWAITE = 1 EWAIT ES Table 22-4.
PAGE 867
Chapter 22 External Bus Interface (S12XEBIV2) 22.3.2.2 External Bus Interface Control Register 1 (EBICTL1) Module Base +0x000F (PRR) 7 R W EWAITE Reset 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 EXSTR2 EXSTR1 EXSTR0 1 1 1 = Unimplemented or Reserved Figure 22-4. External Bus Interface Control Register 1 (EBICTL1) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 868
Chapter 22 External Bus Interface (S12XEBIV2) 22.4 Functional Description This section describes the functions of the external bus interface. The availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in separate sub-sections. 22.4.1 Operating Modes and External Bus Properties A summary of the external bus interface functions for each operating mode is shown in Table 22-7. Table 22-7.
PAGE 869
Chapter 22 External Bus Interface (S12XEBIV2) 22.4.2 Internal Visibility Internal visibility allows the observation of the internal MCU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface. Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal CPU and BDM accesses are made visible on the external bus interface, except those to BDM firmware and BDM registers.
PAGE 870
Chapter 22 External Bus Interface (S12XEBIV2) The following terminology is used: ‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins ‘x’ — Undefined output pin values ‘z’ — Tristate pins ‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’ 22.4.2.2.1 Read Access Timing Table 22-9. Read Access (1 Cycle) Access #0 Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ...
PAGE 871
Chapter 22 External Bus Interface (S12XEBIV2) 22.4.2.2.2 Write Access Timing Table 22-12. Write Access (1 Cycle) Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... Access #0 Access #1 Access #2 1 2 3 high low addr 0 iqstat -1 high low addr 1 iqstat 0 ? ADDR[15:0] / IVD[15:0] ... DATA[15:0] (write) ... ? R/W ... 0 high low ... acc 2 ... addr 2 iqstat 1 ... x ... data 2 ... 1 ... acc 1 acc 0 x data 0 data 1 0 1 ...
PAGE 872
Chapter 22 External Bus Interface (S12XEBIV2) 22.4.2.2.3 Read-Write-Read Access Timing Table 22-15. Interleaved Read-Write-Read Accesses (1 Cycle) Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... Access #0 Access #1 Access #2 1 2 3 high low addr 0 iqstat -1 low addr 1 iqstat 0 acc 0 ... DATA[15:0] (internal read) ... ? DATA[15:0] (external read) ... R/W ... high low ... acc 2 ... addr 2 iqstat 1 ... x ... z ...
PAGE 873
Chapter 22 External Bus Interface (S12XEBIV2) Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fixed amount of stretch cycles 2. Activation of the external wait feature by EWAITE in EBICTL1 register 3. Assertion of the external EWAIT signal when EWAITE = 1 The EXSTR[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2.
PAGE 874
Chapter 22 External Bus Interface (S12XEBIV2) Table 22-17.
PAGE 875
Chapter 22 External Bus Interface (S12XEBIV2) 22.4.6 Low-Power Options The MC9S12XDP512 does not support any user-controlled options for reducing power consumption. 22.4.6.1 Run Mode The MC9S12XDP512 does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface.
PAGE 876
Chapter 22 External Bus Interface (S12XEBIV2) 22.5.1 Normal Expanded Mode This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access. 22.5.1.
PAGE 877
Chapter 22 External Bus Interface (S12XEBIV2) 22.5.2 Emulation Modes In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are directed to the external bus in emulation modes which are substituted by PRR as part of the PRU.
PAGE 878
Chapter 22 External Bus Interface (S12XEBIV2) 22.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 22-5 shows the PRU connection with the available external bus signals in an emulator application. S12X_EBI Emulator ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM PRU PRR Ports LSTRB R/W ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] ECLK ECLKX2 Figure 22-5.
PAGE 879
Chapter 22 External Bus Interface (S12XEBIV2) 22.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals UDS, LDS, RE, and WE from the ADDR0, LSTRB, and R/W signals. Figure 22-6 shows the PRU connection with the available external bus signals in an emulator application.
PAGE 880
Chapter 22 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 881
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 1-1. The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses including internal memories and peripherals are controlled in this module.
PAGE 882
Chapter 23 Memory Mapping Control (S12XMMCV2) • Wait mode MMC is functional during wait mode. Stop mode MMC is inactive during stop mode. • 23.1.2.2 • Functional Modes Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus.
PAGE 883
Chapter 23 Memory Mapping Control (S12XMMCV2) Table 1-2 and Table 1-3 outline the pin names and functions. It also provides a brief description of their operation. Table 23-1. External Input Signals Associated with the MMC Signal I/O Description Availability MODC I Mode input MODB I Mode input Latched after RESET (active low) MODA I Mode input EROMCTL I EROM control input ROMCTL I ROM control input Table 23-2.
PAGE 884
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3 23.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 1-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
PAGE 885
Chapter 23 Memory Mapping Control (S12XMMCV2) Address Register Name 0x011C RAMWPC Bit 7 R RAMXGU R 1 W 0x011E RAMSHL R 1 W 0x011F RAMSHU 5 4 3 2 0 0 0 0 0 XGU6 XGU5 XGU4 XGU3 SHL6 SHL5 SHL4 SHU6 SHU5 SHU4 RPWE W 0x011D 6 R 1 W 1 Bit 0 AVIE AVIF XGU2 XGU1 XGU0 SHL3 SHL2 SHL1 SHL0 SHU3 SHU2 SHU1 SHU0 = Unimplemented or Reserved Figure 23-2. MMC Register Summary 23.3.2 23.3.2.
PAGE 886
Chapter 23 Memory Mapping Control (S12XMMCV2) The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Table 23-4.
PAGE 887
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.2 Mode Register (MODE) Address: 0x000B PRR 7 R W Reset 6 5 MODC MODB MODA MODC1 MODB1 MODA1 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 1-2). = Unimplemented or Reserved Figure 23-4. Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register.
PAGE 888
Chapter 23 Memory Mapping Control (S12XMMCV2) RESET 010 Special Test (ST) 010 1 1 10 0 10 Normal Expanded (NX) 101 Emulation Single-Chip (ES) 001 Emulation Expanded (EX) 011 101 10 1 011 RESET 0 10 RESET RESET 000 001 101 101 010 110 111 Normal Single-Chip (NS) 100 1 00 01 RESET 100 1 01 1 00 Special Single-Chip (SS) 000 000 RESET Transition done by external pins (MODC, MODB, MODA) RESET Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, M
PAGE 889
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.3 Global Page Index Register (GPAGE) Address: 0x0010 7 R 0 W Reset 0 6 5 4 3 2 1 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 23-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used only when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide).
PAGE 890
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.4 Direct Page Register (DIRECT) Address: 0x0011 R W Reset 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Figure 23-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the direct page within the memory map. Table 23-8.
PAGE 891
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.5 MMC Control Register (MMCCTL1) Address: 0x0013 PRR R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 EROMON ROMHM ROMON EROMCTL 0 ROMCTL = Unimplemented or Reserved Figure 23-10. MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other modes the data are read from this register. Write: Refer to each bit description.
PAGE 892
Chapter 23 Memory Mapping Control (S12XMMCV2) Table 23-10.
PAGE 893
Chapter 23 Memory Mapping Control (S12XMMCV2) Global Address [22:0] 0 0 0 Bit19 Bit18 Bit12 Bit11 Bit0 Address [11:0] RPAGE Register [7:0] Address: CPU Local Address or BDM Local Address Figure 23-12. RPAGE Address Mapping NOTE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RPAGE = $00. Table 23-11.
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Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.7 EEPROM Page Index Register (EPAGE) Address: 0x0017 R W 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 1 1 1 1 1 1 1 0 Reset Figure 23-13.
PAGE 895
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.8 Program Page Index Register (PPAGE) Address: 0x0030 R W Reset 7 6 5 4 3 2 1 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 1 1 1 1 1 1 1 0 Figure 23-15.
PAGE 896
Chapter 23 Memory Mapping Control (S12XMMCV2) Table 23-13. PPAGE Field Descriptions Field 7–0 PIX[7:0] Description Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM array pages is to be accessed in the Program Page Window. The fixed 16K page from $4000–$7FFF (when ROMHM = 0) is the page number $FD. The reset value of $FE ensures that there is linear Flash space available between addresses $4000 and $FFFF out of reset.
PAGE 897
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU) Address: 0x011D 7 R 1 W Reset 1 6 5 4 3 2 1 0 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 23-18. RAM XGATE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when RWPE = 0 Table 23-15.
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Chapter 23 Memory Mapping Control (S12XMMCV2) 23.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU) Address: 0x011F 7 R 1 W Reset 1 6 5 4 3 2 1 0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 23-20. RAM Shared Region Upper Boundary Register (RAMSHU) Read: Anytime Write: Anytime when RWPE = 0 Table 23-17.
PAGE 899
Chapter 23 Memory Mapping Control (S12XMMCV2) • • • Normal expanded mode The external bus interface is configured as an up to 23-bit address bus, 8 or 16-bit data bus with dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by the external logic.
PAGE 900
Chapter 23 Memory Mapping Control (S12XMMCV2) CPU or BDM Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 $00_1000 $0000 RAM 253*4K paged 2K Registers $0800 EEPROM 1K window EPAGE 1M minus Kbytes 2K RAM $0F_E000 8K RAM $0C00 1K EEPROM $10_0000 RAM 4K window EEPROM 255*1K paged RPAGE $2000 $13_FC00 256 Kbytes $1000 1K EEPROM 8K RAM $14_4000 $4000 ROMHM=1 $14_8000 Unpaged Flash External Space No 2.
PAGE 901
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page window located from address $8000 to address $BFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register.
PAGE 902
Chapter 23 Memory Mapping Control (S12XMMCV2) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. 23.4.2.
PAGE 903
Chapter 23 Memory Mapping Control (S12XMMCV2) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] CPU Local Address Figure 23-22. BDMGPR Address Mapping 23.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, EEPROM, and FLASH) are not determined by the MMC module.
PAGE 904
Chapter 23 Memory Mapping Control (S12XMMCV2) When the device is operating in expanded modes except emulation single-chip mode, accesses to the global addresses which are not occupied by the on-chip resources (unimplemented areas or external space) result in accesses to the external bus (see Figure 1-23). In emulation single-chip mode, accesses to the global addresses which are not occupied by the on-chip resources (unimplemented areas) result in accesses to the external bus.
PAGE 905
Chapter 23 Memory Mapping Control (S12XMMCV2) CPU and BDM Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 CS3 Unimplemented RAM 2K Registers RAM $0800 EEPROM 1K window EPAGE RAMSIZE $0000 $0F_FFFF $0C00 $2000 EEPROM $13_FFFF 8K RAM $1F_FFFF CS1 External Space $4000 CS2 RPAGE EEPROMSIZE Unimplemented EEPROM $1000 RAM 4K window CS2 1K EEPROM Unpaged Flash $40_0000 Flash 16K window CS0 $8000 Unimplemented FLASH PPAGE $C000 $FFFF Reset Vectors FLASH FLASHSIZE
PAGE 906
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.4.2.4 XGATE Memory Map Scheme 23.4.2.4.1 Expansion of the XGATE Local Address Map The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the BDM module (see Table 1-22). XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes, XGATE can not access the FLASH when MCU is secured.
PAGE 907
Chapter 23 Memory Mapping Control (S12XMMCV2) XGATE Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 $0800 RAM $0F_FFFF XGRAMSIZE 2K Registers RAMSIZE $0000 RAM $FFFF FLASH FLASHSIZE 2K XGRAMSIZE FLASH $7F_FFFF Figure 23-24. Local to Global Address Mapping (XGATE) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 908
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.4.3 23.4.3.1 Chip Access Restrictions Illegal XGATE Accesses A possible access error is flagged by the MMC and signalled to XGATE under the following conditions: • XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses). • XGATE accesses the register space (in case of opcode or vector fetch). • XGATE performs a write to Flash in any modes (in case of load-store access).
PAGE 909
Chapter 23 Memory Mapping Control (S12XMMCV2) The following conditions must be satisfied to ensure correct operation of the RAM protection mechanism: • Value stored in RAMXGU must be lower than the value stored in RAMSHL. • Value stored RAMSHL must be lower or equal than the value stored in RAMSHU. Table 23-22.
PAGE 910
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.4.4 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal and external resources are connected to specific target buses (see Figure 1-26).
PAGE 911
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.4.4.2 Access Conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: • CPU always has priority over XGATE. • BDM access has priority over XGATE. • XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU and BDM for its duration.
PAGE 912
Chapter 23 Memory Mapping Control (S12XMMCV2) This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction can be performed from any address to any other address in the local CPU memory space. The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction.
PAGE 913
Chapter 23 Memory Mapping Control (S12XMMCV2) Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. A summary of PRR accesses is the following: • An aligned word access to a PRR will take 2 bus cycles. • A misaligned word access to a PRRs will take 4 cycles.
PAGE 914
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.5.3 On-Chip ROM Control The MCU offers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called observer) the internal FLASH provides the data and all internal actions are made visible to the emulator. 23.5.3.1 ROM Control in Single-Chip Modes In single-chip modes the MCU has no external bus.
PAGE 915
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.5.3.3 ROM Control in Normal Expanded Mode In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set, the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the data (see Figure 1-29). MCU Application Flash Memory ROMON = 1 MCU Application Memory ROMON = 0 Figure 23-29. ROM in Normal Expanded Mode MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 916
Chapter 23 Memory Mapping Control (S12XMMCV2) 23.5.3.4 ROM Control in Emulation Expanded Mode In emulation expanded mode the external bus will be connected to the emulator and to the application. If the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU actions (see Figure 1-30).
PAGE 917
Chapter 23 Memory Mapping Control (S12XMMCV2) Observer MCU Emulator Application Memory Figure 23-31. ROMON = 0 in Emulation Expanded Mode 23.5.3.5 ROM Control in Special Test Mode In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal FLASH provides the data, otherwise the application memory provides the data (see Figure 1-32). Application MCU Memory ROMON = 0 Application MCU Flash Memory ROMON = 1 Figure 23-32.
PAGE 918
Chapter 23 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 919
Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains the most accurate electrical information for the MC9S12XDP512 microcontroller available at the time of publication.
PAGE 920
Appendix A Electrical Characteristics VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD35 is used for either VDDA, VDDR, and VDDX; VSS35 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL.
PAGE 921
Appendix A Electrical Characteristics the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only.
PAGE 922
Appendix A Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification.
PAGE 923
Appendix A Electrical Characteristics A.1.7 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4.
PAGE 924
Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
PAGE 925
Appendix A Electrical Characteristics Table A-5. Thermal Package Characteristics1 Num C Rating Symbol Min Typ Max Unit LQFP144 1 T Thermal resistance LQFP144, single sided PCB2 θJA — — 41 °C/W 2 T Thermal resistance LQFP144, double sided PCB with 2 internal planes3 θJA — — 32 °C/W 3 Junction to Board LQFP 144 θJB — — 22 °C/W 4 Junction to Case LQFP 1444 θJC — — 7.
PAGE 926
Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL,XFC,TEST and supply pins. Table A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < VDD35 < 3.6 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST and supply pins. Num C Symbol Min Typ Max Unit P Input high voltage VIH 0.65*VDD35 — — V T Input high voltage VIH — — VDD35 + 0.
PAGE 927
Appendix A Electrical Characteristics Table A-7. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST and supply pins. Num C 1 Rating Symbol Min Typ Max Unit 0.65*VDD35 — — V P Input high voltage V T Input high voltage VIH — — VDD35 + 0.3 V P Input low voltage VIL — — 0.35*VDD35 V T Input low voltage VIL VSS35 – 0.
PAGE 928
Appendix A Electrical Characteristics Table A-8. I/O Characteristics for Port C, D, PE5, PE6, and PE7 for Reduced Input Voltage Thresholds Conditions are 4.5 V < VDD35 < 5.5 V Temperature from –40°C to +140°C, unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Input high voltage VIH 1.75 — — V 2 P Input low voltage VIL — — 0.75 V 3 C Input hysteresis VHYS — 100 — mV A.1.
PAGE 929
Appendix A Electrical Characteristics Table A-9. shows the configuration of the peripherals for run current measurement. Table A-9.
PAGE 930
Appendix A Electrical Characteristics A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. No generally applicable numbers can given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-10.
PAGE 931
Appendix A Electrical Characteristics Table A-11.
PAGE 932
Appendix A Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-12 and Table A-13 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to.
PAGE 933
Appendix A Electrical Characteristics Table A-13. ATD Operating Characteristics 3.3V Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 3.15V < VDDA < 3.6V Num C 1 2 D Reference potential Low High Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 — — VDDA/2 VDDA V V 2 C Differential reference voltage1 VRH-VRL 3.15 3.3 3.6 V 3 D ATD clock frequency fATDCLK 0.5 — 2.0 MHz 4 D ATD 10-bit conversion period Clock cycles2 Conv, time at 2.
PAGE 934
Appendix A Electrical Characteristics A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted.
PAGE 935
Appendix A Electrical Characteristics A.2.3 A.2.3.1 ATD Accuracy 5-V Range Table A-15 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance, and source resistance. Table A-15. 5-V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH–VRL = 5.12 V. Resulting to one 8-bit count = 20 mV and one 10-bit count = 5 mV fATDCLK = 2.
PAGE 936
Appendix A Electrical Characteristics A.2.3.3 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = --------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ V –V n 0 DNL ( i ) = --------------------- – n 1LSB i=1 MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 937
Appendix A Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 50 50555060506550705075508050855090509551005105511051155120 Vin mV Figure A-1.
PAGE 938
Appendix A Electrical Characteristics A.3 NVM, Flash, and EEPROM NOTE Unless otherwise noted the abbreviation NVM (nonvolatile memory) is used for both Flash and EEPROM. A.3.1 NVM Timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations.
PAGE 939
Appendix A Electrical Characteristics A.3.1.3 Sector Erase Erasing a 1024-byte Flash sector or a 4-byte EEPROM sector takes: t era 1 ≈ 4000 ⋅ ------------------------f NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: t mass 1 ≈ 20000 ⋅ ------------------------f NVMOP The setup time can be ignored for this operation. A.3.1.
PAGE 940
Appendix A Electrical Characteristics Table A-17. NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 6 7 Unit — 801 MHz 2 D Bus frequency for programming or erase operations fNVMBUS 1 — — MHz 3 D Operating frequency fNVMOP 150 — 200 tswpgm 2 P Single word programming time D Flash burst programming consecutive word 6 D Flash burst programming time for 64 words 7 P Sector erase time 10 5 Max 0.
PAGE 941
Appendix A Electrical Characteristics A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A-18.
PAGE 942
Appendix A Electrical Characteristics Figure A-2. Typical Endurance vs Temperature 500 Typical Endurance [103 Cycles] 450 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 140 Operating Temperature TJ [°C] ------ Flash ------ EEPROM MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 943
Appendix A Electrical Characteristics A.4 Voltage Regulator Table A-19. Voltage Regulator Electrical Characteristics Num C 1 P Input voltages 3 P Output voltage core Full performance mode Reduced power mode Shutdown mode VDD Output Voltage PLL Full Performance Mode Reduced power mode Shutdown mode VDDPLL 4 7 8 9 12 1 2 3 4 5 6 P P P C C Characteristic Low-voltage interrupt3 Assert level Deassert level Low-voltage reset4 Assert level Symbol Min Typ Max Unit VVDDR,A 3.15 — 5.
PAGE 944
Appendix A Electrical Characteristics A.5 Reset, Oscillator, and PLL This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL). A.5.1 Startup Table A-20 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide. Table A-20.
PAGE 945
Appendix A Electrical Characteristics If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will resume operation in self-clock mode after tfws. A.5.1.5 Pseudo Stop and Wait Recovery The recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. A.5.
PAGE 946
Appendix A Electrical Characteristics Table A-21. Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num 1a C Rating C Crystal oscillator range (loop controlled Pierce) 1, 2 Symbol Min Typ Max Unit fOSC 4.0 — 16 MHz 1b C Crystal oscillator range (full swing Pierce) fOSC 0.5 — 40 MHz 2 P Startup current iOSC 100 — — µA 504 ms 2.
PAGE 947
Appendix A Electrical Characteristics A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL Cs R XFC Pin Phase fosc fref 1 D refdv+1 VCO fvco KF fcmp KV Detector Loop Divider 1 synr+1 1 2 Figure A-3.
PAGE 948
Appendix A Electrical Characteristics f f 2⋅ζ⋅f ref ref 1 < ------------------------------------------- ⋅ ----- → f < ------------- ;( ζ = 0.9 ) C C 4 ⋅ 10 10 2 π ⋅ ⎛ζ + 1 + ζ ⎞ ⎝ ⎠ fC < 100kHz And finally the frequency relationship is defined as f VCO n = --------------- = 2 ⋅ ( synr + 1 ) f ref = 20 With the above values the resistance can be calculated.
PAGE 949
Appendix A Electrical Characteristics The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t (N) t (N) ⎞ ⎛ max min J ( N ) = max ⎜ 1 – ----------------------- , 1 – ----------------------- ⎟ N⋅t N⋅t ⎝ nom nom ⎠ For N < 1000, the following equation is a good fit for the maximum jitter: j 1 J ( N ) = -------- + j N 2 J(N) 1 5 10 20 N Figure A-5.
PAGE 950
Appendix A Electrical Characteristics Table A-22. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol Min Typ Max Unit 1 P Self clock mode frequency fSCM 1 — 5.5 MHz 2 D VCO locking range fVCO 8 — 80 MHz 3 D Lock detector transition from acquisition to tracking mode |∆trk| 3 — 4 %1 4 D Lock detection |∆Lock| 0 — 1.5 %1 5 D Unlock detection |∆unl| 0.5 — 2.
PAGE 951
Appendix A Electrical Characteristics A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted. SS1 (Output) 2 1 SCK (CPOL = 0) (Output) 12 13 12 13 3 4 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 6 Bit 6 . . . 1 MSB IN2 10 MOSI (Output) LSB IN 9 11 Bit 6 . . . 1 MSB OUT2 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6.
PAGE 952
Appendix A Electrical Characteristics In Table A-25 the timing characteristics for master mode are listed. Table A-25.
PAGE 953
Appendix A Electrical Characteristics In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. SS (Input) 3 1 2 12 13 12 13 SCK (CPOL = 0) (Input) 4 4 SCK (CPOL = 1) (Input) See Note 7 Slave MSB OUT 5 MOSI (Input) 8 11 9 MISO (Output) Bit 6 . . . 1 Slave LSB OUT 6 MSB IN Bit 6 . . . 1 LSB IN NOTE: Not defined Figure A-9. SPI Slave Timing (CPHA = 1) In Table A-26 the timing characteristics for slave mode are listed. Table A-26.
PAGE 954
Appendix A Electrical Characteristics A.8 External Bus Timing The following conditions are assumed for all following external bus timing values: • Crystal input within 45% to 55% duty • Equal loads of pins • Pad full drive (reduced drive must be off) A.8.1 Normal Expanded Mode (External Wait Feature Disabled) 1 1 CSx ADDRx ADDR1 2 ADDR2 3 RE 4 5 WE 8 6 7 10 DATAx (Read) DATA1 11 (Write) DATA2 9 EWAIT UDS, LDS Figure A-10.
PAGE 955
Appendix A Electrical Characteristics Table A-27. Example 1a: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 0) 1 No. C Characteristic — — Frequency of internal bus — — Internal cycle time — — Frequency of external bus 1 — External cycle time (selected by EXSTR) 1 Symbol Min Max Unit fi D.C. 40.0 MHz tcyc 25 ∞ ns fo D.C. 20.
PAGE 956
Appendix A Electrical Characteristics A.8.2 Normal Expanded Mode (External Wait Feature Enabled) 1 CSx ADDRx ADDR1 2 ADDR2 3 RE WE 8 6 7 (Read) DATA1 DATAx 12 13 EWAIT UDS, LDS Figure A-11. Example 1b: Normal Expanded Mode — Stretched Read Access MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 957
Appendix A Electrical Characteristics 1 CSx ADDRx ADDR1 ADDR2 RE 4 5 WE 9 10 DATAx 11 (Write) DATA1 12 13 EWAIT UDS, LDS Figure A-12. Example 1b: Normal Expanded Mode — Stretched Write Access MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 958
Appendix A Electrical Characteristics Table A-28. Example 1b: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 1) No. C Characteristic 2 Symbol 3 Stretch Cycles Unit Min Max Min Max fi D.C. 40.0 D.C. 40.0 MHz tcyc 25 ∞ 25 ∞ ns fo D.C. 13.3 D.C. 10.
PAGE 959
Appendix A Electrical Characteristics A.8.3 Emulation Single-Chip Mode (Without Wait States) 1 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ACC1 ADDR2 ACC2 ADDR3 ADDR [19:16]/ IQSTAT [3:0] ADDR1 IQSTAT0 ADDR2 IQSTAT1 ADDR3 ADDR [15:0]/ IVD [15:0] ADDR1 IVD0 ADDR2 IVD1 ADDR3 8 9 DATAx DATA0 (Read) DATA1 (Write) DATA2 10 12 11 12 R/W LSTRB Figure A-13. Example 2a: Emulation Single-Chip Mode — Read Followed by Write MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 960
Appendix A Electrical Characteristics Table A-29. Example 2a: Emulation Single-Chip Mode Timing VDD35 = 5.0 V (EWAITE = 0) Characteristic1 No. C — — Frequency of internal bus 1 — Cycle time 2 D 3 Symbol Min Max Unit fi D.C. 40.0 MHz tcyc 25 ∞ ns Pulse width, E high PWEH 11.5 — ns D Pulse width, E low PWEL 11.5 — ns 4 D Address delay time tAD — 5 ns 5 D Address hold time tAH 0 — ns 2 6 D IVDx delay time tIVDD — 4.
PAGE 961
Appendix A Electrical Characteristics A.8.4 Emulation Expanded Mode (With Optional Access Stretching) 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ACC1 IQSTAT0 ? ADDR1 ADDR1 ADDR1 000 IQSTAT1 ADDR2 ADDR2 IVD1 ADDR2 8 9 DATAx DATA0 (Read) DATA1 12 12 R/W LSTRB Figure A-14. Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 962
Appendix A Electrical Characteristics 1 2 3 ECLK2X ECLK 4 5 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ACC1 ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 IQSTAT0 ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ? ADDR1 000 IQSTAT1 x ADDR2 ADDR2 ADDR2 10 DATAx 11 (write) data1 12 12 R/W LSTRB Figure A-15. Example 2b: Emulation Expanded Mode Ò Write with 1 Stretch Cycle MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 963
Appendix A Electrical Characteristics Table A-30. Example 2b: Emulation Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 0) No. 1 C Symbol Characteristic 1 Stretch Cycle Min Max 2 Stretch Cycles Min Max 3 Stretch Cycles Min Max Unit — — Internal cycle time tcyc 25 25 25 25 25 25 ns 1 — Cycle time tcyce 50 ∞ 75 ∞ 100 ∞ ns 2 D Pulse width, E high PWEH 11.5 14 11.5 14 11.5 14 ns 3 D E falling to sampling E rising tEFSR 35 39.5 60 64.5 85 89.
PAGE 964
Appendix A Electrical Characteristics A.8.5 External Tag Trigger Timing 1 ECLK ADDR ADDR DATAx DATA R/W 2 TAGHI/TAGLO 3 Figure A-16. External Trigger Timing Table A-31. External Tag Trigger Timing VDD35 = 5.0 V 1 Characteristic 1 No. C 1 D Frequency of internal bus 2 D 3 4 Symbol Min Max Unit fi D.C. 40.0 MHz Cycle time tcyc 25 ∞ ns D TAGHI/TAGLO setup time tTS 11.
PAGE 965
Appendix B Package Information Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12XDP512 packages. MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 966
Appendix B Package Information B.2 144-Pin LQFP 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 L M CL B V X 140X B1 VIEW Y 36 V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
PAGE 967
Appendix B Package Information B.3 112-Pin LQFP Package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 C AA J V1 E θ1 (Y) (Z) VIEW AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.
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Appendix B Package Information B.4 80-Pin QFP Package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.
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Appendix C Recommended PCB Layout Appendix C Recommended PCB Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1–C6). • Central point of the ground star should be the VSSR pin. • Use low ohmic low inductance connections between VSS1, VSS2, and VSSR.
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Appendix C Recommended PCB Layout Table C-1.
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Appendix C Recommended PCB Layout C6 VDDX Figure C-1. 144-Pin LQFP Recommended PCB Layout VSSA VREGEN C3 VDDA VDD1 C1 VSS2 VSS1 C2 VDD2 VDDX2 VDDR2 C11 VSSX2 C12 VSSR2 C5 Q1 C7 VSSPLL C10 VDDPLL C9 C8 VDDR1 C4 VSSR1 R1 MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix C Recommended PCB Layout C6 VDDX Figure C-2. 112-Pin LQFP Recommended PCB Layout VSSA VREGEN VSSX C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 C5 C7 C10 C9 VDDPLL VSSPLL Q1 C8 VDDR C4 VSSR R1 MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix C Recommended PCB Layout VREGEN C6 VDDX Figure C-3. 80-Pin QFP Recommended PCB Layout VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 C5 VSSPLL Q1 C8 VDDR C7 VSSR C4 VDD2 C10 C9 VSSPLL R1 VDDPLL MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix D Derivative Differences Appendix D Derivative Differences D.
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Appendix D Derivative Differences Device 9S12XD1281 Package Flash RAM EEPROM 128K 8K 2K 64K 4K 1K ROM 112 LQFP 80 QFP 9S12XD641 1 80 QFP Part includes module versions S12XDBGV3 and S12XMMCV3 which arenot covered in this data sheet. Please refer to the corresponding data sheets for detailed information. MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix D Derivative Differences D.2 Memory Sizes and Package Options S12XA - Family Device Package Flash RAM 512K 32K EEPROM 144 LQFP 9S12XA512 112 LQFP 80 QFP 4K 144 LQFP 9S12XA2561 112 LQFP 256K 16K 128K 12K 80 QFP 9S12XA1281 112 LQFP 2K 80 QFP 1 Part includes module versions S12XDBGV3 and S12XMMCV3 which are not covered in this data sheet. Please refer to the corresponding data sheets for detailed information. MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix D Derivative Differences D.3 MC9S12XD-Family Flash Configuration1 2 3 4 5 Global Address DP512/ DT512 DT384 DT256/ DG256 128k 128k 128k DG128/ D128 D64 $78_0000 (PPAGE $E0) $7A_0000 (PPAGE $E8) 128k $7C_0000 (PPAGE $F0) 128k 128k 128k 128k $7E_0000 (PPAGE $F8) 128k 128k 64k Shared XGATE/CPU area Not implemented 1. XGATE read access to Flash not possible on DG128/D128 and D64 2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF 3.
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Appendix D Derivative Differences D.
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Appendix D Derivative Differences 2 ATD1 routed to PAD00-15 instead of PAD08-23. D.
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Appendix D Derivative Differences D.6 Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output.
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Appendix E Ordering Information Appendix E Ordering Information The following figure provides an ordering number example for the MC9S12XD-Family devices MC9S12X DP512 C FU Temperature Options C = -40˚C to 85˚C Package Option Temperature Option V = -40˚C to 105˚C M = -40˚C to 125˚C Device Title Package Options Controller Family FU = 80 QFP PV = 112 LQFP FV = 144 LQFP Figure E-1.
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Appendix E Ordering Information MC9S12XDP512 Data Sheet, Rev. 2.
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Appendix E Ordering Information Table E-1.
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Appendix E Ordering Information Table E-1. MC and SC Part Numbers MC PART NUMBER SC PART NUMBER PKG (MASKSET-INDEPENDENT) FOR OUR RECOMMENDED MASKSET (MASKSET-SPECIFIC) FOR 0L15Y MASKSET ONLY MC9S12XDT512VFV SC104024VFV 144 MC9S12XDT384CFV SC104025CFV 144 MC9S12XDT384MFV SC104025MFV 144 MC9S12XDT384VFV SC104025VFV 144 MC9S12XD384CFV SC104026CFV 144 MC9S12XD384MFV SC104026MFV 144 MC9S12XD384VFV SC104026VFV 144 MC9S12XDP512 Data Sheet, Rev. 2.
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