User's Guide

MPC837xE-RDS, Rev. 1.0
10 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
2.1 Board-Level Functions
The board-level functions discussed in this section are reset, interrupts, clock distribution, and interface
specification.
2.1.1 Reset and Reset Configurations
The MPC837xE-RDS reset module generates a single reset to reset the MPC837xE and other peripherals
on the board. The reset unit provides power-on reset, hard reset, and soft reset signals in compliance with
the MPC837xE hardware specification. Figure 2 shows the reset circuitry.
Figure 2. Reset Circuitry of the MPC837xE
• The COP/JTAG port or the MPC837xE generates the signal for hard reset.
• The Maxim MAX6829 device generates the power-on reset. When MR is de-asserted and 3.3 V is
ready, the MAX6829 internal timeout guarantees a minimum reset active time of 140 ms before
PORESET is de-asserted. This circuitry guarantees a 140 ms PORESET pulse width after 3.3 V
reaches the right voltage level, and this meets the specification of the PORESET
input of
MPC837xE.
• The COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller.
The RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can
directly generate the hard-reset signal by asserting this line low.
• The pushbutton reset interfaces the MR
signal with a debounce capability to produce a manual
master reset of the processor.
MAX6829
3.3 V
Push Button
HRESET from COP
SRESET
from COP
TRST
from COP
SRESET
to MPC837xE
PORESET
to MPC837xE
FLASH
10/100/1000 PHY
MPC837xE
TRST to MPC837xE
GND
1.0 V
MR
Watchdog Input from MPC837xE
PCI-E & Mini PCI-E