User's Guide

MPC837xE-RDS, Rev. 1.0
14 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
Figure 5. DDR2 SDRAM Connection
2.1.5 Local Bus Controller
The MPC837xE local bus controller has a 32-bit LAD[0–31] address that consists of data multiplex bus
and control signals. The local bus speed is up to 133 MHz. To interface with the standard memory device,
an address latch must provide the address signals. The LALE is used as the latching signal. To reduce the
load of the high speed 32-bit local bus interface, there is a data buffer for all low-speed devices attached
to the memory controller. The local bus only drives the 64MB NOR Flash menory on the MPC837xE-RDS
board:
DDR2
SDRAM
Controller
Vref
Generator
Vref 0.9 V
1.8 V Input
Vref
MSYNC_OUT
MSYNC_IN
MPC837xE
DDR2
SDRAM
Vref
Vref
DQ[0:63]
DQ[32:47]
DQ[0:15]
DM[0:7]
DM[0,1]
DM[4,5]
DQS[0:7]
DQS[0,1]
DQS[4,5]
A[0:12], BA[0:2],CTRL
MCK[0:3] pairs
MCK0
MCK2 pair
DDR2
SDRAM
DDR2
SDRAM
DQ[48:63]
DQ[16:31]
DM[2,3]
DM[6,7]
DQS[2,3]
DQS[6,7]
MCK1 pair
MCK3 pair
DDR2
SDRAM
Vref
Vref
1Gb(X16)
1Gb(X16)
1Gb(X16)
1Gb(X16)
pair