User's Guide
Table Of Contents
- About This Book
- 1 Introduction
- 2 MPC837xE-RDS Board
- 2.1 Board-Level Functions
- 2.1.1 Reset and Reset Configurations
- 2.1.2 External Interrupts
- 2.1.3 Clock Distribution
- 2.1.4 DDR2 SDRAM Controller
- 2.1.5 Local Bus Controller
- 2.1.6 Flash Memory
- 2.1.7 I2C
- 2.1.8 SATA Controller
- 2.1.9 PCI Express Interface (PCI-E & Mini PCI-E)
- 2.1.10 10/100/1000 BaseT Interface
- 2.1.11 RS-232 Port
- 2.1.12 USB 2.0 Interface
- 2.1.13 PCI Subsystem
- 2.1.14 COP/JTAG Port
- 2.2 MPC837xE-RDS Assembly
- 2.3 Connectors
- 2.4 LEDs
- 2.5 MPC837xE-RDS Board Configuration
- 2.6 Specifications
- 2.7 Mechanical Data
- 2.1 Board-Level Functions
- 3 Board Bootup
- 4 MPC837xE-RDS Software
- 5 Unit Assembly
- MPC837xE-RDS
MPC837xE-RDS, Rev. 1.0
16 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
2.1.8 SATA Controller
MPC837xE has a SATA controller for storage applications as shown in Figure 7. There are two SATA
channels for MPC8377E. It requires a 100-MHz input clock, which is provided by the clock generator.
2.1.9 PCI Express Interface (PCI-E & Mini PCI-E)
MPC8377E supports the PCI Express (PCI-E) interface. It can be configured as two mini PCI-E interfaces
or one mini PCI-E interface and one 1X PCI-E interface as shown in Figure 7. It also requires a 100-MHz
input clock, which is provided by the clock generator.
Figure 7. SATA and PCI-E Connections
2.1.10 10/100/1000 BaseT Interface
On the MPC837xE-RDS board, eTSEC1 and eTSEC2 use RGMII mode. The eTSEC1 and eTSEC2 drive
two on-board 10/100/1000 PHYs (RTL8211B), respectively. The I/O voltage is set to 3.3 V RGMII for
RTL8211B. The RGMII (1000 BaseT) is a source synchronous bus. For a transmit bus connection, it is
synchronous to GTX_CLK from the TSEC module. The receive bus connection is synchronous to
RX_CLK generated from the PHY device. The MPC837xE MII management interface also connects to
MPC8377E
SATA
eSATA Channel
eSATA Channel
PCI-E (1X)
Mini PCI-E
& PCI-E
Or
Mini PCI-E