SC140 DSP Core Reference Manual Revision 4.1, September 2005 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc.
LICENSOR is defined as Freescale Semiconductor, Inc. LICENSOR reserves the right to make changes without further notice to any products included and covered hereby.
Table of Contents About This Book Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2.1 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.2.2 Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.2.2.3 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.2.2.4 Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.2.2.5 Unsigned Arithmetic. . . .
Chapter 3 Control Registers 3.1 Core Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.2 Exception and Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.2.1 Clearing EMR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.
4.6.4 General EOnCE Register Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.7 EOnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.7.1 EOnCE Command Register (ECR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.7.2 EOnCE Status Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 4.7.3 EOnCE Monitor and Control Register (EMCR). . . . . . . . . . .
Chapter 5 Program Control 5.1 Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 Instruction Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1.1 Instruction Pre-Fetch and Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.1.2 Instruction Dispatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.1.
5.5.5 Fast Return from Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.6 Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.6.1 Normal Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.6.2 Exception Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.6.3 Typical Working Mode Usage Scenarios . . .
6.7 Core Assembly Syntax with an ISAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 6.7.1 Identification of ISAP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 6.7.1.1 Working with One ISAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 6.7.1.2 Working with Multiple ISAPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64 6.7.2 An Example of the Definition Flexibility of an ISAP . . . . . . .
7.5.6 Status Bit Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 7.5.7 Loop Nesting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7.5.8 Loop LA Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 7.5.9 Loop Sequencing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 7.5.10 Loop COF Rules . . . . . . .
A.1.5 Prefix Word Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 A.1.5.1 One-Word Low Register Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.1.5.2 Two-Word Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 A.1.6 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 A.1.6.1 Instruction Sub-types . . . . . . . . . . . . . . .
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List of Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 Block Diagram of a Typical SoC Configuration with the SC140 Core . . . . . . . 1-5 Block Diagram of the SC140 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 DALU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 DALU Data Representations . . . . . . .
4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 xiv Software Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 EOnCE Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-31 2-30 3-1 3-2 4-1 DALU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Write to Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Read from Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 xvi JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 JTAG Scan Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 EOnCE Event Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18 5-19 5-20 5-21 6-1 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 B-1 Exit Wait Processing State due to an Interrupt or NMI . . . . . . . . . . . . . . . . . . 5-45 Exception Vector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 Exception Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 Pipeline Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Examples 3-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 7-1 7-2 7-3 7-4 7-5 7-6 Clearing an EMR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Four SC140 Instructions in an Execution Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Grouping Six SC140 Instructions in an Execution Set. . . . . . . . . . . . . . . . . . . .
7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 xx Duplicate Stack Pointer Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Duplicate Register Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Duplicate SR/EMR Register Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 7-65 7-66 7-67 7-68 7-69 7-70 7-71 7-72 7-73 7-74 7-75 7-76 7-77 7-78 7-79 7-80 SR Write to SR Status Bit Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOVF Update to SR Read or Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOVF Update grouped with Move-like SR updates . . . . . . . . . . . . . . . . . . . . Status Bit Update with SR Read . . . . .
7-81 7-82 7-83 7-84 7-85 7-86 7-87 7-88 7-89 7-90 7-91 7-92 7-93 7-94 7-95 7-96 7-97 7-98 7-99 7-100 7-101 7-102 7-103 7-104 xxii Illegal use of RAS value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR.2 Across a COF Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 from a Delay Slot to a COF Destination . . . . . . . . . . . . . . . . . . . . . . . . . . Set condition during a COF, and use it at the destination (T.1) . . . . . .
About This Book This manual provides reference information for the StarCore SC140 digital signal processor (DSP) core. Specifically, this book describes the instruction set architecture and programming model for the SC140 core as well as corresponding register details, debug capabilities, and programming rules. An appendix provides a detailed instruction reference for the SC140 instruction set, describing the operation, mnemonics, instruction fields, and encoding for each instruction.
Abbreviations The abbreviations used in this manual are listed below: Table 1.
Table 1.
Table 1.
Chapter 1 Introduction The StarCore SC140 digital signal processing (DSP) core, a new member of the SC100 architecture, addresses key market needs of next-generation DSP applications. It is especially suited for wireline and wireless communications, including infrastructure and subscriber communications.
Architectural Differentiation 1.2 Architectural Differentiation The SC140architecture differentiates itself in the market with the following capabilities: • High-level Abstraction of the Application Software — DSP applications and kernels can currently be developed in the C programming language. An optimizing compiler generates parallel instructions while maintaining a high code density.
Core Architecture Features 1.
Core Architecture Features 1.3.1 Typical System-On-Chip Configuration The SC140 is a high-performance general-purpose fixed-point DSP core, allowing it to support many system-on-chip (SoC) configurations. A library of modules containing memories, peripherals, accelerators, and other processor cores makes it possible for a variety of highly integrated and cost-effective SoC devices to be built around the SC140.
Core Architecture Features SoC DSP expansion area System expansion area External memory interface PLL Standard I/O Peripherals Level-2 caches DMA Application specific accelerators On-chip RAM and ROM Host interface General purpose programmable accelerators Other micro-controllers SC140 platform Bus switch & interfaces Trace buffer Unified M1 prog. & data memory PIC JTAG Instruction cache EOnCE Data cache RAM ROM ISAP SC140 core P XA XB Figure 1-1.
Core Architecture Features 1-6 SC140 DSP Core Reference Manual
Chapter 2 Core Architecture This chapter provides an overview of the SC140 core architecture. It describes the main functional blocks and data paths of the core. 2.
Architecture Overview . 32 64 XDBB 32 XDBA 32 XABB XABA 128 PAB PDB Unified Data/Program Memory 64 StarCore SC140 Core Program Sequencer Address Generator Register File DALU Register File DALU AGU EOnCE ISAP 25 2 AAUs JTAG controller BMU 4 ALUs Instruction Bus Figure 2-1. Block Diagram of the SC140 Core 2.1.1 Data Arithmetic Logic Unit (DALU) The DALU performs arithmetic and logical operations on data operands in the SC140 core.
Architecture Overview • MOVE.2L loads or stores two long words (64-bit). 2.1.1.1 Data Register File The DALU registers can be read or written over the data buses (XDBA and XDBB). A DALU register can be the source for up to four simultaneous instructions, but simultaneous writes of a destination register are illegal. The source operands for DALU arithmetic instructions usually originate from DALU registers.
Architecture Overview The AGU in the SC140 core has two address arithmetic units (AAU) to allow two address generation operations at every clock cycle. The AAU has access to: • Sixteen 32-bit address registers (R0–R15), of which R8–R15 can also be used as base address registers for modulo addressing. • Four 32-bit offset registers (N0–N3). • Four 32-bit modulo registers (M0–M3). The two AAUs are identical. Each contains: • A 32-bit full adder, used for offset calculations.
Architecture Overview 2.1.3 Program Sequencer Unit (PSEQ) The PSEQ performs instruction fetch, instruction dispatch, hardware loop control, and exception processing. The PSEQ controls the different processing states of the SC140 core. The PSEQ consists of three hardware blocks: • Program dispatch unit (PDU)—Responsible for detecting the execution set out of a one or two fetch set, and dispatching the execution set’s various instructions to their appropriate execution units where they are decoded.
DALU 2.2 DALU This section describes the architecture and operation of the DALU, the block where most of the arithmetic and logical operations are performed on data operands. In addition, this section details the arithmetic and rounding operations performed by the DALU as well as its programming model. 2.2.1 DALU Architecture The DALU performs most of the arithmetic and logical operations on data operands in the SC140 core.
DALU The DALU programming model is shown in Table 2-1. Register D0 refers to the entire 40-bit register, whereas D0.e, D0.h, and D0.l refer to the extension: high portion and low portion of the D0 register, respectively. In addition, one limit tag bit is associated with each data register. L0–L15 are concatenated to D0–D15, respectively. Table 2-1. DALU Programming Model LIMIT EXT HP LP L0 D0.e D0.h D0.l L1 D1.e D1.h D1.l L2 D2.e D2.h D2.l L3 D3.e D3.h D3. L5 D5.e D5.h D5.l L6 D6.
DALU 2.2.1.1 Data Registers (D0–D15) In this section, the D0–D15 data registers are referred to as Dn. They can be used as: • Source operands • Destination operands • Accumulators The registers can serve as input buffer registers between XDBA or XDBB and the ALUs. The registers are used as DALU source operands, allowing new operands to be loaded for the next instruction while the register contents are used by the current arithmetic instruction.
DALU A special case of the MOVE.L instruction is used for reading from or writing to the EXT portion of a data register. Six variations of this instruction save (restore) the extension bits and Ln bit of data registers to (from) memory. One of the variations writes to memory the Ln bit and extension bits of an even and an odd pair of registers. Another variation reads bits 8:0 from memory to the extension bits and the Ln bit of an even register.
DALU . Table 2-4. Data Registers Access Width Operand Type Data Width (Bits) Byte 8 Word 16 Long 32 Two word 32 Four byte 32 Two long word 64 Four word 64 2.2.1.2 Multiply-Accumulate (MAC) Unit The MAC unit is the arithmetic part of the ALU containing both a multiplier and an adder. It also performs other operations such as rounding, saturation, comparisons, and shifting. Inputs to the MAC unit are from data registers or from immediate data programmed into the instruction.
DALU Table 2-5. DALU Arithmetic Instructions (MAC) (Continued) Instruction Description DECEQ Decrement a data register and set T (the true bit) if zero DECGE Decrement a data register and set T if greater than or equal to zero DIV Divide iteration DMACSS Multiply signed by signed and accumulate with data register right-shifted by word size DMACSU Multiply signed by unsigned and accumulate with data register right-shifted by word size IADDNC.
DALU Table 2-5. DALU Arithmetic Instructions (MAC) (Continued) Instruction Description NEG Negate RND Round SAT.F Saturate fractional value in data register to fit in high portion SAT.L Saturate value in data register to fit in 32 bits SBC Subtract long with carry SBR Subtract and round SUB Subtract SUB2 Subtract two words SUBL Shift left and subtract SUBNC.
DALU Table 2-6.
DALU 2.2.1.5 Scaling The data shifters in the shifter/limiter unit can perform the following data shift operations: • Scale up—Shift data one bit to the left • Scale down—Shift data one bit to the right • No scaling—Pass the data unshifted The eight shifters permit direct dynamic scaling of fixed-point data without additional program steps. For example, this permits straightforward block floating-point implementation of Fast Fourier Transforms (FFTs).
DALU Table 2-8. Ln Bit Calculation S1 S0 Scaling Mode Bits Defining the Ln bit Calculation 0 0 No Scaling Bits 39, 38..............32, 31 0 1 Scale Down Bits 39, 38..............33, 32 1 0 Scale Up Bits 39, 38..............31, 30 The Ln bit is calculated (and set or cleared) for the following saturable instructions: ABS, ADC, ADR, ADD, ADDNC, ASL, ASR, DIV, INC, MAC, MACR, MPY, MPYR, NEG, RND, SBC, SBR, SUB, SUBL, SUBNC, and TFRx.
DALU Table 2-9. Limiting Example Memory/ Register New Value Comments move.w #$0030,r0 r0 $0000 0020 R0 holds the address for the first move to memory moveu.w #$7fff,d0.h d0 $7fff 0000 d0.h set with the most positive 2’s complement number moveu.w #$7fff,d1.h d1 $7fff 0000 d1.h set with the most positive 2’s complement number add d0,d1,d3 d3 $1:00:fffe 0000 move.f d3,(r0)+ $0020 $fffe No limiting from the move instruction moves.
DALU The following table (Table 2-11) shows the arithmetic saturation and rounding operations for the four possible cases of scaling, no scaling, and arithmetic saturation mode on/off. Table 2-11.
DALU 16-bit word operand D0.h—D15.h, 16-bit memory 40-bit registers D0—D15 –28 – 20 2–15 20 2–15 2–16 2–31 Signed Fractional Two’s Complement Representations 16-bit word operand D0.l—D15.l, 16-bit memory 40-bit registers D0—D15 –215 214 20 . –239 231 216 215 20 . Signed Integer Two’s Complement Representations Figure 2-3. DALU Data Representations 2.2.2.
DALU 2.2.2.2.2 Signed Integer This format is used when processing data as integers. Using this format, the N-bit operand is represented using the N.0 bit format (N integer bits). Signed integer numbers lie in the following range: -2[N-1] ≤ SI ≤ [2[N-1]-1] For words and long-word signed integers, the most negative word that can be represented is -32768 ($8000) and the most negative long word is -2147483648 ($8000 0000).
DALU 2.2.2.3 Multiplication Most of the operations are performed identically in fractional and integer arithmetic. However, the multiplication operation is not the same for integer and fractional arithmetic. As illustrated in Figure 2-4, fractional and integer multiplication differ by a 1-bit shift. Any binary multiplication of two N-bit signed numbers gives a signed result that is 2N-1 bits in length.
DALU 2.2.2.5.2 Unsigned Comparison When performing an unsigned comparison, the condition code computation is different from signed comparisons. The most significant bit of the unsigned operand has a positive weight, while in signed representation it has a negative weight. Special instructions are implemented to support unsigned comparison such as CMPHI (compare greater). 2.2.2.6 Rounding Modes The SC140 DALU performs rounding of the full register to single precision if requested in the instruction.
DALU Figure 2-5 shows the four cases for rounding a number in the Dn.h register. If scaling is set in the SR, the rounding position is updated to reflect the alignment of the result when it is put on the data bus. However, the contents of the register are not scaled. Case I: If D0.l < $8000 (1/2), then round down (add nothing) Before Rounding After Rounding 0 D0.e D0.h D0.l XX..XX XXX...XXX0100 011XXX....XXX 39 32 31 16 15 0 D0.e D0.h D0.l* XX..XX XXX...XXX0100 000.........
DALU 2.2.2.6.2 Two’s Complement Rounding When two’s complement rounding is selected by setting the rounding mode (RM) bit in the SR, all values greater than or equal to one-half are rounded up, and all values less than one-half are rounded down. Therefore, a small positive bias is introduced. For no scaling, the higher portion (HP) of the register is bits 39:16; the low portion (LP) is bits 15:0. The HP is incremented by one bit if the LP was ≥ 1/2. The HP is left alone if the LP was <1/2.
DALU Figure 2-6 shows the four cases for rounding a number in the Dn.h register. If scaling is set in the SR, the rounding position is updated to reflect the alignment of the result when it is transferred to the data bus. However, the contents of the register are not scaled. Case I: If D0.l < $8000 (1/2), then round down (add nothing) Before Rounding After Rounding 0 D0.e D0.h D0.e D0.l XX..XX XXX...XXX0100 011XXX....XXX 39 32 31 16 15 0 D0.h D0.l* XX..XX XXX...XXX0100 000.........
DALU 2.2.2.7 Arithmetic Saturation Mode By setting the arithmetic saturation mode (SM) bit in the SR, the arithmetic unit’s result is limited to 32 bits (high portion and low portion). The dynamic range of the DALU is therefore reduced to 32 bits. The purpose of this bit is to provide a saturation mode for algorithms that do not recognize or cannot take advantage of the extension bits.
DALU 2.2.2.8 Multi-Precision Arithmetic Support The SC140 DALU supports multi-precision arithmetic for fractional and integer operations. 2.2.2.8.1 Fractional Multi-Precision Arithmetic A set of DALU instructions is provided for fractional multi-precision multiplications. When these instructions are used, the multiplier accepts some combinations of two’s complement signed and unsigned formats. Table 2-15 lists these instructions. Table 2-15.
DALU Figure 2-8 illustrates the use of these instructions in the case of a double-precision multiplication of 32-bit x 32-bit operands. The “Unsigned x Unsigned” operation is used to multiply or multiply-accumulate the unsigned low portion of one double-precision number with the unsigned low portion of the other double-precision number.
DALU Figure 2-9 illustrates the use of the fractional multiplication and multiply-accumulate instructions in the case of a mixed double-precision multiplication of 16-bit by 32-bit signed operands. The “Signed x Unsigned” operation is used to multiply the signed high portion of one single-precision number with the unsigned low portion of the other double-precision number. The “Signed x Signed” DMAC operation is used to multiply-accumulate the two signed high portions of the two signed operands.
DALU Figure 2-10 illustrates the use of these instructions in the case of a signed integer double-precision multiplication of 32-bit by 32-bit signed operands. In this example, only a 32-bit result is generated. The most significant 32 bits are shifted out.The “Unsigned x Unsigned” operation is used to multiply or multiply-accumulate the unsigned low portion of one double-precision number with the unsigned low portion of the other double-precision number.
DALU Figure 2-11 illustrates the use of these instructions in the case of an unsigned integer double-precision multiplication of 32-bit by 32-bit unsigned operands. In this example, only a 32-bit result is generated. The most significant 32-bits are shifted out. All multiplications are of the “Unsigned x Unsigned” type using different combinations of high and low portions. D0.h D0.l × D1.h D1.l = Unsigned × Unsigned impyuu d0,d1,d2 D1.l × D0.l Unsigned × Unsigned impyhluu d0,d1,d3 D0.h × D1.
Address Generation Unit 2.3 Address Generation Unit The AGU is one of the execution units in the SC140 core. The AGU performs effective address calculations using the integer arithmetic necessary to address data operands in memory. It also contains the registers used to generate the addresses. The AGU implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. It operates in parallel with other chip resources to minimize address generation overhead.
Address Generation Unit R8/B0 M0 N0 R9/B1 M1 N1 R10/B2 M2 N2 R11/B3 M3 N3 R12/B4 XABA XABB 32 32 PAB 32 R0 Address Arithmetic Unit (AAU) R1 R2 R3 R4 MCTL R13/B5 R5 R14/B6 R6 R15/B7 R7 NSP ESP Bit Mask Unit (BMU) Program Counter (PC) Address Memory Data Bus 1 (XDBA) 64 Memory Data Bus 2 (XDBB) 64 Figure 2-12. AGU Block Diagram All sixteen address registers (R0–R15) as well as the NSP or ESP are used for generating addresses in the register indirect addressing modes.
Address Generation Unit During every instruction cycle, the two AAUs can generate one 32-bit program memory address on the PAB (in case of change of flow) or two 32-bit data memory addresses (one on each of the XABA and XABB). Each AAU can generate an address to access a byte, a 16-bit word, a 32-bit long word, or a 64-bit two-word long operand in memory to feed into the DALU in a single cycle. Each AAU can update one address register during one instruction cycle.
Address Generation Unit 2.3.2 AGU Programming Model The programming model of the AGU is shown in Figure 2-13. The address registers can be programmed for linear addressing, modulo addressing (regular or multiple wrap-around), and reverse-carry addressing. Automatic updating of address registers is available when using address register indirect addressing.
Address Generation Unit 2.3.2.1 Address Registers (R0–R15) The sixteen 32-bit address registers R0–R15 can contain addresses or general-purpose data. These are 32-bit read/write registers. The 32-bit address in a selected address register is used in calculating the effective address of an operand. The contents of an address register can point directly to data, or can be used as an index. The sixteen address registers R0–R15 are composed of two separate banks, a low bank (R0–R7) and a high bank (R8–R15).
Address Generation Unit 2.3.2.2.1 Shadow Stack Pointer Registers Both stack pointers have shadow registers which contain a decremented value of the stack pointers. When the shadow register is not valid, the POP instruction is executed in two cycles. The first cycle is used to decrement the stack pointer. When the shadow register is valid, the POP instruction is executed in only one cycle. When an SP is written by the AAU register transfer (TFRA), its shadow register automatically becomes invalid.
Address Generation Unit 2.3.2.6 Modifier Control Register (MCTL) The MCTL register is a 32-bit read/write register. This control register is used to program the address mode (AM) for each of the eight low address registers (R0–R7). The addressing mode of the high address register file (R8–R15) cannot be programmed and functions in linear addressing mode only. The format of MCTL is shown in Figure 2-14.
Address Generation Unit 2.3.3 Addressing Modes The SC140 core provides four types of addressing modes: • Register direct • Address register indirect • PC relative • Special The addressing modes are related to where the operands are to be found and how the address calculations are to be made. These modes are described in the following sections: 2.3.3.
Address Generation Unit • Post-decrement, (Rn)- —The operand address is in the address register. After the operand address is used, it is decremented by the access width (1, 2, 4, or 8 bytes) and stored in the same address register. The type of arithmetic used for updating R0-R7 is determined by programming the MCTL register. An example is: move.l (r3)-,d2. In this case, the value in r3 is decremented by four after the move has taken place.
Address Generation Unit active SP register are unchanged. The type of arithmetic used is always linear. An example is: move.w #$ffff,(sp–$3e). The encoded displacement is 31,the maximum value of five bits, and the actual displacement is 62 ($3e), since the access width is two. • SP Word Displacement, (SP + xxxx)—The operand address is the sum of the contents of the active stack pointer (SP) and an immediate displacement. The displacement is a signed 15-bit word that requires a second instruction word.
Address Generation Unit 2.3.3.4 Special Addressing Modes The special addressing modes do not use an address register when specifying an effective address. They either use an immediate value that is included in the instruction for the data value, such as the data value address, or they use a register that is implicitly referenced by the instruction for the data value. • Immediate Short Data — A 5-bit, 6-bit, or 7-bit operand is part of the instruction operation word.
Address Generation Unit 2.3.3.5 Memory Access Width The SC140 core supports variable width access to data memory. With every memory access, the core sends one of four signals to the memory interface to designate whether the access width is 8 bits, 16 bits, 32 bits, or 64 bits wide. The access width is determined by the type of MOVE instruction being used. For example, MOVE.B is used for byte access. MOVE.W is used for word access. For long-word access, MOVE.L, MOVE.2F, and MOVE.2W are used.
Address Generation Unit Table 2-19 summarizes the memory address alignment rule for each type of memory access. Table 2-19. Memory Address Alignment Access Type Aligned Address Byte access Any address Word access Multiple of 2 Long-word access Multiple of 4 Two long-word access Multiple of 8 2.3.3.7 Addressing Modes Summary Table 2-20 provides a summary of the addressing modes described in the previous sections.
Address Generation Unit Table 2-20.
Address Generation Unit 2.3.4 Address Modifier Modes The AAU supports linear, reverse-carry, modulo, and multiple wrap-around modulo arithmetic types for address register indirect modes operating on R0-R7. These arithmetic types allow the easy creation of data structures in memory for First-In/First-Out (FIFO) queues, delay lines, circular buffers, stacks, and reverse-carry Fast Fourier Transform (FFT) buffers.
Address Generation Unit register Rn has one Mj register assigned to it by encoding in the MCTL. The lower boundary value of the buffer resides in the Bn register, and the upper boundary is calculated as Bn+Mj-1. Mj must be smaller than 231 - 1 (Mj < 231 - 1). The modulo addressing definition, using a base register (Bn) and a modulo register (Mj), enables the programmer to locate the modulo buffer at any address. The buffer start address is only required to be aligned to the access width.
Address Generation Unit Table 2-21 describes the modulo register values and the corresponding address calculation. Table 2-21. Modulo Register Values for Modulo Addressing Mode Modifier Mj Address Calculation Arithmetic $0000 0000 Unused $0000 0001 Modulo 1 $0000 0002 Modulo 2 $7FFF FFFE Modulo 231-2 $7FFF FFFF Modulo 231-1 2.3.4.4 Multiple Wrap-Around Modulo Addressing Mode Multiple wrap-around addressing is useful for decimation, interpolation, and waveform generation.
Address Generation Unit Table 2-22 describes the modulo register Mj values and the corresponding multiple wrap-around address calculation. Table 2-22. Modulo Register Values for Wrap-Around Modulo Addressing Mode Modifier Mj Address Calculation Arithmetic $0000 0001 Multiple Wrap-around Modulo 2 $0000 0003 Multiple Wrap-around Modulo 4 $0000 0007 Multiple Wrap-around Modulo 8 $7FFF FFFF Multiple Wrap-around Modulo 231 $FFFF FFFF Linear 2.3.
Address Generation Unit Table 2-23. AGU Arithmetic Instructions (Continued) Instruction Description DECGEA AGU Decrement and set T if result is equal to or greater than zero INCA AGU Increment register (affected by the modifier mode) LSRA AGU Logical shift right (32-bit) SUBA AGU Subtract (affected by the modifier mode) SXTA.B AGU Sign-extend byte SXTA.W AGU Sign-extend word TFRA AGU Register transfer TSTEQA AGU Test for equal to zero TSTEQA.
Address Generation Unit Table 2-24 lists the arithmetic instructions that are executed in the BMU. Table 2-24. AGU Bit Mask Instructions (BMU) Instruction Description AND.W Logical AND on a 16-bit operand BMCHG Bit mask change Inverts every bit in the destination (register or memory) that has the value 1 in the mask. BMCLR Bit mask clear Clears every bit in the destination (register or memory) that has the value 1 in the mask.
Address Generation Unit 2.3.6.1.1 Example of Normal Usage of the Semaphoring Mechanism The following sequence accesses a resource controlled by a semaphore. label : BMTSET.W #mask,(R0) JT label Normally, the mask enables only one bit. In this case, the memory destination pointed to by (R0) is read, and the enabled bit is tested. The enabled bit is then set, and the memory destination is written back.
Address Generation Unit The suffix just after the period in the MOVE nomenclature indicates the following: • B = Byte • W = Integer word (16 bits) • L = Long word (32 bits) • F = Fractional word (16 bits) Either a two or four may modify the last suffix. Table 2-25. AGU Move Instructions 2-52 Instruction Description MOVE.2F Move two fractional words from memory to a register pair MOVE.2L Move two longs to/from a register pair MOVE.
Address Generation Unit Integer moves from memory (byte, word, long, two long) are right-aligned in the destination register, and by default are sign-extended to the left. Unsigned moves are marked with “U” (for example, MOVEU.B), and zero extended in the destination register. A schematic representation of integer moves from memory into a 40-bit register is shown in Figure 2-16. Moves from registers to memory use the appropriate portion from the source register.
Address Generation Unit . 39 32 sign extension MOVE.F (fractional move) 39 MOVE.2F (fractional double move) 32 sign extension sign extension 39 MOVE.4F (fractional quad-move) 32 sign extension sign extension sign extension sign extension 16 0 zero-fill 16 0 zero-fill zero-fill 0 16 zero-fill zero-fill zero-fill zero-fill Figure 2-17. Fractional Move Instructions The four instructions MOVES.F, MOVES.2F, MOVES.4F, and MOVES.
Memory Interface The extension bits of the even data register occupy bits 0 to 8 (bit 8 is the limit bit). The extension bits of the odd register occupy bits 16 to 24 (bit 24 is the limit bit) as described in Figure 2-18. 31 24 16 0 39 32 8 0 0 16 Memory Long Word 0 L0 + extension D0 L1 + extension D1 Figure 2-18. Bit Allocation in MOVE.L D0.e:D1.e Moves from memory to an extension are only to single registers.
Memory Interface • Memory must resolve access ordering on a cycle by cycle basis. All accesses on a given cycle must be completed before proceeding to accesses in the next cycle. Note that a conflict acces may occur when there are multiple requests to access the same memory module, in the same cycle. An access conflict is resolved by a stall cycle (per conflict), which serializes the multiple request.
Memory Interface The two data buses that connect between the core and the memory are each 64 bits wide. Instructions such as load to registers and store to memory utilize the bus according to the application requirement. Different versions of the instructions are used for different bandwidths such that: • MOVE.B loads or stores bytes (8 bits). • MOVE.W and MOVE.F load or store integer or fractional words (16 bits). • MOVE.2W, MOVE.2F, and MOVE.
Memory Interface Table 2-26 describes the data representation for each 64-bit row in Figure 2-21. Table 2-26. Data Representation in Memory Representation Type Value Eight 8-bit bytes A0 = $0a, A1 = $0b, A2 = $0c, A3 = $0d, A4 = $0e, A5 = $0f Four 16-bit numbers A8 = $0102, A10 = $0304, A12 = $0506, A14 = $0708 Two 32-bit numbers A16 = $11223344, A20 = $ccddeeff 2.4.1.3 Data Moves Data moves are executed by moving core registers to and from memory over one of the data buses (XDBA or XDBB).
Memory Interface Memory Big Endian 0 1 Little Endian 7 2 3 4 5 6 7 0 0a 0b 0c 0d 0e 0f 8 01 02 03 04 05 06 07 08 6 5 4 3 2 1 0 0f 0e 0d 0c 0b 0a 07 08 05 06 03 04 01 02 cc dd ee ff 11 22 33 44 16 ($10) 11 22 33 44 cc dd ee ff 24 ($18) 0 8 16 ($10) 24 ($18) 32 ($20) 32 ($20) xxxx xxxx xxxx xx0a xxxx xxxx xxxx xx0c xxxx xxxx xxxx 0102 xxxx xxxx 1122 3344 64-bit XB-BUS Data Bus Contents MOVE.B (A0), D0 MOVE.B (A2), D0 MOVE.W (A8), D0 MOVE.
Memory Interface 2.4.1.4 Multi-Register Moves For accesses involving more than one register, such as with MOVE.2W or MOVE.4F instructions, the SC140 ensures that data originating from a specific register reaches the same address in memory in both little and big endian modes (and the other way round). The memory system does not distinguish between MOVE.L and MOVE.2W transfers that have the same data width. Memory treats them both like a long word transfer.
Memory Interface This is the desired result. This effect is achieved in little endian mode through logic in the core, which modifies the data on the data bus to the memory for both reads and writes. Figure 2-23 shows examples of multi-register data transfers in big and little endian modes.
Memory Interface 2.4.1.5 Instruction Word Transfers Instruction words are transferred to the core from memory over the program data bus (PDB) to special instruction registers in the program dispatch unit (PDU). The instruction registers can be accessed only with aligned access of 128-bit width (8 instruction words). Figure 2-24 shows the program memory organization in big and little endian modes. Note that program data consists of a series of 16-bit instructions.
Memory Interface Figure 2-25 shows the memory accesses to the same memory area by both program fetches as well as data accesses in big and little endian modes. Memory Big Endian 0 1 2 3 4 5 6 7 Little Endian 7 6 5 4 3 2 1 0 a0b0 c0d0 e0f0 a1b1 0 c1d1 e1f1 a2b2 c2d2 8 c2d2 a2b2 e1f1 c1d1 8 e2f2 a3b3 c3d3 e3f3 16 ($10) e3f3 c3d3 a3b3 e2f2 16 ($10) a1b1 e0f0 c0d0 a0b0 0 MOVE.4W from address $00 a1b1_e0f0_c0d0_a0b0 xxxx_xxxx_c1d1_e1f1 MOVE.
Memory Interface 2.4.1.6 Memory Access Behavior in Big/Little Endian Modes Table 2-27 shows the representation of the move instructions in big and little endian modes. In the examples shown in this table, it is assumed that R0 points to address A0. Each alphanumeric A–H represents one byte. Also, the memory contents may not exactly equal the register contents. For example, in VSL instructions, the memory word (16 bits) is the register word shifted left by one bit.
Memory Interface Table 2-27. Move Instructions in Big and Little Endian Modes (Continued) Instruction Register Operands MOVE.L (Extension) Example: MOVE.L D0.E:D1.E, (A0) 39 MOVE.2L D0 = L0 + A D1 = L1 + B MOVE.4F MOVES.4F 0 32 0 D0 = A B C D D1 = E F G H Example: MOVE.F D0, (R0) 39 32 D0 = MOVE.2F MOVES.2F 16 Example: MOVE.2L D0:D1, (R0) 39 MOVE.F MOVES.F 32 16 A 0 32 16 D0 = A B D1 = C D 0 Example: MOVE.
Memory Interface Table 2-27. Move Instructions in Big and Little Endian Modes (Continued) Instruction VSL.4W 16 A B D6 = C D Note 1 E F Note 2 G H A0 = B A1 = A A2 = D A3 = C A4 = F A5 = E A6 = H A7 = G A0 = C A1 = D A2 = A A3 = B A4 = G A5 = H A6 = E A7 = F A0 = B A1 = A A2 = D A3 = C A4 = F A5 = E A6 = H A7 = G 0 A0 = C A1 = D A2 = A A3 = B A0 = B A1 = A A2 = D A3 = C 0 A0 = C A1 = D A2 = A A3 = B A0 = B A1 = A A2 = D A3 = C Example: VSL.
Memory Interface Table 2-28 shows the representation of the stack support instructions in big and little endian modes. In the examples shown in this table, it is assumed that the stack access is to address A0. The stack instructions treat the register data like a 32-bit long word move. Table 2-28.
Memory Interface Table 2-30 shows the representation of the change-of-flow instructions in big and little endian modes. In this table, it is assumed that the stack access is to address A0. This shows how the contents of the PC and SR are transferred to/from memory like 32-bit long words. Table 2-30.
Chapter 3 Control Registers This chapter describes the core control registers for the SC140 core. Several bits in these registers are not used, and are marked as reserved. These bits are initialized with a zero value and should be written with a zero value for future compatibility. 3.1 Core Control Registers The SC140 programming model contains two 32-bit core control registers: a status register (SR) and an exception and mode register (EMR).
Core Control Registers • ILLEGAL • DEBUG, DEBUGEV (if configured in the EOnCE to generate an exception) The following instructions implicitly pop the SR from the stack: • RTE/D Refer to Appendix A, “SC140 DSP Core Instruction Set,” for a full description of these instructions. The pipeline imposes certain programming rules relating to the minimum distance between writing the SR and when the change takes effect. For further details, refer to Chapter 7, “Programming Rules.
Core Control Registers Table 3-1. Status Register Description (Continued) Name Description Settings LF2 Bit 29 Loop Flag 2 — When set, indicates that hardware loop #3 is enabled. At the start of an ISR, the SR (including the LF2 bit) is pushed onto the software stack and the LF2 bit is cleared. This bit is cleared at core reset. 0 = Hardware loop #3 not enabled 1 = Hardware loop #3 enabled LF1 Bit 28 Loop Flag 1 — When set, indicates that hardware loop #2 is enabled.
Core Control Registers Table 3-1. Status Register Description (Continued) Name Description Settings OVE Bit 20 Overflow Exception Enable Bit — Enables or disables the generation of an exception caused by an overflow. The DOVF bit in EMR is always set when an overflow occurs. If the OVE bit is set and the DOVF bit is already set, no exception is generated until the DOVF bit is cleared and set again. See Section 3.1.2, “Exception and Mode Register (EMR),” for more information.
Core Control Registers Table 3-1. Status Register Description (Continued) Name Description S Bit 6 Scaling Bit — Set when moving a result from a data register (D0–D15) to memory using a MOVES (saturated move) instruction. The scaling bit is set when the absolute value of the data that is moved to memory (after scaling and limiting) is greater than or equal to 0.25 and less than 0.75. The logical equations of this bit, if viewed as functions of the data in the register, are dependent on the scaling mode.
Core Control Registers Table 3-1. Status Register Description (Continued) Name Description Settings SM Bit 2 Arithmetic Saturation Mode — Selects automatic saturation on 32 bits for data arithmetic and logic unit (DALU) results. This bit provides an arithmetic saturation mode for algorithms that do not recognize or cannot take advantage of the extension register. When the arithmetic saturation mode is set, the scaling mode bits are ignored for most instructions. No scaling is performed.
Core Control Registers Table 3-1. Status Register Description (Continued) Name Description Settings C Bit 0 Carry Bit — Indicates whether a carry is generated from the resulting most significant bits (MSB) of the last addition operation or a borrow generated in the last subtraction operation. The carry or borrow is generated from bit 39 of the result. The carry bit is also affected by DALU bit manipulation as well as rotate and shift instructions.
Core Control Registers Table 3-2 describes the EMR fields. Table 3-2. EMR Description Name Description R Bits 31–24 Reserved GP6–GP0 Bits 23–17 General Purpose Flags — Use of these bits is dependent on the state of external pins. Their function is specific to the SoC. BEM Bit 16 Big Endian Memory Bit — Indicates big endian or little endian memory configuration. See Section 2.4.1, “SC140 Endian Support,” for more information.
Core Control Registers Table 3-2. EMR Description (Continued) Name Description Settings ILST Bit 1 Illegal Execution Set — Indicates whether an execution set grouping rule has been violated (for example, more than one opcode dispatched to an execution unit). The ILST bit is a sticky bit. The bit is set if the appropriate exception occurred, and it can only be cleared by the programmer. The clearing operation should only be performed during the illegal exception service routine.
PLL and Clock Registers 3.1.2.1 Clearing EMR Bits The ILIN, ILST, DOVF, and NMID bits can only be set by the hardware. These events should be regarded as asynchronous to the program flow given the complex relationship between the events that set these bits and the program flow. These bits are typically cleared by the SW during an exception service routine. DOVF can be cleared outside of an exception service routine for polling usage.
Chapter 4 Emulation and Debug (EOnCE) The SC140 core provides board and chip-level testing capability through two on-chip modules: • Enhanced on-chip emulation (EOnCE) module • Joint test action group (JTAG) test access module These modules are accessed through the JTAG or EOnCE port. The EOnCE module provides a means of non-intrusive interfacing with the SC140 core and its peripherals, enabling users to examine registers, memory, or on-chip peripherals.
Overview of the Combined JTAG and EOnCE Interface In addition, the EOnCE: • Reduces system intrusion when debugging in real time. • Reduces the use of general-purpose peripherals for debugging I/O activities. • Standardizes the process of system-level debugging across multiple target platforms. • Provides a rich set of watchpoint features with real-time operation. • Provides non-intrusive access capability to peripheral registers (for read and write) while in debug state.
Overview of the Combined JTAG and EOnCE Interface tdi EOnCE1 EOnCE2 choose_tdi EOnCEn-1 EOnCEn choose_clock_dr eonce_reset tck tdo tdi JTAG TAP Controller Figure 4-1. JTAG and EOnCE Multi-core Interconnection To access the EOnCE module of each of the cores through the JTAG port, it is important to know the following: • The JTAG scan paths • The JTAG instructions • The EOnCE control register value 4.2.
Overview of the Combined JTAG and EOnCE Interface Table 4-2. JTAG Instructions (Continued) B4 B3 B2 B1 B0 Instruction Description 0 0 1 0 0 HIGHZ Selects the Bypass Register. Disables all device output drivers and forces the output to high impedance (tri-state) as per the IEEE specification. 0 0 1 1 0 ENABLE_EONCE Selects the EOnCE registers. Allows to perform system debug functions.
Overview of the Combined JTAG and EOnCE Interface TMS=1 Test-Logic-Reset TMS=0 TMS=0 TMS=1 TMS=1 Select-DR-Scan Run-Test/Idle TMS=0 TMS=1 TMS=0 TMS=1 Capture-DR TMS=0 Capture-IR TMS=0 TMS=0 Shift-DR TMS=0 Shift-IR TMS=1 TMS=1 Exit1-DR Exit1-IR TMS=0 TMS=0 TMS=0 Pause-DR TMS=0 Pause-IR TMS=1 TMS=1 TMS=0 TMS=1 Select-IR-Scan Exit2-DR TMS=1 TMS=0 TMS=1 Update-DR TMS=1 Exit2-IR TMS=1 TMS=1 Update-IR TMS=1 TMS=0 TMS=0 Figure 4-2. TAP Controller State Machine Table 4-3.
Overview of the Combined JTAG and EOnCE Interface The first action that occurs when either block is entered is a Capture operation. The Capture-DR state captures the data into the selected serial data path, and the Capture-IR state captures status information into the instruction register. The Exit state follows the Shift state when shifting of instructions or data is complete.
Overview of the Combined JTAG and EOnCE Interface SC140 CORE 1 CORE n EOnCE EOnCE Choose Choose ~ ~ TDI SC140 to TDO mux JTAG Controls Figure 4-3. Cascading Multiple EOnCE Modules 4.2.5 DEBUG_REQUEST and ENABLE_EONCE Commands After the CHOOSE_EONCE instruction completes, DEBUG_REQUEST and ENABLE_EONCE instructions can be executed. More than one such instruction can execute, and other instructions can be placed between them and also between them and the CHOOSE_EONCE instruction.
Overview of the Combined JTAG and EOnCE Interface Execute CHOOSE_EONCE instruction in JTAG Write JTAG data in order to choose the EOnCE Execute ENABLE_EONCE instruction in JTAG EOnCE is connected to the TDO. EOnCE is ready to get command in ECR. . Write command into ECR register via shift-dr - update-dr Bits 0-6 = offset of the chosen register. Bits 7-8 = 00 Bit 9 = 0 when write command, and 1 when read command The chosen register is selected.
Overview of the Combined JTAG and EOnCE Interface (A) EOnCE register write operation through JTAG 7 0 EOnCE register TDI (relevant bits) (don’t care bits) TDO internal shift register (B) EOnCE register read (capture) operation through JTAG 23 0 7 EOnCE register 24 zeros TDI 0 (bits captured as zero) (relevant bits) TDO internal shift register Figure 4-5.
Main Capabilities of the EOnCE Module 4.3 Main Capabilities of the EOnCE Module While the JTAG port provides board test capability, the EOnCE module provides emulation and debug capability. The EOnCE module permits full-speed, real-time, and non-intrusive emulation for a target system or a SC140 development board. This section describes the environment in which the EOnCE module is used for debugging a real-time embedded application.
Main Capabilities of the EOnCE Module 4.3.2 EOnCE Dedicated Instructions The instruction set of the SC140 core architecture includes three instructions which are dedicated to the EOnCE module and available for debugging purposes: • DEBUG — Upon decoding by the core, if the SDD bit in EMR is clear, the core enters the debug processing state. • DEBUGEV — This instruction indicates to the EOnCE that a debug event has occurred.
Main Capabilities of the EOnCE Module If the core is in execution state or in a power-saving state (stop or wait) when a debug request is issued, the core enters debug state. In special cases where the core is frozen (for example, during external access) the core enters debug state after restart of the core clock. To exit debug state, set the EX bit in the EOnCE command register (ECR) by the EOnCE command shifted through the JTAG port. See Section 4.7.1, “EOnCE Command Register (ECR),” for more details.
Main Capabilities of the EOnCE Module Execute CHOOSE_EOnCE and DEBUG_REQUEST instructions using the JTAG port. EOnCE is in debug state and ready to receive a command in the ECR register. Write a command into the ECR register with the address of the ERCV register. The ERCV register is selected. Write the program data to be transferred into the memory of the ERCV register. The ERCV register is written with the program data.
Main Capabilities of the EOnCE Module 4.3.7 EOnCE Events An emulator event is an occurrence that the emulator can count or trace, or that can cause the emulator to perform an action. Examples: A core clock cycle is an example of an event because the emulator can count core clock cycles. The execution of a DEBUGEV instruction is another example of an event because the emulator can perform an action—such as placing the core in debug state—whenever the core executes a DEBUGEV instruction.
Main Capabilities of the EOnCE Module 4.3.8 EOnCE Actions An emulator action is something that the EOnCE does as a result of an emulator event. Example: Action Placing the core in debug state is an example of an action. The EOnCE can perform the following actions: • Place the core in debug state. • Generate a debug exception or external interrupt request • Enable program tracing. • Disable program tracing. • Enable the counter. • Enable the EDCD. • Enable EDCAs. 4.3.
EOnCE Enabling and Power Considerations Table 4-5. EOnCE Event and Action Summary Event type Counted trace trigger Debug state Debug exception Enable tracing Disable tracing Clock + - - - - - Trace Transaction + - - - - - EC + - - - - - MARK - + - - - - COF - + - - - - Other actions 4.
EOnCE Module Internal Architecture • Reading and writing EOnCE registers from the software • Real-time JTAG port access • Real-time data transfer • Executing instructions while in debug state • Samples core PC information in various states Figure 4-8 displays the EOnCE controller block diagram.
EOnCE Module Internal Architecture Table 4-6. EOnCE Controller Register Set Register Name Description PC_NEXT PC of the next execution set PC_LAST PC of the last execution set PC_DETECT PC breakpoint address register The functionality of the EOnCE controller registers is described in Section 4.7, “EOnCE Controller Registers.” 4.5.
EOnCE Module Internal Architecture Figure 4-9 shows a block diagram of the event counter. Count Value 31-bit Event Counter System Clock Inst Execution ECNT_VAL Event0-5 EventD Count Event Count Selector Trace DEBUGEV EC0-1 External EDCA6,7 event 31-bit Extension Counter Control Register ECNT_CTRL ECNT_EXT Figure 4-9. Event Counter Block Diagram ECNT_VAL and ECNT_EXT are 32-bit registers, but their values are limited to 31 bits; their MSB is always zero. Their range is from zero to $7FFF FFFF.
EOnCE Module Internal Architecture 4.5.
EOnCE Module Internal Architecture In the case of read-modify-write commands, the EDU generates an event even if the read-modify-write command failed. Figure 4-10 shows the event detection unit block diagram. EED EE[5..0] PC, XABA, XABB Address Buses Data Buses XDBxx EDCA#0 EDCA#1 EDCA#2 EDCA#5 EDCD EventD Event0 Event1 Event2 Event5 Count event from EDCA6,7 (ext.) Event6,7 (external) Count event (from Counter) Debug State Event Selector Debug Exceptio Enable Trace Disable Trace Figure 4-10.
EOnCE Module Internal Architecture 4.5.3.1 Address Event Detection Channel (EDCA) One of the main elements of the EDU is the EDCA. An EDCA has all the logic required to detect address values according to a user-programmable configuration. There is no support for breakpoints on the PC of an instruction that is not the first instruction of the execution set. All PC detections are done at execution set level. XABB XABA PC Figure 4-11 shows the EDCA block diagram.
EOnCE Module Internal Architecture • Greater than Each EDCA includes four registers, as shown in Table 4-8. Table 4-8. EDCA Register Set Register Name Description EDCAi_CTRL EDCA control register EDCAi_REFA EDCA reference value register A EDCAi_REFB EDCA reference value register B EDCAi_MASK EDCA mask register The functionality of the EDCA registers is described in Section 4.9.1, “Address Event Detection Channel (EDCA).
EOnCE Module Internal Architecture 4.5.3.2 Data Event Detection Channel (EDCD) The EDCD is one of the main elements of the EDU. It has all the logic required to detect data values according to a user-programmable configuration. XDBAR XDBAW XDBBR XDBBW Figure 4-12 shows the EDCD block diagram. MUX Access Type Select EED Event 0..5 EDCD MASK Register External Event 6,7 Count Event Two Comparators EventD Reference Value Register Control Register Figure 4-12.
EOnCE Module Internal Architecture 4.5.3.3 Optional External Event Detection Address Channels The EDU has two ports to optional external event detection channels named EDCA6 and EDCA7. If needed, the system designer may add additional event detection capabilities to the EOnCE using these ports.
EOnCE Module Internal Architecture Event0..Event5 External Event6, Event7 EventD Count event Debug State Debug Exception Enable Trace Disable Trace DEBUGEV EE[4:0] ES The ES block diagram is shown in Figure 4-13. Figure 4-13. Event Selector Block Diagram The ES can be used to detect reading or writing data from/to a certain data address by using the EDCD to detect the data, an EDCA to detect the address (on XABA, XABB, or both), and the ES to generate an EOnCE event if both events occur.
EOnCE Module Internal Architecture — Return from exception instructions • Other change of flow events: — Interrupts — Hardware loops • Any execution set • Mark instructions For each change-of-flow event, a package of information is stored in the trace buffer, including the PC of the source, the PC of the destination, and, optionally, the value of the event counter and the counter extension. The EOnCE trace unit: • Supports a circular hardware trace buffer external to the core.
EOnCE Module Internal Architecture Figure 4-14 displays a block diagram of the trace unit. Trace Unit Trace Unit PC Controller Hardware Loops MARK Change of Flow Interrupts Normal Execution Set Enable Trace Control Register Read Pointer Disable Trace Strobes Data Address Write Pointer Trace Buffer (TB) Off-Core Figure 4-14. Trace Unit Block Diagram 4.5.5.1 Change of Flow and Interrupt Tracing The trace logic can be configured to trace change of flow instructions.
EOnCE Module Internal Architecture — BREAK — CONT, CONTD — SKIPLS Note that TRAP, and ILLEGAL are traced as interrupts, not as change of flow instructions. When tracing interrupts, a source destination address pair is also traced. The source address normally reflects the PC of the last executed execution set, and the destination address reflects the PC of the interrupt vector.
EOnCE Register Addressing Table 4-11. Trace Buffer Register Set Register Name TB_CTRL Description Trace buffer control register TB_RD Trace buffer read pointer register TB_WR Trace buffer write pointer register TB_BUFF Trace buffer virtual register The functionality of the trace unit registers is described in Section 4.11, “Trace Unit Registers.” 4.6 EOnCE Register Addressing The various units described above use a large number of registers.
EOnCE Register Addressing Table 4-12 displays the EOnCE register addressing offsets. Table 4-12.
EOnCE Register Addressing Table 4-12.
EOnCE Register Addressing Table 4-12.
EOnCE Register Addressing The ACK bit could be checked on TDO by executing a “neutral” JTAG EOnCE command such as “ENABLE_EONCE”. Only after it was verified with the ACK bit that the previous access was accepted by the core, the next register could be accessed. This check should be performed also for accessing the ECR. 4.6.3 Real-Time Data Transfer The EOnCE controller enables the core software to transmit data from the core to the host as well as to receive data sent from the host to the core.
EOnCE Register Addressing Accessibility of the registers through JTAG is the same as from software with the following exceptions: • The ETRSMT register is only readable only using the JTAG port. • The ERCV registers are only writable using the JTAG port. • PC_LAST and PC_NEXT can only be read by the JTAG port. • The CORE_CMD register can only be written by the JTAG port in debug state.
EOnCE Controller Registers 4.7 EOnCE Controller Registers A list of the EOnCE controller registers is given in Table 4-6 on page 4-17. The sections that follow describe these registers. 4.7.1 EOnCE Command Register (ECR) The ECR is a write-only 16-bit shift register that receives its serial data from the TDI input signal. This register is accessed only using JTAG. Figure 4-15 displays the bit configuration of the ECR.
EOnCE Controller Registers Table 4-13. ECR Description (Continued) Name Description Settings GO Bit 8 Go Command — If this bit is set, there are two possible modes of execution: • When used together with writing or reading a register (except for CORE_CMD), this register is first written or read, and then the next instruction in the pipeline is executed. When used together with the NOREG register, only the next instruction in the pipeline is executed.
EOnCE Controller Registers BIT 15 DRSW 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 DREE DREE DREE DREE DREE DRCOUNDRED DRED DRED DRED DRED DRED DRED DRED DREDCD 4 3 2 1 0 TER CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 TYPE r r r r r r r r r r r r r r r r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The shaded bits are reserved and should be initialized with zeros for future software compatibility. The reset values for REVNO and CORETP (shown as x) are derivative-dependent.
EOnCE Controller Registers Table 4-14. ESR Description (Continued) Name Description TBFULL Bit 25 Trace Buffer Full — Indicates that the trace buffer of EOnCE is full. In order not to lose addresses when TBFDM and IME bits in the EMCR register are set (when TB is full), the bit causes a debug exception. The TBFULL bit is set when the TB write pointer equals TB-size minus 15, where TB-size is defined for each SoC derivative.
EOnCE Controller Registers Table 4-14. ESR Description (Continued) Name Description DREE3 Bit 13 Debug Reason is EE3 — Set when the core enters debug state or executes a debug exception as a result of EE3 assertion. It is cleared by the EOnCE when the core exits debug state, or when the DIS bit in EMCR is reset by the user. DREE2 Bit 12 Debug Reason is EE2 — Set when the core enters debug state or executes a debug exception as a result of EE2 assertion.
EOnCE Controller Registers 4.7.3 EOnCE Monitor and Control Register (EMCR) The EMCR is a 32-bit register. Bits 31–16 are read/write control bits. Bits 15–0 are sticky status bits and can only be written with zeros. Writing them with a one has no effect. The sticky status bits of the register indicate an event generated by the EOnCE EDU. Figure 4-17 displays the configuration of EMCR.
EOnCE Controller Registers Table 4-15. EMCR Description (Continued) Name Description DEBUGERST Bits 21–18 Debugger Status Information — If several applications (debugger processes) try to connect to the core, unaware of each other, DEBUGERST bits serve as flags. Reset once the core is powered, they can be set/reset by the application as an occupy signal. The debugger may use these bits to reserve the core for its use.
EOnCE Controller Registers 4.7.4 EOnCE Receive Register (ERCV) ERCV is a 64-bit shift register that can be written from the TDI input signal. The register can be read by the software as two 32-bit registers. The ERCV register has to be read in a specific order with the Least Significant Part first. The Least Significant Part read is optional, but the Most Significant Part read is required to clear the RCV bit in the ESR. ERCV is used to transfer data from the host.
EOnCE Controller Registers 4.7.6 EE Signals EE signals are general-purpose core interfaces which serve as input or output to the EOnCE. They can be connected off-chip or to a specific on-chip peripheral. This connection is defined by the SoC derivative. In some systems, the EE signals are not connected to an external signal. 4.7.6.1 EE Signals as Outputs EE signals can be used to indicate internal EOnCE events to devices outside the core.
EOnCE Controller Registers 4.7.6.1.4 Status Bit of the ETRSMT Register The EE4 signal can be programmed to serve as an indication of data availability in the ETRSMT register. This capability provides interrupt driven transfers to the host debugger. If the EE4 signal is programmed in this way, each time the core performs the transfer (and writes to the ETRSMT register), the EE4 signal is asserted and the host is interrupted.
EOnCE Controller Registers The functionality of EE signals when programmed as an input depends on the programming of the EDU and the ES. See Section 4.9, “Event Detection Unit (EDU) Channels and Registers,” for further details. Table 4-16 describes the EE_CTRL fields. Table 4-16. EE_CTRL Description Name Description Settings EEDDEF Bit 15 EED Definition — Programs the EED signal. As an output of the EED, the EEDDEF bit can indicate detection by the EDCD, working as a toggle.
EOnCE Controller Registers Table 4-16. EE_CTRL Description (Continued) Name Description Settings EE2DEF Bits 5–4 EE2 Definition — Programs the EE2 signal. Programmed as an output of the EOnCE, EE2 can indicate detection by EDCA2, working as a toggle.
EOnCE Controller Registers 4.7.7 Core Command Register (CORE_CMD) The CORE_CMD register is used to execute instructions in the core while in debug state. The external host writes the instruction into the CORE_CMD register as described in Section 4.2.6, “Reading/Writing EOnCE Registers Through JTAG.” The EOnCE commands written into the ECR must be Write CORE_CMD and GO. After writing the instruction into the CORE_CMD register, the core executes it without leaving debug state.
EOnCE Controller Registers 4.7.8 PC of the Exception Execution Set (PC_EXCP) PC_EXCP enables the user to determine exactly which execution set caused an imprecise internal Illegal or DALU overflow exception. It is a read-only register that is accessed through the JTAG port or by core software. In the case of an illegal instruction, illegal execution set or DALU overflow, the PC of the execution set is saved in the PC_EXCP register.
Event Counter Registers • This event was programmed in ESEL_DM. • The debug reason bits (DREDCA0-5, DREDCD) in ESR indicate that the data detection event was part of the reason to enter debug state. ESR should be checked because ESEL_DM may be programmed to enter debug state for other reasons that do not cause sampling into PC_DETECT. This ESR check should match the way the data memory events were programmed to combine to a debug entry condition in ESEL_CTRL.
Event Counter Registers ascertain the number of cycles needed by a device to get from a starting address to an ending address, in the following manner: 1. Write $7FFF FFFF to the ECNT_VAL register. 2. Configure ECNT to count the internal clock. 3. Program ECNT to be enabled upon EDCAi detection. 4. Program EDCAi to detect the starting address. 5. Program EDCAj to detect the ending address. 6. Program ES to generate a debug exception upon EDCAj detection. The following stages are: 1.
Event Counter Registers Table 4-18. ECNT_CTRL Description (Continued) Name Description Settings ECNTEN Bits 7–4 Event Counter Enable — Used to enable the ECNT operation. When ECNTEN is set to 1111, ECNT is operational and will count events according to ECNTWHAT bits, which select the source for that count.
Event Counter Registers 4.8.3 Extension Counter Value Register (ECNT_EXT) This is a 32-bit register that is used in the extended mode of operation to count the number transitions from 1 to 0 in the ECNT_VAL register. See Section 4.5.2, “Event Counter,” for further details. The ECNT_EXT register counts up. Reset writes zeros to this register. Software can write the register when new counting is started. The MSB is always zero, so the count is from $0000 0000 to $7FFF FFFF.
Event Detection Unit (EDU) Channels and Registers 4.9 Event Detection Unit (EDU) Channels and Registers The various event detection channels and corresponding registers are described in the sections that follow. 4.9.1 Address Event Detection Channel (EDCA) The EDCA can be used to detect the following: • Program breakpoint, specified on a specific PC value or range • Data address breakpoint, specified on a specific data address or range.
Event Detection Unit (EDU) Channels and Registers Table 4-19. EDCA_CTRL Description (Continued) Name Description Settings EDCAEN Bits 13–10 Event Detection Channel (EDCAi) Enable — Used to enable or disable event detection channels. When it is enabled, it continues to operate until it is explicitly disabled by writing 0000 into EDCAEN bits, or EDCAEN bits are changed for another enabling condition. The channel remains disabled until a new enabling condition occurs. 0000 =.EDCAi is disabled. 0001 =.
Event Detection Unit (EDU) Channels and Registers Table 4-19.
Event Detection Unit (EDU) Channels and Registers the range on bus B, and the two EDCA events should be OR-ed in the event selector. The apparent alternative of detecting the upper range boundary on both buses and the other EDCA to detect the lower range boundary on both buses (AND-ing them in the event selector) may produce erroneous results, for example if two unrelated parallel accesses match the conditions by chance.
Event Detection Unit (EDU) Channels and Registers 4.9.2 Data Event Detection Channel (EDCD) In order to set a watchpoint on a given data value, the user should: • Write the watched value into the EDCD_REF. • Enter a write mask into the EDCD_MASK. • Specify the type of access (read or write) in the EDCD_CTRL. • Specify the data type (byte/word/long) in the EDCD_CTRL. • Enable the event detection unit in EDCD_CTRL, as the last action.
Event Detection Unit (EDU) Channels and Registers Table 4-20. EDCD_CTRL Description (Continued) Name Description Settings AWS Bits 9–8 Access Width Selection — Determines the width of the data access that should be watched. The different width types are summarized in the settings column. 00 = Byte 01 = Word 10 = Long 11 = Reserved In byte access mode, only the eight LSB bits of the masked data are compared with the eight LSB bits of the EDCD_REF register.
Event Detection Unit (EDU) Channels and Registers Table 4-20. EDCD_CTRL Description (Continued) Name Description Settings EDCDEN Bits 6–3 EDCD Enable — Used to enable or disable the EDCD. When enabled, EDCD continues to operate until it is explicitly disabled by writing 0000 into EDCDEN bits, or when EDCDEN bits are changed for another enabling condition. The channel remains disabled until a new enabling condition occurs. 0000 =.EDCD is disabled. 0001 = EDCD is disabled, but is.
Event Selector (ES) Registers 4.9.2.2 EDCD Reference Value Register (EDCD_REF) EDCD_REF is a 32-bit register used to hold a reference value to be compared by the EDCD comparator. EDCD_REF is used by the EDCD comparator. If a byte (8 bits) or a word (16 bits) is to be written into the EDCD_REF, it should be LSB-aligned. 4.9.2.3 EDCD Mask Register (EDCD_MASK) EDCD_MASK is a 32-bit register that allows the masking of any of the bits in the data bus value that is compared.
Event Selector (ES) Registers Figure 4-23 displays the bit configuration of ESEL_CTRL. BIT 7 6 5 4 3 SELDTB SELETB 2 1 BIT 0 SEDLDI SELDM TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 The shaded bits are reserved and should be initialized with zeros for future software compatibility. Figure 4-23. Event Selector Control Register (ESEL_CTRL) The ESEL_CTRL fields are described in Table 4-21. Table 4-21.
Event Selector (ES) Registers For each outcome, the individual events could be AND-ed or OR-ed as specified in ESEL_CTRL. When the ESEL_CTRL is configured as “OR” for a certain outcome, all events could be enabled as needed. However, AND-ing events is more restricted, since the respective events that are AND-ed have to be related so that the combination will be meaningful.
Event Selector (ES) Registers 4.10.3 Event Selector Mask Debug Exception Register (ESEL_DI) This 16-bit register has one bit for each source of event selection. Setting the appropriate bit enables the related source to cause a debug exception. Figure 4-25 displays the bit configuration of ESEL_DI.
Trace Unit Registers 4.10.5 Event Selector Mask Disable Trace Register (ESEL_DTB) This 16-bit register has one bit for every source of the ES. Setting the appropriate bit configures the related source to cause a disable trace. Figure 4-27 displays the bit configuration of ESEL_DTB.
Trace Unit Registers In addition, the counter values could be added to the trace package of each trace event, thereby allowing to monitor the elapsed cycles between trace events. The possible counter tracing modes are: • TCOUNT upon a trace event, trace the counter value (ECNT_VAL) • TCNTEXT upon a trace event, trace the extension counter value (ECNT_EXT). This mode is usefull only with the TCOUNT mode. Activating the TCOUNT mode adds a 32-bit entry to the traced package upon each trace event.
Trace Unit Registers In order to ensure that the LSB value of the trace data is always valid according to this convention, the values of the 31-bit event counter and event counter extension are traced shifted one position to the left, occupying positions [31:1] of the traced 32-bit value. Hence for example a counter value of 0x8 will be traced as 0x10. The debugger SW should account for this shift when interpreting trace data.
Trace Unit Registers Table 4-23. TB_CTRL Description (Continued) Name Description Settings TLOOP Bit 5 Trace Loops Mode — Enables tracing the addresses of hardware loops. When the bit is set, every change of flow resulting from a loop puts the last address of loop (LA) into the trace buffer. In the case of a long loop, the start address of loop (SA) is put into the trace buffer after LA. If the loop has a number of iterations N, the LA and SA of the loop are written to the trace buffer (N-1) times.
Trace Unit Registers 4.11.2 Trace Buffer Read Pointer Register (TB_RD) TB_RD is a 16-bit register that points to the location in the RAM buffer from which the next value is read. The register is reset when the trace buffer is enabled. 4.11.3 Trace Buffer Write Pointer Register (TB_WR) TB_WR is a 16-bit register that points to the next location available for writing into the buffer. The register is reset when the trace buffer is enabled. 4.11.
Trace Unit Registers 4-70 SC140 DSP Core Reference Manual
Chapter 5 Program Control This chapter describes the program control features for the SC140 including: • Pipeline • Instruction grouping • Instruction timing • Hardware loops • Stack support • Processing states • Exception processing The SC140 core, being a multiple ALU processor, has special hardware that can issue up to two AGU and four DALU instructions at the same time.
Pipeline To support parallel execution, the core uses a variable length execution set (VLES) architecture with a static grouping mechanism. Several instructions can be grouped together to form an execution set, which is dispatched to the execution units in parallel. The core contains four ALUs and two AAUs and thus execution set can contain up to four DALU instructions and two AGU instructions with a maximum of eight words. For many instructions, an execution set takes only one clock cycle.
Pipeline Table 5-1 shows a typical pipeline flow. For the machine to advance to the next instruction cycle, all of the five operations at the current cycle must be completed. Table 5-1.
Pipeline 5.1.1.1 Instruction Pre-Fetch and Fetch The first two stages of the pipeline are the pre-fetch and fetch stages. These two stages combined are responsible for the program memory read of the fetch set. Each fetch set contains eight instruction words. In the pre-fetch stage, the address of the fetch set is driven into the program address bus (PAB) along with the read strobe. This enables the memory read process.
Instruction Grouping 5.1.1.4 Execution During the execution stage, all DALU arithmetic calculations are performed by: • Reading the data operands from source registers • Performing arithmetic operations on the data • Writing the results to destination registers 5.2 Instruction Grouping The SC140 instruction set architecture is built around a 16-bit instruction set for optimal code density and performance.
Instruction Grouping In the execution set described above, six SC140 instructions are grouped together. When executed, the following occurs: 1. The contents of the D0 and D1 registers are multiplied fractionally. The result is added to the content of the D7 data register. The final result is then stored in the D7 data register. 2. The contents of the D3 and D4 registers are multiplied fractionally. The result is added to the content of the D6 data register.
Instruction Grouping Prefix grouping can group together any instructions that have available execution units. However, the prefix method requires one additional instruction word per execution set. Serial grouping is more compact, but only supports a subset of instructions. The assembler automatically selects serial or prefix grouping based on the instructions in each execution set so that the encoding length is minimized. The grouping method selection algorithm is described in Figure 5-3. 5.2.1.
Instruction Grouping 5.2.2 Prefix Types The SC140 architecture supports 2 types of prefix instructions, each is used to convey a subset or all of the following information about the VLES: • The number of instructions that are grouped together in the execution set. • Conditional execution of the whole set or a subgroup of the set (encoding the IFT/IFF/IFA prefix instructions). • Looping information for supporting hardware loops (encoding the LPMARKA and LPMARKB bits).
Instruction Grouping 5.2.2.2 One-Word Low Register Prefix The One-Word Low register prefix encodes all information of the two-word prefix, except for encoding for high registers. It is used whenever no instruction in the VLES uses a high register, and a prefix is needed for one of the other reasons: instruction grouping that cannot be done with serial grouping, conditional execution of the whole VLES or a sub-group, and encoding for HW loop support. 5.2.
Instruction Grouping Table 5-4. Conditional IFc Syntax Assembly Syntax Meaning IFT inst [inst] IFF inst [inst] Execution of subgroup1 if T==1 Execution of subgroup2 if T==0 IFT inst [inst] Execution of the whole group if T==1 IFF inst [inst] Execution of the whole group if T==0 IFT inst [inst] IFA inst [inst] Execution of subgroup1 if T==1; always execute subgroup2 IFF inst [inst] IFA inst [inst] Execution of subgroup1 if T==0; always execute subgroup2 5.2.
Instruction Grouping Yes Are registers D8-D15 or R8–R15 used in the execution set? Use a two-word prefix. No Continue Is the set conditionally executed (IFc), or does it convey looping information? Yes Use a one-word low-register prefix. No Continue Yes Does the execution set contain only one instruction? No prefix is needed.
Instruction Grouping 5.2.5 Instruction Reordering Within an Execution Set The SC140 can execute up to four DALU instructions and up to two AGU instructions concurrently. These instructions are grouped together in an execution set and dispatched in parallel to the execution units by the PDU. Since the execution units of each type are identical (in principle), any ALU can receive any DALU instruction. As well, any AAU can receive any AGU instruction.
Instruction Grouping Example 5-3. Execution Set with Three One-word and Two Two-word Instructions Position 0 1w prefix 1 2 2w - - ext 3 1w 4 5 2w - - ext 6 1w 7 1w The instruction reordering by the assembler operates as follows: • Instruction words of an execution set must be encoded contiguously. No encoding gaps are allowed. • Up to two AGU instructions may appear in an execution set. One must encode in an even position. The other must encode in an odd position.
Instruction Timing Given the execution set in Example 5-5, the assembler adds a NOP to the object code for correct encoding. 5.3 Instruction Timing Most of the instructions used for DSP algorithms take one cycle to execute. They can be grouped together and executed simultaneously. Other instructions, such as those used in the control portion of the application, may take more than one cycle to execute. Some of these multi-cycle instructions are change-of-flow (COF) instructions.
Instruction Timing Table 5-5 summarizes the timing of the various categories of SC140 instructions. Table 5-5. Instruction Categories Timing Summary Basic Instruction Category Example/Condition DALU MAC D0, D1, D2 1 Data move with simple addressing MOVE.W (R0)+N2, D3 1 Data move with address pre-calculation MOVE.W (R5+N0), D4 2 BMU with simple addressing BMSET.W #$1010, (R0) 2 BMU with address pre-calculation BMSET.
Instruction Timing 5.3.1.1 DALU Instruction Timing DALU instructions are the most timing-critical instructions in the DSP algorithm kernels, taking only one cycle to execute. DALU instructions consist, among others, of the following: • Multiply-accumulate (MAC) • Multiply (MPY) • ADD • SUB • Compare • Shift • Test 5.3.1.2 Move Instruction Timing Most of the move instructions take one cycle to execute, assuming a zero-wait-state, contention-free memory.
Instruction Timing 5.3.2 Change-Of-Flow Instruction Timing The change-of-flow (COF) instructions include branches, jumps, traps, returns, conditional branches, conditional jumps, and loop control instructions that affect the program counter and/or software stack. Program control instructions may affect or be affected by status register bits as specified in the instruction.
Instruction Timing Table 5-6.
Instruction Timing 5.3.2.2 Delayed COF When a change-of-flow instruction is executed, the core must wait for the pipeline to fill, starting with a new pre-fetch from memory. A delay slot is the next VLES after a delayed change-of-flow instruction. Since it is possible to use the delay slots of the change-of-flow operation to continue the execution of the previously fetched instructions, special delayed instructions are added to the instruction set.
Instruction Timing change-of-flow occurs to a new execution set spread over two fetch sets, two new fetches must be read from memory. • The subroutine call instructions (JSR, JSRD, BSR, and BSRD) need one free cycle in order to push the return PC and SR onto the stack. Normally, a subroutine call instruction uses one of the idle cycles while the pipeline is filling up so that no stall occurs.
Instruction Timing Table 5-8. Number of Cycles Needed by Change-of-Flow Instructions (Continued) Instruction Number of Cycles Minimum Number of Cycles Condition RTE 5 6 Shadow SP is valid. Shadow SP is not valid. RTED 5 – Cd Shadow SP is valid. Shadow SP is not valid. 6 – Cd RTS 3 5 6 RTSD 3 – Cd 3 – Cd RAS is valid. RAS is not valid and shadow SP is valid. RAS is not valid and shadow SP is not valid. 1 2 5 – Cd 6 – Cd RAS is valid and shadow SP is valid.
Instruction Timing The read or write for each memory access can be mapped to the execution cycle in which they operate as follows: • Cycle 1 — Move read or write without address pre-calculation. — Bit mask read without address pre-calculation. — Pop read with shadow SP valid. • Cycle 2 — Move read or write with address pre-calculation. — Bit mask read with address pre-calculation. — Bit mask write without address pre-calculation. — Pop read with shadow SP invalid.
Instruction Timing cycle-by-cycle basis. Accesses issued on the same cycle may cause a contention. The cases where contentions will occur and how many stall cycles will be introduced depends on the definition of the memory system, which may be different than that described below. Example 5-8 provides an execution set that does not cause contention since the instructions execute in different cycles. Example 5-8. Parallel Execution of Two Move Instructions MOVE.L D0,(R0) MOVE.
Instruction Timing Example 5-11 shows the parallel execution of a bit mask and a pop instruction. The example distinguishes the cases of a valid and invalid shadow SP (see Section 5.5.4, “Shadow Stack Pointer Registers.” ) If the shadow SP is not valid as in Case A (meaning the address of the stack pointer was overwritten), the address of the stack pointer (SP–8) must be pre-calculated from the value in SP. There is no contention since the two read operations occur at different cycles.
Hardware Loops 5.4 Hardware Loops One of the most important features of a DSP algorithm is efficient loop execution. The SC140 core has a fully optimized looping mechanism, which enables loop execution with up to four levels of loop nesting. The loop programming model is part of the PSEQ programming model, and includes four pairs of registers that specify the start address of the loop as well as the number of times the loop is to be executed. 5.4.
Hardware Loops 5.4.1.2 Loop Counter Registers (LCn) The LCn registers are 32-bit read/write registers used to define the number of times each loop is to be executed. LCn always holds a 32-bit signed value. This means that the largest number of loop iterations is 231-1. The DOENn or DOENSHn instructions initialize the LCn register. 5.4.1.3 Status Register (SR) Loop Flag Bits Certain status bits in the SR are associated with hardware loop initiation and execution.
Hardware Loops Table 5-9 illustrates the location of these marker bits and their functionality in both short and long loops. Refer to Appendix A, “SC140 DSP Core Instruction Set,” for further details. Table 5-9. LPMARKA and LPMARKB Bits in Short and Long Loops LPMARKA LPMARKB Loop Type Location Functionality Location Functionality Short loop SA Identifies a single-execution set loop. Causes no timing overhead. SA Identifies a two-execution set loop. Causes no timing overhead.
Hardware Loops 5.4.4 Loop Nesting The core has four hardware loops (LOOP0, LOOP1, LOOP2 and LOOP3) to execute up to four levels of loop nesting. A loop can only be nested within a loop that has a lower index. In a nested loop structure, more than one loop can be enabled at one time. A loop is enabled when its corresponding LFn is set. The LF3–LF0 bits indicate which of the loops are enabled. The enabled loop with the highest index is defined as the “active loop”. Only one loop can be active at a time.
Hardware Loops 5.4.6 Loop Control Instructions Table 5-10 lists the loop instructions. Table 5-10. Loop Control Instructions Instruction Operation DOSETUPn
Hardware Loops instruction to the last address, the LPMARKA bit will be placed at LA in addition to the LPMARKB bit at LA-2. In nested loops, if the LPMARKA and LPMARKB bits occur in the same execution set, the LPMARKA bit belongs to the inner loop, and the LPMARKB bit belongs to the outer loop. The following is an example of a long loop. Example 5-12. Long Loop dosetup0 _start0 doen0 #$10 move.
Hardware Loops The following is an example of a short loop in one execution set. Example 5-15. Short Loop, One Execution Set doensh0#$10 ... loopstart0 mac d0,d1,d2 loopend0 SA, LA move.w (r0)+,d0 Loop body LPMARKA The following is an example of a nested loop. Example 5-16. Nested Loop dosetup0 _start0 dosetup1 _start1 doen0 #$10 ... loopstart0 _start0 SA loop 0 SA LA LA loop 1 loop 1 loop 0 bmset #$ff01,d0 doen1 d7 clr d2 skipls _end1 loopstart1 _start1 mac d0,d1,d2 move.
Stack Support 5.4.7 Loop Timing If the loop starting address is not aligned (meaning that the first execution set is spread over two fetch sets), one stall cycle is added to the loop execution on each iteration of the loop. In every other case, no stall cycles are added to the loop execution time. A loop may be aligned with the assembler directive FALIGN, which when placed just before the LOOPSTART, will cause the assembler to insert NOP instructions in order to align the first execution set of the loop.
Stack Support Memory space is required for interrupts because any task may be active when an interrupt occurs. The ISR pushes registers on the current stack and may also allocate local variables on the current stack. Since it is not known which task is being executed when an interrupt occurs, each task stack must be increased by the maximum ISR memory use. In both situations, the memory is used only once, but it is allocated in more than one location. RTOS functions return without switching tasks.
Stack Support 5.5.3 Stack Support Instructions The core provides push and pop instructions that reference the active stack pointer (NSP or ESP). Table 5-11 describes these instructions. Table 5-11.
Stack Support Table 5-13 describes the stack memory map while performing a single or a dual push access. Table 5-13. Stack Memory Map Type Memory Location X+4 Memory Location X Single push - even register Unused Even operand Single push - odd register Odd operand Unused Dual push Odd operand Even operand Up to two pop instructions are supported in a single execution set.
Stack Support 5.5.5 Fast Return from Subroutines The SC140 supports a mechanism for speeding up the execution of the return from subroutine (RTS) instruction, using a return address stack (RAS) register. The RAS is updated with the return address during the execution of a JSR or BSR instruction. Normal execution of an RTS takes five to six execution cycles.
Working Modes 5.6 Working Modes The working mode is determined by the EXP bit in theStatus Register (SR), as shown in the table below: Table 5-15. Working Modes Working Mode EXP bit Active SP Normal 0 NSP Exception 1 ESP The SC140 can operate in one of two working modes. Normal mode - Typically intended for task-related services. Works with NSP as the stack pointer. Exception mode - Typically intended for RTOS kernels, exception routines and peripheral device drivers.
Working Modes 5.6.3 Typical Working Mode Usage Scenarios The core changes its working modein different ways, depending on the protection and stack paradigm in use. The sections immediately below illustrate two common task management paradigms supported by the SC140 core, that may be used by an RTOS: Dual-stack, and Single-stack The terms “single” or “dual” stack refer to the number of stack pointer registers that are used by the system.
Working Modes 5.6.3.2 Single-stack RTOS Figure 5-9 illustrates state transitions for a single-stack-based operating system. Reset exception or external interrupt request Exception Mode EXP SP 1 ESP return from exception via RTE/D Figure 5-9. Working mode Transitions - Unprotected Single-stack RTOS Existing single-stack operating systems operate exclusively in the Exception working mode. The EXP bit is always set, making ESP the active SP for all operating system and user tasks.
Working Modes • The EXP bit in the SR is set(if not already), thereby enabling the Exception Stack Pointer (ESP) as the active SP. • The PC and previous SR are pushed on the active (ESP) stack. • The PC jumps to the Vector Base Address (VBA) + Exception Offset Address. For example, executing a TRAP instruction causes the core to enter an Exception state and begin executing instructions at VBA + 0x00, since the TRAP instruction has an exception offset address of 0x00.
Processing States 5.7 Processing States The SC140 core is always in one of the five processing states: • Execution • Debug • Reset • Wait • Stop These states are described in the sections that follow. In some states, the operation of peripherals and other blocks is affected. Note: The descriptions of the change in operation given here may be different for certain products that utilize a SC140 core. Consult the product-specific manuals for details of actions in each processing state. 5.7.
Processing States 5.7.2 Processing State Transitions The transitions between the states are summarized in the following figure. EXECUTION 14 11 8 4 5 10 DEBUG RESET 3 13 9 12 7 6 WAIT 2 1 STOP Figure 5-10. Core State Diagram Table 5-17 describes the processing state transitions shown in Figure 5-10.
Processing States Table 5-17. Processing State Transitions Processing State Transitions 1, 2, 3, 4 5 6, 7 Description Assertion of one of the core hardware reset input signals. De-assertion of reset if EE0 or a JTAG debug command is asserted during reset Entering debug state through an external request (JTAG, EE pin or system input).
Processing States 5.7.5 Debug State The debug state is a special core processing state in which the pipeline is stalled and waits for user commands from the JTAG or EOnCE. The core can enter the Debug state in the following cases: • JTAG issues a debug request is asserted, in all states. • The EE0 EOnCE signal is asserted during reset. • The EE0 EOnCE signal is asserted anytime, if programmed as a debug request input in the EE_CTRL register. • An EOnCE Debug state event occurs.
Processing States Table 5-18. Exit Wait Processing State due to an Interrupt or NMI Disable Interrupts (DI) Disable NMI (NMID) Maskable Request with IPL > core IPL as determined by the I2–I0 bits of the SR Clear (interrupts enabled) Clear or set Exit the wait processing state. Jump to the Interrupt Service Routine (ISR). Maskable Request with IPL > core IPL as determined by the I2–I0 bits of the SR Set (interrupts disabled) Clear or set Exit the wait processing state.
Exception Processing 5.8 Exception Processing Exceptions are events that interfere with the normal operation of the core and the system in which it works. The Exception working mode was designed to deal with situations such as these. In general, the prioritizing and arbitrating between all the exception sources is performed in the programmable interrupt controller (PIC), which is not part of the SC140 core.
Exception Processing Figure 5-11 below depicts the core interface to an external interrupt controller. INTERRUPT OFFSET 6 6 NMI_REQ 20 IREQ VBA 6 AUTO_VEC 3 IPL Program Sequencer PSEQ PAB Internal Exceptions SC140 Figure 5-11. Core-PIC Interface The interface signals (inputs to the core from an external interrupt controller) are described in the following list. • Maskable Interrupt Request Signal (IREQ) — Asserted to inform the core of a pending maskable interrupt request.
Exception Processing 3. The PSEQ services an exception request when ready, typically in five cycles. It may postpone an exception while a change-of-flow is executing (up to 16 cycles latency). After fetching an exception service routine base address, the core enters the exception working mode. The next PC value (namely, the address of the execution set where execution should be resumed upon the return from the exception) is pushed onto the exception stack together with the SR.
Exception Processing Table 5-19. Exception Vector Address Table Exception Address Offset Priority (0 - highest) Type Description 0x00 0 TRAP TRAP instruction 0x40 - Reserved 0x80 1 ILLEGAL ILLEGAL instruction, and illegal instruction set 0xC0 2 DEBUG DEBUG exception from EOnCE 0x100 3 Overflow DALU overflow 0x140 - Reserved 0x180 5 Auto-NMI NMI default vector 0x1C0 6 Auto-IR Interrupt default vector 5 NMI NMI External interrupts External interrupts 0x200-0xFC0 5.8.
Exception Processing 5.8.3 Maskable Interrupts 5.8.3.1 Interrupt Priority Level An external maskable interrupt is given a request IPL (between 1 and 7) by driving a 3-bit input along with the request. The core IPL is held in the I2–I0 bits of the SR. Only interrupts with a request IPL greater than the core IPL are serviced. Refer to Section 3.1.1, “Status Register (SR),” on page 3-1, for further information.
Exception Processing If two or more exceptions are pending on the same clock cycle, the one with the higher priority (as defined in Table 5-19 on page 5-49) is taken. Due to the imprecise nature of these exceptions, there may be additional exception events between the first event and its exception service routine.
Exception Processing instruction also occurred during this period, the ILIN bit in EMR will be set to indicate multiple causes for this illegal exception. If the illegal exception service routine has an illegal execution set, nested illegal exceptions will occur. 5.8.5.2 DALU Overflow The DALU overflow exception is generated whenever an overflow occurs as a result of a DALU operation.
Exception Processing 5.8.6.2 Exception Mode Execution An exception mode execution is performed in exactly the same way as a normal program flow. There is no constraint on the length of an exception routine. Table 5-20 shows the flow for the pipeline changing from normal execution to exception execution. Table 5-20.
Exception Processing Then — The execution set from the target of the exception vector is executed after ES1, and the address of ES2 is pushed as a return address to the stack. — 2 cycles are added. Else, if (ES1 is JUMP): Then – The execution set from the target of the exception vector is executed after ES0, and the address of ES1 is pushed as a return address to the stack. – 3 cycles are added.
Exception Processing Figure 5-12 provides a flow chart for Example 5-17. Is ES1 a JUMP? Yes Execute ES0. Store ES1 address. Add three cycles. Execute exception vector. No No Is ES2 a JUMP? Execute ES2. Store ES3 address. Add one cycle. Execute exception vector. Yes Yes Execute ES1. Store ES2 address. Add two cycles. Execute exception vector. Figure 5-12.
Exception Processing The following pipeline table shows the first case in Example 5-17. ES0 is a JMP with a minimum cycle count of three. ES1 and ES2 are not change-of-flow instructions. And, I1 is the first instruction at the exception vector address. The exception request is initiated in cycle 4. Table 5-21.
Chapter 6 Instruction Set Accelerator Plug-In This chapter describes the ISAP capability of the SC140 core, and how to incorporate an ISAP when using the SC140 core as part of a larger system. 6.1 Introduction An ISAP is an Instruction Set Accelerator Plug-in - a unit external to the core that the SC140 core controls using dedicated instructions that are incorporated into the SC140 program. The SC140 has an interface and dedicated encoding space that enables defining and integrating such a unit.
ISAP - SC140 Schematic Connection 6.2 ISAP - SC140 Schematic Connection The ISAP-SC140 connection actually involves an external data memory bank as well. Two connection schemes are shown: SC140 to single ISAP, and SC140 to multiple ISAPs. 6.2.1 Single ISAP Connection with the ISAP is illustrated in Figure 6-1 below: Address buses (A, B) Data Memory 2 Read buses (A,B) SC140Core 2 ISAP - Core Register channel 2 Write buses (A, B) ISAP Core to ISAP instruction dispatch Figure 6-1.
ISAP - SC140 Schematic Connection 6.2.2 Multiple ISAP Connection between the core and multiple ISAPs is illustrated in Figure 6-2, below: ISAP SC140Core ISAP ISAP selection encoding Core to ISAP instruction dispatch ISAP Enable bits ISAP Controller Figure 6-2. Core to Multiple ISAP Connection Schematic In a multiple ISAP configuration, some of the ISAP instruction encoding bits should be dedicated in advance for encoding the ISAP selection.
ISAP instructions and instruction encoding 6.3 ISAP instructions and instruction encoding This section presents an overview of the concept of programming the ISAP from the SC140 assembly code. The SC140 core can dispatch one ISAP opcode per VLES. This opcode uses the 2-word prefix encoding, and is recognized as an ISAP opcode if it is not the first opcode in the VLES.
ISAP-core register transfers However, this feature requires some assembler support (core and ISAP) when using such instructions. When the ISAP must either write or retrieve data from the data memory via the data busses, the core assembler must create a parallel AGU MOVE instruction in the same VLES as the ISAP instruction.
Immediate Data Transfer to ISAP registers Example 6-2. ISAP-Core register transfers The following line of code, core_ins {move_special d1,k0} That uses these instructions, 1st - core_ins = a generic core instruction 2nd - {move_special d1, k0} = a fictional ISAP instruction (for illustration purposes only), whose intent is to take the data in d1 (a core register), and place it in the k0 ISAP register.
Core Assembly Syntax with an ISAP 6.7 Core Assembly Syntax with an ISAP This section describes aspects of the core assembly syntax, supported by the software tools, that relate to the presence of an ISAP and to ISAP assembly instructions. 6.7.1 Identification of ISAP instructions ISAP specific commands are included in brackets: {}, for example: add d0,d1,d2 {...ISAP instructions..
Core Assembly Syntax with an ISAP 3rd - abs d0 = a core instruction The syntax defines that the string between the brackets is sent to the ISAP assembler. One ISAP in a Single-Line VLES mac d0,d1,d3 {isap_instruction k0,k1,k2 move_special.l k2,(r0)+} In this example, the MAC instruction is executed by the core and the instructions delimited by the brackets are executed by the ISAP.
Core Assembly Syntax with an ISAP Example 6-5.
Core Assembly Syntax with an ISAP This is similar example to that shown in Section 6.7.1, “Identification of ISAP instructions,” but instead of the ISAP tsteq instruction, a special move from a memory location to ISAP register k0 is used. The special ISAP move instruction (called permute_lsb_set.2l in this case) can read 64-bit data, permute the bytes according to a certain definition, set the LSB, and write the result to register k0.
Programming Rules line 1: The ift (if true) prefix instruction indicates that the core MAC instructions will be executed only if the T bit is set. lines2,3,4: The iff (if false) prefix instruction indicates that the ISAP instructions on lines 2,3 (including the implicit MOVE generated for the move_special ISAP instruction) and the core MOVE.L instruction on line 4 will be executed if the T bit is cleared. 6.
Programming Rules 6.8.2 Grouping rules for explicit ISAP instructions G.G.2: up to 8 instruction words per VLES G.G.3: One ISAP encoding word per VLES G.G.4: A destination operand can only be updated by one source per VLES.
Programming Rules 6.8.4 Sequencing rules for T bit update The ISAP has the ability to change the T bit as a destination of it’s instructions. The ISAP is less tightly coupled with the core, hence there the required dependency distance between The update of the T bit by the ISAP and usage by conditional core instructions is larger for non-DALU instructions. T.2a: One VLES required between an ISAP instruction that updates the T bit and a conditional COF instruction T.
Programming Rules 6-70 SC140 DSP Core Reference Manual
Chapter 7 Programming Rules The SC140 has programming rules for correct construction and execution of assembly language code. These rules define the ability to group or sequence instructions that activate various execution units, because of their use of shared resources. This chapter describes the SC140 programming rules and guidelines for correct code construction.
VLES Grouping Semantics • All instructions in a VLES execute in parallel. This means: — The assembly source order of instructions and labels within an unconditional VLES does not change the results, with one exception being the assembly source order determines which instruction (if any) updates the carry bit. Because source order within an unconditional VLES is not required for correct code execution, the assembler sometimes reorders instructions in the VLES during the encoding process.
Programming Rule Notation 7.3 SC140 Pipeline Exposure The SC140 has no hardware interlocks, so the pipeline is fully exposed during VLES execution. This is in direct contrast with the VLES sequencing and grouping semantics presented above, and is the motivation for the SC140 programming rules that follow. The programming rules hide the short pipeline latencies so they are not exposed in the assembly source code, saving hardware complexity and making SC140 code portable across different pipelines.
Programming Rule Notation 7.4.2 Sequencing Rules Sequencing rules enforce the VLES sequencing semantics by specifying the minimum distance between different VLES having instructions “A” and “B”. They use the notation “at least n VLES are required between” or “the minimum number of VLES between” instructions “A” and “B”. For a minimum VLES distance between “A” and “B”, the VLES having “A” and “B” are not included in this count. 7.4.2.1 Cycle Counts Rules A.1 and A.
Programming Rule Notation 7.4.3.2 B Register Aliasing The B0-7 base registers are the same registers as the R8-15 address registers in the AGU. For example, B0 and R8 have different source syntax and instruction encoding, but they are aliases to the same physical register. The rules always specify the Rn registers. The assembler and simulator detect the programming rules using either alias. Example 7-1. B Register Aliasing move.l d0,r8 move.l d1,b0 ;not allowed by G.G.4 - r8 and b0 are the same reg. 7.4.
Programming Rule Notation 7.4.7 AGU Arithmetic Instructions “AGU arithmetic instructions” are those instructions that execute during the Address Generation pipeline stage. This includes all instructions in Table A-9: AGU Arithmetic Instructions on page A-15. All SC140 instructions in this category end with the letter A (such as CMPEQA, ADDA, TFRA) with the following exceptions: IFA (a prefix instruction) and BRA (a non-loop COF instruction) are excluded. 7.4.
Static Programming Rules 7.4.10 Hardware Loops The loop count “LCn” and start address “SAn” registers are described in Section 5.4.1, “Loop Programming Model,” on page 5-25. The VLES addresses “LA, LA-1, LA-2” (relative to the loop end (last) address) and “SA, SA-1, SA-2” (relative to the loop start address) are defined in Section 5.4.2, “Loop Notation and Encoding,” on page 5-26. The minus “-” notation adjusts the VLES address earlier in the source code order.
Static Programming Rules • The SAn register contains the starting address of the first VLES of long loop n. These assumptions ensure the LOOPSTARTn and LOOPENDn directives are consistent with the hardware loop state machine’s decoding of the LPMARKx bits. The assembler may not detect hardware loop rules if these assumptions are violated. 7.5.2 General Grouping Rules Rule G.G.1 Up to 6 instructions can be grouped in a VLES. Prefix instructions (IFc, LPMARKx, and NOP) are not counted for this rule.
Static Programming Rules Rule G.G.4 Instructions grouped in a VLES cannot write to the same register or affect the same status bit. For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup unless explicitly stated. The less obvious cases are: • Multiple COF instructions that implicitly write the PC register cannot be grouped in a VLES. This case applies to the whole VLES, independent of the T bit state.
Static Programming Rules Example 7-8 Duplicate Register Destinations move.w #$1234,d0.h move.w #$5678,d0.l bmset #3,sr.h bmset #4,sr.l ;not allowed ;not allowed Note that BMSET #$3,SR.H reads and writes the 32-bit SR register. • MOVE-like instructions that write the SR or EMR register cannot be grouped in a VLES with instructions that affect individual status bits in the same register.
Static Programming Rules Example 7-12 Mutually Exclusive Register Destination Exception ift movet tfrt ift ift ift [ift add #1,d0 iff add #2,d0 r0,r1 movef r2,r1 d0,d1 tfrf d5,d1 add #1,d0 ifa tfrf d1,d0 adda #1,r0 iff adda #2,r0 move.w (r0)+,d0 iff move.w (r0)-,d0 move.
Static Programming Rules Rule G.P.1 Up to two extension words can be grouped in a VLES. This means: • A three-word instruction can only be grouped in a VLES with one-word instructions. Example 7-16 VLES Extension Words Exceed Two [ bmset #$ab34,d3.l move.l #$f0d0,vba ] • ; 1st extension word ; not allowed - 2nd & 3rd extension word A two-word instruction can only be grouped in a VLES with one other two-word instruction and/or one-word instructions.
Static Programming Rules Rule G.P.3 The following instructions in each line are mutually exclusive, and cannot be grouped in a VLES. For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup. • MARK • DEBUG and DEBUGEV • DI and EI • BREAK, CONT, CONTD, DOENn, DOENSHn, and SKIPLS STOP, WAIT, and any COF instruction cannot be grouped in a VLES. This applies also to a VLES having two mutually exclusive IFc subgroups. Example 7-18.
Static Programming Rules Example 7-20. Data Source Use of Nn and Mn Registers move.l n0,d0 ift move.l n0,d0 move.l n0,d1 iff move.l n0,d1 ;not allowed ;allowed move.l move.l move.l move.l move.l move.l move.l move.l n1,d1 suba n0,r0 move.l (r0)+n0,d1 move.l (r0+n0),d1 move.l (r1)+n0,d1 move.l (r1+n0),d1 move.l (r1+n0),d1 ;allowed ;allowed ;allowed ;allowed ;allowed ;allowed ;allowed n0,d0 n0,d0 n0,d0 n0,d0 (r0)+n0,d0 (r0)+n0,d0 (r0+n0),d0 move.l n0,d0 adda n0,n0 adda n0,n0 vsl.
Static Programming Rules Rule G.P.8 It is not allowed to group AGU instructions that use or update a data register (D0-D15) in the same VLES with an ISAP instruction. This rule relates to independent AGU instructions, not to instructions that are implicitly generated by the assembler from ISAP instructions to support ISAP memory accesses and register transfers. For more details on how this works, see Section 6.4, “ISAP Memory Access,” on page 6-60. Example 7-23.
Static Programming Rules 7.5.4 AGU Rules Rule A.1 At least two cycles are required between when an instruction writes the MCTL register and when an AGU instruction reads the R0-R7 registers with an address register update or address pre-calculation, or as an operand affected by a MCTL modifier field. This rule does not apply to R8-R15, or to R0-R7 using the no update (Rn) addressing mode. Example 7-25. MCTL Write to R0-R7 Use 7-16 move.l move.
Static Programming Rules Rule A.2 At least one cycle is required between a MOVE-like instruction writing to an address register (Rn or Nn) as a data operand and when the same register is used in the following manner with the following instructions: • An address operand of a MOVE-like instruction. • A source operand of an AGU arithmetic instruction. • An operand holding a target of a COF instruction 1.
Static Programming Rules If the VLES having a JT/JF or TRAP instruction is at the end of a program section, the following VLES must be a NOP. It cannot be data tables or uninitialized memory. Rule A.4 An AGU arithmetic instruction that writes a Rn or Nn register, or a MOVE-like instruction that writes a Rn or Nn register as an address operand, cannot be grouped in a VLES with a MOVE-like instruction that reads the same register as a data operand.
Static Programming Rules Rule A.7 A RTSTK or RTSTKD instruction cannot be grouped in a VLES with a MOVE-like instruction that reads the EMR register. For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup. Example 7-29. NMID Update to EMR Read rtstk move.l emr,d0 ;not allowed 7.5.5 Delayed COF Rules Rule D.1 The following instructions are not allowed in a delay slot: • COF instructions • STOP and WAIT • DI • DEBUG Example 7-30.
Static Programming Rules Rule D.2 Core or ISAP instructions that read or write the SR register, affect status bits in SR, or are affected by status bits in SR are not allowed in a RTED delay slot. This rule applies to instructions that use the stack pointer SP (implicitly or explicitly) and other stack pointer OSP, since SR affects which stack pointer is used (EXP status bit). Example 7-31. Instructions in a RTED Delay Slot rted move.l d0,sr ;not allowed rted move.
Static Programming Rules Rule D.4 Instructions that read the PC register (implicitly or explicitly) as a source operand are not allowed in a RTED/RTSD/RTSTKD delay slot. This rule does not apply to the MARK instruction that reads the PC register for the EOnCE trace buffer. Example 7-33. PC Read in a Return Delay Slot rted adda pc,r0 ;not allowed rtsd dosetup0 _label ;not allowed Rule D.
Static Programming Rules Rule D.8 A MOVE-like instruction that reads the SR register is not allowed in the delay slot of a CONTD instruction. Example 7-37. SR Read in a CONTD Delay Slot contd _label move.l sr,d0 ;not allowed Rule D.9 Instructions that read the EMR register are not allowed in the delay slot of a RTED, or RTSTKD instruction. Example 7-38. EMR Use in Return Delay Slots rtstkd move.l emr,d0 ;not allowed rted bmclr #$fffb,emr.l ;not allowed 7.5.6 Status Bit Rules Rule T.
Static Programming Rules Rule T.2.a At least one VLES is required between an ISAP instruction that affects the T status bit in SR and a conditional COF instruction. Example 7-40. T Bit Update by ISAP and COF {tsteq k0} jt r0 ; tsteq is an ISAP instruction that updates the T bit ; not allowed {tsteq k0} nop jf _destination ; allowed Rule T.2.b At least two VLES are required between an ISAP instruction that affects the T status bit in SR and a MOVET/MOVEF instruction. Example 7-41.
Static Programming Rules This rule applies to instructions that use the stack pointer (implicitly or explicitly), since SR affects which stack pointer is used (EXP status bit). A MOVE-like instruction that writes the SR register may be followed by a MOVE-like instruction that reads the SR register, if not affected by a SR status bit. The assembler-mapped instruction CLR Dn is never affected by SR status bits, even though it is implemented as SUB Da,Da,Dn.
Static Programming Rules Example 7-43. SR Write to SR Status Bit Use bmclr #$ffff,sr.h move.w #$1234,d0 ;change SR ;allowed, not affected by SR bmclr rol #$ffff,sr.h d0 ;change SR ;not allowed, affected by SR[C] bmclr nop rol #$ffff,sr.h ;change SR d0 ;not allowed, affected by SR[C] bmclr nop nop rol #$ffff,sr.h ;change SR d0 ;allowed bmclr nop push #<1,sr.l ;change SR d0 ;not allowed, affected by SR[EXP] bmclr #<1,sr.h nop ift clr d0 ;change SR bmtstc #$0001,sr.
Static Programming Rules Rule SR.3 At least one VLES is required between a MOVE-like instruction that writes the SR register and the following instructions that affect status bits in SR: • DI and EI • DOENn and DOENSHn • CONT/D, BREAK, and SKIPLS Example 7-44. SR Write to SR Status Bit Update move.l #<1,sr di ; not allowed bmclr doen0 #$ffff,sr.h #<10 ; not allowed pop cont sr _next ; not allowed Rule SR.
Static Programming Rules Example 7-45. DOVF Update to SR Read or Write bmset #$4,emr.l move.l emr,d2 ;allowed move.l #$4,emr move.l emr,d0 ;allowed move.l #$4,emr move.l d0,emr ;allowed move.l d1,emr move.l emr,d0 ;allowed add d0,d1,d2 nop move.l emr,d3 ;overflow may set DOVF bit adr nop move.l d3,d4 ;overflow may set DOVF bit d0,emr ;not allowed bmset nop move.l #$01,emr.l ;read and write EMR register d0,emr ;allowed ;not allowed sub d0,d1,d2 nop move.
Static Programming Rules Rule SR.7 The following instructions that affect status bits in SR cannot be grouped in a VLES with a MOVE-like instruction that reads the SR register: • BREAK • CONT/CONTD • DI and EI • DOENn and DOENSHn • SKIPLS For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup. Example 7-47. Status Bit Update with SR Read doen0 #5 di skipls _dest move.l sr,d0 push sr bmtsts #4,sr.h ;not allowed ;not allowed ;not allowed 7.5.
Static Programming Rules Rule L.N.2 A loop body n must be surrounded by the LOOPSTARTn and LOOPENDn assembly directives, and can only be nested inside a loop body having a smaller index. Example 7-49. Nested Loops with Ordered Index doen1 move.w move.l move.w #count1 #num,d1 #mem_l,r1 #offset,n0 loopstart1 label1 inc dosetup0 doen0 move.w d1 label2 #count2 #num,d2 loopstart0 ;not allowed label2 inc d2 impyuu d1,d2,d3 move.w d3,(r1)+ loopend0 nop loopend1 Rule L.N.
Static Programming Rules Example 7-51. DOENn instruction following DOENSHn Instruction doensh0 #3 doen0 #3 dosetup0 _loop_start nop nop _loop_start loopstart0 move.l #0,d0 move.l #1,d0 move.l #2,d0 loopend0 ; not allowed (SLF isn't reset) ;instruction should be in the loop, but isn't! Example 7-52.
Static Programming Rules 7.5.8 Loop LA Rules Rule L.L.1 The following instructions are not allowed at LA-1 or LA of a long loop: • COF instructions • STOP and WAIT • DI • DEBUG Example 7-54. Instructions at the End of Long Loops move.w #count2,d6 dosetup0 label2 doen0 d6 move.w #1,d1 move.w #2,d2 move.w #3,d3 move.w #4,d4 loopstart0 label2 inc d1 inc d2 inc d3 inc d4 wait loopend0 ;not allowed Rule L.L.
Static Programming Rules Rule L.L.3 The following instructions are not allowed in a short loop: • COF instructions • STOP and WAIT • DI • DEBUG • DOENn/DOENSHn • MOVE-like instructions that read any LCn register • MOVE-like instructions that write any LCn register • MOVE-like instructions that read the SR register • MOVE-like instructions that write the SR register This rule does not apply to other instructions that affect status bits in SR. Example 7-56.
Static Programming Rules Rule L.L.5 A MOVE-like instruction that writes the SR register is not allowed at LA-4, LA-3, LA-2, LA-1, or LA of a long loop. Rule L.L.6 A MOVE-like instruction that writes the SR register is not allowed at SA-2 or SA-1 of a short loop. 7.5.9 Loop Sequencing Rules Rule L.D.
Static Programming Rules Rule L.D.3 The minimum number of VLES between the following instructions that write a LCn register and SA of the same short loop n is: • DOENSHn Rn or #x: one VLES (address register or immediate value) • DOENSHn Dn: two VLES (data register) • MOVE-like instruction that writes a LCn register: two VLES Example 7-60. LCn Write at the Start of Short Loop n move.w #3,r0 doensh0 r0 move.l d1,lc0 move.w #2,d2 loopstart0 inc d1 loopend0 ;allowed ;not allowed Rule L.D.
Static Programming Rules Example 7-62. SAn Write at the End of Long Loop n loopstart0 ... doen1 #5 ... loopstart1 ... dosetup0 _addr loopend1 nop loopend0 ;not allowed Rule L.D.7 At least one VLES is required between an instruction that writes any SAn register and a CONT/CONTD instruction. Example 7-63. SAn Write to CONT/D Instruction doen1 #5 dosetup1 label1 loopstart1 label1 cont label2 inc d0 move.w #$23,d2 move.w #$beef,d3 loopend1 label2 inc d1 ;not allowed Rule L.D.
Static Programming Rules 7.5.10 Loop COF Rules Rule L.C.1 A COF instruction cannot have a COF destination that is LA-1 or LA of a long loop, or LA of a 2-VLES short loop. This rule does not apply to loop COF instructions (BREAK, CONT, CONTD and SKIPLS) in a nested loop having a COF destination that is LA-1 or LA of an enveloping loop. Example 7-65. COF Destination to Loop Delay Slots doensh1 #5 ... cmpeq.w #3,d0 jf _dest inc d0 loopstart1 inc d0 _dest add d1,d2,d3 loopend1 ;not allowed Rule L.C.
Static Programming Rules Rule L.C.5 A Bc or Jc instruction is not allowed at LA-3 of a long loop. Example 7-68. Bc/Jc at LA-3 of a Long Loop dosetup1 label7 move.
Static Programming Rules Rule L.C.7 A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) in an enabled loop n cannot have a COF destination in the same loop n. Example 7-69.
Static Programming Rules Rule L.C.9 A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) cannot have a COF destination that is one VLES before two consecutive VLES that are both LA of long loops. Example 7-70. Loop COF at End of Nested Long Loops doen0 #5 ... loopstart0 ... doen1 #10 ... loopstart1 ... doen2 d0 ... skipls _dest loopstart2 ... loopend2 ... ; not allowed _dest nop nop loopend1 nop loopend0 ; last address of long loop 1 ; last address of long loop 0 Rule L.C.
Static Programming Rules Rule L.C.11 A delayed COF instruction is not allowed at LA-3 of a long loop. Example 7-72. Delayed COF at LA-3 of a Long Loop jmpd_dest nop nop nop loopend0 ;not allowed Rule L.C.12 A delayed COF instruction is not allowed at SA-1 of a short loop. Example 7-73. Delayed COF at SA-1 of a Short Loop jmpd _dest loopstart0 nop loopend0 ;not allowed 7.5.11 General Looping Rules Rule L.G.
Dynamic Programming Rules Rule L.G.5 A loop having one or two VLES must be enabled by a DOENSHn instruction. A loop having three or more VLES must be enabled by a DOENn instruction. Example 7-76. Enabling Short and Long Loops doen1 #5 dosetup1 label1 skipls label2 loopstart1 ; not allowed label1 move.l d1,(r1)+ addnc.w #1,d1,d1 loopend1 label2 nop 7.
Dynamic Programming Rules 7.6.2 Memory Access Rules Rule A.5 Only one memory write instruction to the same location can be grouped in a VLES. Multiple memory write instructions grouped in a VLES must write to different locations, so the order that multiple writes occur does not change the memory results. If this is not done, the memory contents of the accessed locations are undefined. For mutually exclusive IFc subgroups in a VLES, this rule applies independently to each subgroup. Example 7-78.
Dynamic Programming Rules 7.6.3 RAS Rules Rule J.4 Upon execution of the RTS or RTSD instruction, if the RAS is valid, the value of the RAS (used to restore the PC) must be equal to the value in the stack, pointed to by the SP, that would have been used if the RAS was not valid. The following case manipulates the SP and builds on the return address using RAS: Example 7-81. Illegal use of RAS value move.l d6,(sp-8) adda #<8,sp rts move.l d7,(sp-$c) ; not allowed since RAS may be valid 7.6.
Dynamic Programming Rules 7.6.5 Rule Detection Across COF Boundaries Some sequencing rules may be violated across COF boundaries — between instructions that are before the COF instruction or grouped in a VLES with the COF instruction (or its delay slot), and instructions at or after the COF destination. The assembler does not analyze this control flow and lacks the run-time execution trace to detect these cases.
Dynamic Programming Rules 7.6.5.2 VLES-Based COF Rules VLES-based COF rules are detected like static rules, except the rule is detected from the simulation trace, not the source code order. A VLES having a COF instruction is counted like any other VLES. Exceptions to the above are JSR/D and BSR/D instructions, guaranteeing an inherent one VLES distance between the instructions in the source execution flow (including the delay slot), and the instructions in the destination flow.
Dynamic Programming Rules 7.6.6 Rule Detection Across Exception Boundaries The SC140 can take an exception at most VLES boundaries in a program, and return using a RTE//RTED/ instruction after completing the exception service routine. The programming rules ensure that the transition from the program to the exception service routine, and the return back to the program are correct. The return back to the program is covered by the RTE//RTED/ programming rules in this chapter.
Dynamic Programming Rules Rule A.1a AGU instructions that read the R0-R7 registers with an address register update or address pre-calculation, or as an operand affected by a MCTL modifier field are not allowed at the first 2 cycles of an exception service routine. This rule does not apply to R8-R15, or to R0-R7 using the no update (Rn) addressing mode. Example 7-86. MCTL Write to R0-R7 Use ; ISR Start move.w (r0)+,d0 ;use MCTL, not allowed ; ISR Start nop move.
Programming Guidelines 7.7 Programming Guidelines The rules in this section cannot be detected within the visibility of the assembler and simulator. For example, the assembler and simulator cannot determine if the computed JMP below has a valid COF destination. Example 7-87.
Programming Guidelines Rule J.5 A program section that ends near a border of reserved memory must end with a non-conditional change of flow (COF) instruction(s) followed by 4 aligned fetch sets (64 bytes) of NOPs or un-allocated memory. If the last meaningful instruction is not aligned with an end of a fetch set, some more NOPs are needed (up to 7) before 4 mentioned fetch sets.
Programming Guidelines • Observe the immediate operand ranges as specified within the braces { } in Appendix A.2, “Instructions,” on page A-19. Operand values outside these ranges are undefined. Some specific examples are: — — • ADD #u5,Dn {0 < u5 < 32} ASLL Da,Dn {-40 < Da[6:0] < 40} Observe address pointer alignments on memory accesses as specified in Table 2-19: Memory Address Alignment and within the braces { } in Appendix A.2, “Instructions.” Misaligned memory accesses are undefined.
LPMARK Rules • Do not write explicit binary encodings using DC (declare constant) assembler directives. It cannot be checked for errors by the assembler. • Do not use “reserved” or “--” operand field values in instruction encodings. This maintains software compatibility if a “reserved” or “--” field is defined in the future. 7.7.2.3 Software Development Practices • Programmers should not disable programming rule detection by the assembler and simulator.
LPMARK Rules 7.8.2 Static Programming Rules This section defines new SC140 LPMARK programming rules for correct LPMARKA and LPMARKB instruction use in a VLES, when enabled by an assembler switch. When enabled, these rules apply in addition to the other programming rules. 7.8.2.1 General Grouping Rules LPMARK Rule G.G.1 The LPMARKA and LPMARKB instructions are not counted for this rule. 7.8.2.2 Prefix Grouping Rules LPMARK Rule G.P.3 Multiple LPMARKA instructions cannot be grouped in a VLES.
LPMARK Rules 7.8.3.1.2 Active SAn Register “Active SAn register” is defined as the SAn register where n = the active loop index. This definition is dynamic and follows the SC140 loop state machine. 7.8.3.1.3 Active LCn Register “Active LCn register” is defined as the LCn register where n = the active loop index. This definition is dynamic and follows the SC140 loop state machine. 7.8.3.2 Loop Nesting Rules LPMARK Rule L.N.5 At least one LFn status bit in SR must be set at LPA or LPB of a loop.
LPMARK Rules LPMARK Rule L.L.2 A DOENn or MOVE-like instruction that writes the active LCn register is not allowed at LPB, LPB+1, or LPB+2 of a long loop. Example 7-93. Active LCn Write at the End of Long Loops doen1 #3 move.l #$12345678,r1 inc d0 {lpmarkb set} doen1 #5 ;not allowed move.w d3,(r1)+ LPMARK Rule L.L.
LPMARK Rules LPMARK Rule L.L.6 A MOVE-like instruction that writes the SR register is not allowed at LPA-2, LPA-1, LPB-2 or LPB-1 of a short loop. 7.8.3.4 Loop Sequencing Rules LPMARK Rule L.D.2 + L.D.
LPMARK Rules Example 7-97. Active LCn Read at the Start of a Loop doensh0 #$10 push lc0 inc d0 ;not allowed {lpmarka set} doensh0 #$10 push lc1 inc d0 ;allowed {lpmarka set} move.w #count2,d6 dosetup0 label2 doen0 d6 move.w #1,d1 move.w #2,d2 move.w #3,d3 move.w #4,d4 label2 inc d1 move.l lc0,d0 ;not allowed inc d2 {lpmarkb set} inc d3 inc d4 move.w #count2,d6 dosetup0 label2 doen0 d6 move.w #1,d1 move.w #2,d2 move.w #3,d3 move.w #4,d4 label2 inc d1 move.
LPMARK Rules Example 7-98. COF Instructions at LPB of a Long Loop dosetup1 label1 doen1 #n2 move.l #mem_l1,r1 move.l #mem_l2,r0 label1 inc d1 jsr r1 {lpmarkb set} add d1,d2,d3 move.w d3,(r0) ;not allowed LPMARK Rule L.C.3 + L.C.5 A Bc or Jc instruction is not allowed at LPA-1 or LPB-1 of a loop. Example 7-99. Bc/Jc at the Start of a Loop cmpgt d4,d3 nop iff doensh3 #count2 bt _dest ;not allowed inc d2 ... _dest inc d2 {lpmarka set} dosetup1 label7 move.w #0,d1 doen1 #5 move.
LPMARK Rules LPMARK Rule L.C.9 A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) cannot have a COF destination that is at LPB of a long loop if immediately followed by LPA. Example 7-100. Loop COF at End of Nested Long Loops doen0 #5 ... doen1 #10 ... doen2 d0 nop skipls _dest nop ift break label nop nop {lpmarkb set} nop nop ... nop {lpmarkb set} ;not allowed _dest nop label nop nop {lpmarkb set} {lpmarka set} ;last address of long loop 1 ;last address of long loop 0 LPMARK Rule L.C.
LPMARK Rules LPMARK Rule L.C.11 + L.C.12 A delayed COF instruction is not allowed at LPA-1 or LPB-1 of a loop. Example 7-102. Delay Slot at LPA or LPB of a Loop jmpd_dest nop nop nop jmpd ;not allowed {lpmarkb set} _dest nop ;not allowed {lpmarka set} 7.8.3.6 General Looping Rules LPMARK Rule L.G.3 + L.G.4 At least one VLES is required between a MOVE-like instruction that reads the SR register and LPA or LPB of a loop. Example 7-103.
NOP Definition LPMARK Rule L.C.1 A COF instruction cannot have a COF destination that is LPB+1 or LPB+2 of a long loop or LPB+1 of a short loop. This rule does not apply to loop COF instructions (BREAK, CONT, CONTD and SKIPLS) in a nested loop having a COF destination that is LPA-1 or LPA of an enveloping loop. Example 7-104. COF Destination to Loop Delay Slots doensh1 #5 ... cmpeq.
NOP Definition 5. Source syntax order in a VLES generally has no effect on the baseline size, as parallel semantics define no instruction serialization within a VLES. The baseline size is determined by the encoding rules in the assembler.
NOP Definition [INC D0NOP NOP] is encoded as: [1W prefix, INC, NOP] and [NOPNOP INC D0] is encoded as: [1W prefix, INC, NOP] 2. If a baseline VLES has a 1W or 2W prefix, a 1W embedded NOP is encoded for each source NOP. For example: [LPMARKAINC D0 NOP] is encoded as: [1W prefix, INC, NOP] and [INC D8NOP] is encoded as: [2W prefix, INC, NOP] 3. If a baseline VLES requires assembler padding for modulo alignment, a 1W embedded NOP is encoded for each source NOP. For example: [MOVE.W #s16,d0MOVE.
NOP Definition [2W IFT-IFF prefix, INC, CLR, NOP] and [IFF CLR D8IFT INC D1 IFT NOP] is encoded (ignoring the NOP subgroup) as: [2W IFT-IFF prefix, CLR, INC, NOP] 7. If a baseline VLES has multiple NOPs in a conditional subgroup, a 1W embedded NOP is encoded for each source NOP.
NOP Definition 7-64 SC140 DSP Core Reference Manual
Appendix A SC140 DSP Core Instruction Set A.1 Introduction This appendix describes in detail the SC140 instruction set, its encoding, and its syntax. The first pages of this appendix contain information common to all of the instructions such as the conventions, notation, and syntax used in the Appendix. Next, the encoding for the prefix words is given. Then, the names and simple descriptions of the instructions are listed in functional groups.
DSP Core Instruction Set A.1.1 Conventions Table A-1 lists the conventions used in this appendix to define the instructions. Table A-1. Instruction Conventions Convention Definition () aa Cn Da Da:Db De.E; Do.E De.E:Do.E Db De Dn Do DR Ea HP Ln LP rc Rn rx Rx {} Indirect address Absolute address Control registers Single source/destination data register Source/destination data register pair Data register extension (bits 39:32 + Ln bit) Data register extension pair (e.g., D4.E:D5.
DSP Core Instruction Set Table A-2 describes the operators and operations syntax for each instruction. Table A-2.
DSP Core Instruction Set Table A-4 lists special syntax used in this appendix to define an instruction’s assembler syntax. Note that the assembler syntax is case insensitive. Table A-4. Assembler Syntax # Prefix for an immediate value (for example, #u5 means an immediate 5-bit unsigned number and #s16 is an immediate 16-bit signed number). $ Prefix to a hexadecimal value (for example, #$1A4F as an immediate value or $2FC as an address offset).
DSP Core Instruction Set A.1.2 Addressing Mode Notation Table A-5 and Table A-6 define the fields in the address offset or post increment tables, which are found in the instruction field section of an instruction definition. EA stands for effective address. A different field in the opcode (RRR) determines what register is used for Rn. EA MMM Effective Address Notation 000 (Rn+N0) 010 (Rn) 100 (Rn)+N0 110 (Rn)+N2 001 (Rn)– 011 (Rn)+ 101 (Rn)+N1 111 (Rn)+N3 11 (Rn) Table A-5.
DSP Core Instruction Set A.1.3 Data Representation in Memory for the Examples For the examples in this appendix, the convention for the representation of data in memory is to show the same order in memory as is in the source register for a write. For example, a 32-bit write from a register containing $12345678 to address $100 will be shown as: ($100) = $12345678. The exact order of multi-byte operands in memory depends on the endian mode, and is described in Section 2.4.
DSP Core Instruction Set A.1.5 Prefix Word Encoding Each execution set can be associated with a one-word (low or high register) or two-word prefix that is placed at the beginning of the set. A prefix conveys additional information about the set such as: • Conditional execution of an execution set or a subgroup (originating in the IFT/IFF/IFA instructions). • The number of instructions that are grouped together in the execution set.
DSP Core Instruction Set A.1.5.1 One-Word Low Register Prefix Includes information on grouping, looping, and IFc (conditional execution). Instruction Formats and Opcodes Prefix Words Cycles Type Opcode 15 1W LOW REG PREFIX 1 0 4 1 0 0 1 a a a 8 7 0 1 0 1 0 p j c c c Instruction Fields aaa: Number of instruction words being grouped, including the prefix word minus one.
DSP Core Instruction Set Example: skipl _last ;(there is a skipl to _last in the program) . . . execution_set execution_set _last execution_setlpmarkA In the case of the loop having just one execution, the lpmarkA bit is set in the prefix of this single execution set of the loop. A.1.5.2 Two-Word Prefix Includes information on grouping, looping, IFc (conditional execution), and high-register banks (D8-D15, R8-R15).
DSP Core Instruction Set Example: lpmarkB;(set LA – 2) ;(set LA – 1) _last ;(set LA) In the case of a loop with two execution sets such as SA mark, the lpmarkB bit is set in the first execution set of the loop.
DSP Core Instruction Set Hh: High register expansion encoding for AGU execution unit 0. This includes all AGU and BMU instructions. R0-7 registers are expanded up to R0-15. The two bits Hh controls the expansion of R0-R7 registers to R8-R15 registers in one or two AGU instruction’s operands according to the following rules: The H bit is used for all of the operands from the types: - Rn operand defined with RRR field (e.g.
DSP Core Instruction Set A.1.6 Instruction Types The SC140 instruction set is organized into the following instruction types, specified at the top of every instruction definition in this Appendix: DALU Instructions- perform operations on the data registers D0-D15 using the DALU execution units (MAC and BFU). All DALU instructions are listed in Table A-7 and Table A-8. The architecture is described in Section 2.2.1, “DALU Architecture,” on page 2-6.
DSP Core Instruction Set Table A-7. DALU Arithmetic Instructions (MAC) Instruction Description ABS Absolute value ADC Add long with carry ADD Add ADD2 Add two words ADDNC.
DSP Core Instruction Set Table A-7. DALU Arithmetic Instructions (MAC) (Continued) Instruction Description MPYR Multiply signed fractions and round MPYSU Multiply signed fraction and unsigned fraction MPYUS Multiply unsigned fraction and signed fraction MPYUU Multiply unsigned fraction and unsigned fraction NEG Negate RND Round SAT.F Saturate fractional value in data register to fit in high portion SAT.
DSP Core Instruction Set Table A-8. DALU Logical Instructions (BFU) (Continued) Instruction Description ROL Rotate one bit left through the carry bit ROR Rotate one bit right through the carry bit SXT.B Sign extend byte SXT.L Sign extend long SXT.W Sign extend word ZXT.B Zero extend byte ZXT.L Zero extend long ZXT.W Zero extend word Table A-9.
DSP Core Instruction Set Table A-10. AGU Move Instructions Instruction Description MOVE.2F Move two fractional words from memory to a register pair MOVE.2L Move two longs to/from a register pair MOVE.2W Move two integer words to/from memory and a register pair MOVE.4F Move four fractional words from memory to a register quad MOVE.4W Move four integer words to/from memory and a register quad MOVE.B Move byte to/from memory MOVE.F Move fractional word to/from memory MOVE.
DSP Core Instruction Set Table A-12. AGU Bit-Mask Instructions (BMU) Instruction Description AND Logical AND on a 16-bit operand BMCHG Bit-mask change a 16-bit operand BMCHG.W Bit-mask change a 16-bit operand in memory BMCLR Bit-mask clear a 16-bit operand BMCLR.W Bit-mask clear a 16-bit operand in memory BMSET Bit-mask set a 16-bit operand BMSET.W Bit-mask set a 16-bit operand in memory BMTSET Bit mask test and set a 16-bit operand BMTSET.
DSP Core Instruction Set Table A-13. AGU Non-Loop Change-of-Flow Instructions Instruction Description RTED Return from exception (delayed) RTS Return from subroutine RTSD Return from subroutine (delayed) RTSTK Force restore PC from the stack, updating SP RTSTKD Force restore PC from the stack, updating SP (delayed) TRAP Execute a precise software exception Table A-14.
DSP Core Instruction Set A.2 Instructions The following pages list all of the SC140 instructions and provide specific details about each instruction’s operation and encoding. A.2.1 Instruction Definition Layout INST Description (type) Instruction type (AGU, DALU, etc.) A brief description of the instruction INST Instruction name, the same as in the mnemonic Operation Assembler Syntax The fields under this header describe the operations carried out by the various forms of this instruction.
ABS A ABS ABS Absolute Value (DALU) Operation Assembler Syntax ⏐Dn⏐ → Dn ABS Dn Description ABS Dn Replaces the value in a data register (Dn) with its absolute value. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode. SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the Ln bit calculation.
ABS Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ABS Dn Note: 1 1 0 8 * 1 0 0 1 7 F F F 0 1 1 0 0 1 1 0 ** indicates serial grouping encoding. Instruction Fields Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
ADC ADC Add Long With Carry (DALU) Operation Assembler Syntax Dc + Dd + C → Dd ADC Dc,Dd ADC Description ADC Dc,Dd Adds two source data registers (Dc, Dd) plus the carry bit and stores the result in the second data register (Dd). This instruction can be used in multiple precision addition as illustrated in the example, which is a 64-bit addition.
ADC Register/Memory Address Before After EMR $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ADC Dc,Dd Note: 1 1 0 * 1 0 1 1 e 8 7 e 0 0 1 1 1 1 0 1 0 ** indicates serial grouping encoding. Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: D0,D1 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix.
ADD ADD ADD Add (DALU) Operation Assembler Syntax #u5 + Dn → Dn ADD #u5,Dn {0 ≤ u5 < 32} Da + Db → Dn ADD Da,Db,Dn Description These operations add two source operands and store the result in a destination data register (Dn). ADD #u5,Dn The five bits of the unsigned immediate are right-aligned and the upper bits are zero-extended to form a 40-bit source operand. That operand is then added to a data register (Dn) and the result stored in the destination data register (Dn).
ADD Register/Memory Address Before After L2:D2 $0:$00 0000 0007 EMR $0000 0000 Example 2 add d1,d0,d2 Register/Memory Address Before After SR $00E0 0000 D1 $00 72E3 8F2A D0 $00 7216 EE3C L2:D2 $1:$00 E4FA 7D66 EMR $0000 0000 The L2 bit is set from the 32-bit overflow. Note that the extension bits are in use in the sum, bit 32 =0, bit 31 = 1.
ADD Instruction Fields Da,Db JJJJJ Data Register Pairs 00000 D0,D4 01000 D2,D4 10000 D0,D0 11000 D1,D2 00001 D0,D5 01001 D2,D5 10001 D0,D1 11001 D1,D3 00010 D0,D6 01010 D2,D6 10010 D0,D2 11010 D5,D6 00011 D0,D7 01011 D2,D7 10011 D0,D3 11011 D5,D7 00100 D1,D4 01100 D3,D4 10100 D4,D4 11100 D2,D2 00101 D1,D5 01101 D3,D5 10101 D4,D5 11101 D2,D3 00110 D1,D6 01110 D3,D6 10110 D4,D6 11110 D6,D6 D1,D7 01111 D3,D7 10111 D4,D7 11111 D6,D7 00111 Notes:
ADD2 ADD2 Add Two 16-Bit Values (DALU) Operation Assembler Syntax Da.H + Dn.H → Dn.H Da.L + Dn.L → Dn.L ADD2 Da,Dn ADD2 Description ADD2 Da,Dn Performs a 32-bit addition of source registers Da and Dn with carry disabled between bits 15 and 16, so that the high and low words of each register are added separately. The result is stored back in Dn. The extension byte of the result is undefined. Status and Conditions that Affect Instruction None.
ADD2 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ADD2 Da,Dn 1 2 1 8 1 0 1 0 0 7 F F F 0 1 0 0 0 J J J Instruction Fields Dn FFF 000 001 Note: Da D0 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
ADDA ADDA Add (AGU) ADDA Operation Assembler Syntax #u5 + Rx → Rx ADDA #u5,Rx {0 ≤ u5 < 32} #s16 + rx → Rn ADDA #s16,rx,Rn {–215 ≤ s16 < 215} rx + Rx → Rx ADDA rx,Rx Description These operations add an immediate signed 16-bit integer to the contents of a source AGU register and store the result in a destination address register. If the second source operand (rx) uses R0-R7, the operation is affected by the modifier mode selected in the modifier control register (MCTL).
ADDA Example 1 adda r0,r1 Register/Memory Address Before After MCTL $0000 0000 R0 $0000 1100 R1 $0000 2200 $0000 3300 Example 2 move.l #$8,mctl ;assigns m0 to r0, modulo arithmetic move.l #$10,m0 ;puts modulo 16 in m0 move.
ADDA rx rrrr 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx AGU Source Register This instruction can specify R8-R15 as operands by using a high register prefix.
ADDL1A ADDL1A Add With One-Bit Arithmetic Shift Left of Source Operand (AGU) Operation Assembler Syntax (rx<<1) + Rx → Rx ADDL1A rx,Rx ADDL1A Description ADDL1A rx,Rx Performs a one-bit arithmetic shift left on the data from source AGU register (rx) and adds the result to a second source AGU register (Rx). The sum is stored back in Rx. For R0-R7 destinations, the operation is affected by the modifier mode selected in MCTL.
ADDL1A Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ADDL1A rx,Rx 1 2 1 8 1 1 7 0 R R R R 0 0 0 0 0 r r r r Instruction Fields rx rrrr 0000 N0 0100 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx AGU Source Register — 1000 R0 1100 R4 This instruction can specify R8-R15 as operands by using a high register prefix.
ADDL2A ADDL2A Add With Two-Bit Arithmetic Shift Left of Source Operand (AGU) Operation Assembler Syntax (rx<<2) + Rx → Rx ADDL2A rx,Rx ADDL2A Description ADDL2A rx,Rx Performs a two-bit arithmetic shift left on the data from AGU source register (rx), adds the result to another AGU source register (Rx), and stores the sum in the destination (second) register (Rx). For R0-R7 destinations, the operation is affected by the modifier mode selected in MCTL.
ADDL2A Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ADDL2A rx,Rx 1 2 1 8 1 1 7 0 R R R R 0 0 0 1 0 r r r r Instruction Fields rx rrrr 0000 N0 0100 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx AGU Source Register — 1000 R0 1100 R4 This instruction can specify R8-R15 as operands by using a high register prefix.
ADDNC.W ADDNC.W ADDNC.W Add Without Changing the Carry Bit (DALU) Operation Assembler Syntax #s16 + Da → Dn ADDNC.W #s16,Da,Dn {–215 ≤ s16 < 215} Description ADDNC.W #s16,Da,Dn Sign-extends the 16-bit immediate value to 40 bits and adds it to the source data register Da. The sum is stored in destination register Dn. The carry bit is not affected by this instruction.
ADDNC.
ADR ADR ADR Add and Round (DALU) Operation Assembler Syntax Rnd(Da + Dn) → Dn ADR Da,Dn Description ADR Da,Dn Adds one source data register (Da) to another (Dn) and rounds the sum. The result is stored in the destination data register (Dn). Rounding adjusts the LSB of the high part of the destination register according to the value of the low part of the register and then zeros the low part. The boundary between the high part and the low part changes with scaling.
ADR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ADR Da,Dn Note: 1 1 0 8 * 1 1 0 0 7 F F F 0 1 0 0 0 J J J ** indicates serial grouping encoding. Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D15 as operands by using a prefix.
AND AND AND Bitwise AND (DALU) Operation Assembler Syntax #0u16 • Da → Dn AND #0{u16},Da,Dn {0 ≤ u16 < 216} #u16$0000 • Da → Dn AND #{u16}$0000,Da,Dn {0 ≤ u16 < 216} Da • Dn → Dn AND Da,Dn Description These operations perform a "logical and" between the two source operands, and store the result in the destination operand. AND #0{u16},Da,Dn The immediate unsigned word is zero-extended in bits [40:16] to form a 40-bit immediate operand.
AND Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register.
AND Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 AND #0{u16},Da,Dn 1 4 2 1 4 1 1 2 0 0 1 1 J J J 1 i i i 1 1 F F F 1 0 0 i i i i i i i i i i i 8 7 i i 0 0 0 1 1 J J J 1 i i i 0 1 F F F 1 0 0 i i i i i i i i i i i 8 7 15 AND Da,Dn 7 0 15 AND #{u16}$0000,Da,Dn 8 1 1 0 1 1 1 F F F i i 0 0 0 0 0 J J J Instruction Fields Da JJJ Single Source Data Register 000 001 Note: Dn D0 010
AND AND Bitwise AND with 16-Bit Immediate (BMU) Operation Assembler Syntax #u16 • DR.L → DR.L AND #u16,DR.L #u16 • DR.H → DR.H AND #u16,DR.H AND Description AND #u16,DR.L Performs a bitwise AND on an immediate unsigned word and the contents of the LP of a source data or address register (DR). Stores the result in the LP of the data or address register (DR). The HP of the register is unaffected. Note: This instruction is assembler-mapped to BMCLR #~u16,DR.
AND Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 AND #u16,DR.L 2 2 3 2 2 3 7 0 0 0 0 0 1 0 0 0 i i i 0 H H H H 1 0 1 i i i i i i i i i 8 7 15 AND #u16,DR.
AND.W AND.W Bitwise AND with 16-Bit Immediate (BMU) AND.W Operation Assembler Syntax #u16 • (R) → (R) AND.W #u16,(Rn){0 ≤ u16 < 216} #u16 • (SP – u5) → (SP – u5) AND.W #u16,(SP–u5){0 ≤ u16 < 216}{0 ≤ u5 < 64,W} #u16 • (a16) → (a16) AND.W #u16,(a16){0 ≤ u16 < 216}{0 ≤ a16 < 216,W} #u16 • (SP + s16) → (SP + s16) AND.
AND.W Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None. Example and.
AND.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 AND.W #u16,(Rn) 2 3 2 3 3 3 2 3 0 1 0 0 0 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i 8 7 3 3 3 i i i 0 0 0 0 0 0 0 0 0 i i i A A A A A 1 0 1 i i i i i i i i i 8 7 1 1 i i 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i 0 i 0 i 0 i 0 i 15 AND.W #u16,(SP+s16) 0 0 15 AND.W #u16,(a16) 7 0 15 AND.
ASL ASL ASL Arithmetic Shift Left By One Bit (DALU) Operation Assembler Syntax Da << 1→ Dn ASL Da,Dn Description ASL Da,Dn Shifts a source data register (Da) left one bit and stores the result in a destination data register (Dn). If the source and destination registers are the same, the original value is destroyed, leaving the shifted value in the register.
ASL Register/Memory Address Before After SR $00E0 0000 $00E0 0001 EMR $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 ASL Da,Dn 1 1 1 ASL Da,Dn 1 1 1 0 8 1 0 1 1 F F F * 1 0 0 0 F F F 15 Note: 0 7 * 8 0 1 0 J J J J 1 1 0 0 0 j 7 J 0 j ** indicates serial grouping encoding.
ASL2A ASL2A ASL2A Arithmetic Shift Left By Two Bits (AGU) Operation Assembler Syntax Rx<<2 → Rx ASL2A Rx Description ASL2A Rx Shifts an AGU register (Rx) left two bits. Bits [29:0] are copied into bits [31:2]. Bits [1:0] are cleared. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR.
ASLA ASLA ASLA Arithmetic Shift Left By One Bit (AGU) Operation Assembler Syntax Rx<<1 → Rx ASLA Rx Description ASLA Rx Shifts an AGU (Rx) register left one bit. Bits [30:0] are copied into bits [31:1]. Bit 0 is cleared. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None.
ASLL ASLL ASLL Multiple-Bit Arithmetic Shift Left (DALU) Operation Assembler Syntax Dn << #u5 → Dn ASLL #u5,Dn {0 ≤ u5 < 32} If Da[6:0] > 0, then Dn << Da[6:0] → Dn ASLL Da,Dn {–40 ≤ Da[6:0] ≤ 40} else Dn >> |Da[6:0]| → Dn Description These operations shift the contents of Dn by the amount in #u5 or in Da. Bits shifted out of Dn are lost except for the last bit, which is stored in the C bit. ASLL #u5,Dn Shifts left by #u5, an immediate unsigned 5-bit integer.
ASLL Status and Conditions Changed by Instruction Register Address Bit Name Description SR[0] C Calculates and updates the carry bit in the status register. EMR[2] DOVF Set if the result cannot be represented in 40 bits. Ln L Clears the Ln bit in the destination register.
ASLL Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 ASLL #u5,Dn 1 1 1 ASLL Da,Dn 1 1 2 0 8 * 1 1 1 1 F F F 1 0 1 0 1 F F F 15 Note: 1 7 8 0 1 0 i i i i i 0 0 1 0 J J J 7 0 ** indicates serial grouping encoding. Instruction Fields Da JJJ Single Source Data Register 000 001 Note: Dn A-54 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
ASLW ASLW Word Arithmetic Shift Left 16 Bits (DALU) Operation Assembler Syntax Da<<16 → Dn ASLW Da,Dn ASLW Description ASLW Da,Dn Shifts the source register Da left by 16 bits and stores it in the destination register Dn. Bit 24 of the source register is copied into the C bit. Bits [23:0] of the source register are copied into bits [39:16] of the destination register. Bits [15:0] of the destination register are cleared. C 39 32 31 16 15 0 0 Status and Conditions that Affect Instruction None.
ASLW Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ASLW Da,Dn 1 2 1 8 1 0 1 1 0 7 F F F 0 0 0 1 0 J J J Instruction Fields Dn FFF 000 001 Note: Da D0 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
ASR ASR ASR Arithmetic Shift Right By One Bit (DALU) Operation Assembler Syntax Da>>1 → Dn ASR Da,Dn Description ASR Da,Dn Performs an arithmetic right shift by one bit on the source register Da, and stores it in the destination register Dn. The LSB (bit 0) of the source register is copied into the status register carry (C) bit. Bits [39:1] of the source register are copied into bits [38:0] of the destination register. Bit 39 of the source register is copied into bit 39 of the destination register.
ASR Register/Memory Address Before SR After $00E4 0000 $00E4 0001 EMR $0000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ASR Da,Dn Note: 1 1 0 8 * 1 1 0 1 7 F F F 0 1 0 0 0 J J J ** indicates serial grouping encoding. Instruction Fields Da JJJ 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D15 as operands by using a prefix.
ASRA ASRA ASRA Arithmetic Shift Right By One Bit (AGU) Operation Assembler Syntax Rx>>1 → Rx ASRA Rx Description ASRA Rx Performs an arithmetic right shift by one bit on the AGU register (Rx). Moves bits [31:1] into bits [30:0]. Bit 31 remains the same, creating a sign-extension. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand.
ASRR ASRR Multiple-Bit Arithmetic Shift Right (DALU) Operation Assembler Syntax Dn >> #u5 → Dn ASRR #u5,Dn {0 ≤ u5 < 32} If Da[6:0] > 0, then Dn >> Da[6:0]→ Dn else Dn << |Da[6:0]| → Dn ASRR Da,Dn ASRR Description This operation shifts the contents of Dn by N bits. Bits shifted out of Dn are lost except for the last bit, which is stored in the C bit. ASRR #u5,Dn Performs an arithmetic right shift by N, an immediate unsigned 5-bit integer. The MSB is copied into the vacated positions.
ASRR Status and Conditions Changed by Instruction Register Address Bit Name Description SR[0] C Set to the value of the last bit out. EMR[2] DOVF Set if the result cannot be represented in 40 bits (possible only for ASRR Da,Dn) Ln L Clears the Ln bit in the destination register.
ASRRS Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ASRR #u5,Dn 1 1 0 8 * 1 1 1 1 15 1 ASRR Da,Dn Note: 1 2 1 0 1 0 1 0 F F F 8 1 7 1 1 i i i i 7 i 0 F F F 0 0 1 1 J J J ** indicates serial grouping encoding.
ASRW ASRW Word Arithmetic Shift Right 16 Bits (DALU) Operation Assembler Syntax Da>>16 → Dn ASRW Da,Dn ASRW Description ASRW Da,Dn Performs an arithmetic right shift of 16 bits on the source register Da and stores the result in the destination register Dn. It copies bit 39 of the source register to bits [39:24] of the destination register, bit 15 of the source register to the C bit, and bits [39:16] of the source register to bits [23:0] of the destination register.
ASRW Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ASRW Da,Dn 1 2 1 8 1 0 1 1 0 7 F F F 0 0 0 1 1 J J J Instruction Fields Da JJJ Single Source Data Register 000 001 Note: Dn 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
BF B BF BF Branch If False (AGU) Operation Assembler Syntax If T==0, then PC + displacement → PC BF label Description BF label Branches to label if the true bit is cleared. If the T bit is cleared, the program continues executing at location PC + displacement. If the T bit is set, the PC is updated to point to the next execution set, and the program continues executing sequentially.
BF Register/Memory Address Before After d2 $0000 $0000 pc $0006 $0016 Instruction Formats and Opcodes Words Cycles1 Type Instruction Opcode 15 BF label 7 1 7 1 A A A 1 0 0 0 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: If the branch is not taken, it uses 1 cycle. If the branch is taken, it uses 4 cycles.
MOVES.4F BFD Branch If False Using a Delay Slot (AGU) Operation Assembler Syntax If T==0, then PC + displacement → PC BFD label BFD Description BFD label Branches to label if the true bit is cleared. If the T bit is cleared, the program continues executing at location PC + displacement. If the T bit is set, the PC is updated to point to the next execution set, and the program continues executing sequentially.
MOVES.4F Register/Memory Address Before After d1 $0000 $002A d2 $0000 $0000 d4 $0000 $001A pc $0006 $0016 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 BFD label 7 1 7 0 0 0 1 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: If the branch is not taken, it uses 1 cycle.
BMCHG BMCHG Bit-Masked Change a BMCHG 16-Bit Operand (BMU) Operation Assembler Syntax ~C1.Hi → C1.Hi (i denotes bits=1 in #u16) BMCHG #u16,C1.H {0 ≤ u16 < 216} ~C1.Li → C1.Li BMCHG #u16,C1.L {0 ≤ u16 < 216} ~DR.Hi → DR.Hi BMCHG #u16,DR.H {0 ≤ u16 < 216} ~DR.Li → DR.Li BMCHG #u16,DR.L {0 ≤ u16 < 216} Description These operations use an unsigned 16-bit immediate data mask to invert selected bits in the destination operand.
BMCHG.W Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination data register. Example bmchg #$f0f0,d1.h Register/Memory Address Before After immediate $F0F00000 L1:D1 $0:$FFF0F07B22 $0:$FF00007B22 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMCHG #u16,C1.
BMCHG.
BMCHG.W BMCHG.W Bit-Masked Change a 16-Bit Operand in Memory (BMU) BMCHG.W Operation Assembler Syntax ~(SP-u5)i → (SP-u5)i BMCHG.W #u16,(SP–u5){0 ≤ u16 < 216}{0 ≤ u5 < 64,W} (i denotes bits=1 in #u16) ~(SP+s16)i → (SP+s16)i BMCHG.W #u16,(SP+s16){0 ≤ u16 < 216}{–215 ≤ s16 < 215,W} ~(Rn)i → (Rn)i BMCHG.W #u16,(Rn) {0 ≤ u16 < 216} ~(a16)i → (a16)i BMCHG.
BMCHG.W Example bmchg.w #$661f,<$800c Register/Memory Address Before After immediate $661F $800C $ACE1 In binary, $661F 0110 0110 0001 1111 $ACE1 1010 1100 1110 0001 $CAFE 1100 1010 1111 1110 $CAFE Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 BMCHG.
BMCHG.
BMCLR;Instruction Set:BMCLR BMCLR Bit-Masked Clear a 16-Bit Operand (BMU) BMCLR Operation Assembler Syntax 0 → C1.Hi (i denotes bits=1 in #u16) BMCLR #u16,C1.H {0 ≤ u16 < 216} 0 → C1.Li BMCLR #u16,C1.L {0 ≤ u16 < 216} 0 → DR.Hi BMCLR #u16,DR.H {0 ≤ u16 < 216} 0 → DR.Li BMCLR #u16,DR.L {0 ≤ u16 < 216} Description These operations use an unsigned 16-bit immediate data mask to clear selected bits in the destination operand.
BMCLR Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register. Example bmclr #$b646,d7.l Register/Memory Address Before After immediate $B646 L7:D7 $0:$0050006C5A $0:$0050004818 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMCLR #u16,C1.
BMCLR #u16 iiiiiiiiiiiiiiii SC140 DSP Core Reference Manual 16-bit unsigned immediate data A-77
BMCLR.W BMCLR.W Bit-Masked Clear a 16-Bit Operand in Memory (BMU) BMCLR.W Operation Assembler Syntax 0 → (SP–u5)i BMCLR.W #u16,(SP–u5){0 ≤ u16 < 216<{0 ≤ u5 < 64,W} (i denotes bits=1 in #u16) 0 → (SP+s16)i BMCLR.W #u16,(SP+s16){0 ≤ u16 < 216}{–215 ≤ s16 < 215,W} 0 → (Rn)i BMCLR.W #u16,(Rn){0 ≤ u16 < 216} 0 → (a16)i BMCLR.W #u16,(a16){0 ≤ u16 < 216}{0 ≤ a16 < 216,W} Description These operations use an unsigned 16-bit immediate data mask to clear selected bits in the destination operand.
BMCLR.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMCLR.W #u16,(SP–u5) 2 3 3 3 3 3 2 2 0 0 0 0 0 0 i i i A A A A A 1 0 1 i i i i i i i i i 8 7 0 3 1 3 2 3 i 0 0 1 A A A A A A A A A A A A A 1 0 i i 0 i 0 i 0 i 1 i 1 i 0 i 0 A A A i i 8 7 i i i i i i 0 i 1 i 1 i 0 0 0 0 1 0 0 0 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i 8 7 15 BMCLR.W #u16,(a16) 0 0 15 BMCLR.
BMSET BMSET Bit-Masked Set a 16-Bit Operand (BMU) BMSET Operation Assembler Syntax 1→ C1.Hi (i denotes bits=1 in #u16) BMSET #u16,C1.H {0 < u16 < 216} 1 → C1.Li (selected bits) BMSET #u16,C1.L {0 < u16 < 216} 1 → DR.Hi (selected bits) BMSET #u16,DR.H {0 < u16 < 216} 1 → DR.Li (selected bits) BMSET #u16,DR.L {0 < u16 < 216} Description These operations use an unsigned 16-bit immediate data mask to set selected bits in the destination operand.
BMSET bmset #$2436,d1.l Register/Memory Address Before After $2436 L1:D1 $0:$0043A1243C $0:$0043A1243E Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMSET #u16,C1.
BMSET BMSET.W Bit-Masked Set a 16-Bit Operand in Memory (BMU) Operation BMSET.W Assembler Syntax 1 → (SP–u5)i (i denotes bits=1 BMSET.W #u16,(SP–u5){0 ≤ u16< 216}{0 ≤ u5 < 64,W} in #u16) 1 → (SP+s16)i (selected bits) BMSET.W #u16,(SP+s16){0 ≤ u16 < 216}{–215 ≤ s16 < 215,W} 1 → (Rn)i (selected bits) BMSET.W #u16,(Rn){0 ≤ u16 < 216} 1 → (a16)i (selected bits) BMSET.
BMSET Example bmset.w #$f111,<$800c Register/Memory Address Before After immediate $F111 ($800C) $C642 $F753 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMSET.
BMTSET BMTSET BMTSET Bit-Masked Test and Set a 16-Bit Operand (BMU) Operation Assembler Syntax 1 → DR.Hi (i denotes bits=1 in #u16) if (all selected bits were set), then 1 → T, else 0 → T BMTSET #u16,DR.H {0 ≤ u16 < 216} 1 → DR.Li (selected bits) if (all selected bits were set), then 1 → T, else 0 → T BMTSET #u16,DR.L {0 ≤ u16 < 216} Description These operations use an unsigned 16-bit immediate data mask to test and set selected bits in the destination operand.
BMTSET Example 2 bmtset #$4238,d4.l Register/Memory Address Before After SR $00E4 0000 immediate $00E4 0002 $4238 d4 $00 1234 5678 $00 1234 5678 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMTSET #u16,DR.H 2 2 3 2 2 3 7 0 0 0 0 0 1 1 1 0 i i i 1 H H H H 1 0 1 i i i i i i i i i 8 7 15 BMTSET #u16,DR.
BMTSET.W BMTSET.W BMTSET.W Bit-Masked Test and Set a 16-Bit Operand in Memory (BMU) Operation Assembler Syntax BMTSET.W #u16,(SP–u5){0 ≤ u16 < 216} 1 → (SP–u5)i (i denotes bits=1 in #u16) if (all selected bits were set), then 1 → T, else 0 → T {0 ≤ u5 < 64,W} BMTSET.W #u16,(SP+s16){0 ≤ u16 < 216} 1 → (SP+s16)i 15 15 if (all selected bits were set), then 1 → T, else 0 → T {–2 ≤ s16 < 2 ,W} BMTSET.W #u16,(Rn){0 ≤ u16 < 216} 1 → (Rn)i if (all selected bits were set), then 1 → T, else 0 → T BMTSET.
BMTSET.W Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if all the bits selected by the mask are set, or the memory access fails; cleared otherwise. Example bmtset.
BMTSET.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 BMTSET.W #u16,(SP–u5) 3 3 3 3 3 2 2 0 0 0 1 1 0 i i i A A A A A 1 0 1 i i i i i i i i i 8 7 0 3 1 3 2 3 i 0 0 1 A A A A A A A A A A A A A 1 0 i i 1 i 0 i 1 i 1 i 1 i 0 i 0 A A A i i 8 7 i i i i i 0 i i 1 i 1 i 0 0 0 0 1 0 1 1 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i 8 7 15 BMTSET.W #u16,(a16) 0 0 15 BMTSET.
BMTSTC BMTSTC Bit-Masked Test a 16-Bit Operand If Clear (BMU) BMTSTC Operation Assembler Syntax if (#u16 & C1.H) == $0000, then 1 → T, else 0 → T BMTSTC #u16,C1.H {0 ≤ u16 < 216} if (#u16 & C1.L) == $0000, then 1 → T, else 0 → T BMTSTC #u16,C1.L {0 ≤ u16 < 216} if (#u16 & DR.H) == $0000, then 1 → T, else 0 → T BMTSTC #u16,DR.H {0 ≤ u16 < 216} if (#u16 & DR.L) == $0000, then 1 → T, else 0 → T BMTSTC #u16,DR.
BMTSTC Register/Memory Address Before L7:D7 After $0:$0024A60000 SR $00E40000 $00E40002 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMTSTC #u16,C1.
BMTSTC.W BMTSTC.W BMTSTC.W Bit-Masked Test a 16-Bit Operand in Memory If Clear (BMU) Operation Assembler Syntax if (#u16 & (SP-u5)) == $0000, then 1→T else 0→T BMTSTC.W #u16,(SP–u5){0 ≤ u16 < 216} {0 ≤ u5 < 64,W} if (#u16 & (SP+s16)) == $0000, then 1→T else 0→T BMTSTC.W #u16,(SP+s16){0 ≤ u16 < 216} {–215 ≤ s16 < 215,W} if (#u16 & (Rn)) == $0000, then 1→T else 0→T BMTSTC.W #u16,(Rn){0 ≤ u16 < 216} if (#u16 & (a16)) == $0000, then 1→T else 0→T BMTSTC.
BMTSTC.W Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if all the bits selected by the mask are clear, cleared otherwise. Example bmtstc.
BMTSTC.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 BMTSTC.W #u16,(SP–u5) 3 3 3 3 3 2 2 0 0 0 1 0 0 i i i A A A A A 1 0 1 i i i i i i i i i 8 7 0 3 1 3 2 3 i 0 0 1 A A A A A A A A A A A A A 1 0 i i 0 i 0 i 1 i 1 i 1 i 0 i 0 A A A i i 8 7 i i i i i 0 i i 1 i 1 i 0 0 0 0 1 0 1 0 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i 8 7 15 BMTSTC.W #u16,(a16) 0 0 15 BMTSTC.
BMTSTS BMTSTS Bit-Masked Test a 16-Bit Operand If Set (BMU) BMTSTS Operation Assembler Syntax if (#u16 & ~C1.H = $0000), then 1 → T, else 0 → T BMTSTS #u16,C1.H {0 ≤ u16 < 216} if (#u16 & ~C1.L = $0000), then 1 → T, else 0 → T BMTSTS #u16,C1.L {0 ≤ u16 < 216} if (#u16 & ~DR.H = $0000), then 1 → T, else 0 → T BMTSTS #u16,DR.H {0 ≤ u16 < 216} if (#u16 & ~DR.L = $0000), then 1 → T, else 0 → T BMTSTS #u16,DR.
BMTSTS Example bmtsts #$24a6,d7.h Register/Memory Address Before After immediate $24A60000 L7:D7 $0:$0024A60560 SR $00E40000 $00E40002 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BMTSTS #u16,C1.
BMTSTS.W BMTSTS.W BMTSTS.W Bit-Masked Test a 16-Bit Operand in Memory (BMU) Operation Assembler Syntax if (#u16 & ~(SP–u5) = $0000), then 1→ T, else 0 → T BMTSTS.W #u16,(SP–u5){0 ≤ u16 < 216} {0 ≤ u5 < 64,W} if (#u16 & ~(SP+s16) = $0000), then 1→ T, else 0 → T BMTSTS.W #u16,(SP+s16){0 ≤ u16 < 216} {–215 ≤ s16 < 215,W} if (#u16 & ~(Rn) = $0000), then 1→ T, else 0 → T BMTSTS.W #u16,(Rn){0 ≤ u16 < 216} if (#u16 & ~(a16) = $0000), then 1→ T, else 0 → T BMTSTS.
BMTSTS.W Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if all the selected bits in the mask are set, or the memory access fails; cleared otherwise. Example bmtsts.
BMTSTS.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 BMTSTS.W #u16,(SP–u5) 3 3 3 3 3 2 2 0 0 0 1 0 1 i i i A A A A A 1 0 1 i i i i i i i i i 8 7 0 3 1 3 2 3 i 0 0 1 A A A A A A A A A A A A A 1 0 i i 0 i 0 i 1 i 1 i 1 i 0 i 1 A A A i i 8 7 i i i i i 0 i i 1 i 1 i 0 0 0 0 1 0 1 0 1 i i i 0 1 R R R 1 0 1 i i i i i i i i i i 8 7 15 BMTSTS.W #u16,(a16) 0 0 15 BMTSTS.
BRA BRA Branch (AGU) Operation Assembler Syntax PC + displacement → PC BRA label BRA Description BRA >label BRA
BRA Example bra _label2 nop nop ; disassembled: bra >*+$8 _label2 Register/Memory Address Before After _label (displacement) $0000 000A PC $0000 0002 $0000 000A Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BRA label 7 a 0 0 7 0 0 0 1 1 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a Instruction Fields displacement (
BRAD BRAD Branch Using a Delay Slot (AGU) Operation Assembler Syntax PC + displacement → PC BRAD label BRAD Description BRAD label Causes program execution to continue at location PC + displacement after executing the execution set immediately following the execution set containing the BRAD instruction (called the delay slot).
BRAD Register/Memory Address Before After lbl3 (displacement) $0000 000A PC $0000 0004 $0000 000E Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BRAD label 7 a 0 0 7 0 0 0 1 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: The branch uses 4 cycles minus the execution time used by execution set in the delay slot.
BREAK BREAK Terminate the Loop and Branch to an Address (AGU) Operation Assembler Syntax PC + displacement → PC 0 → LFn BREAK label BREAK Description BREAK label Exits the active loop n unconditionally before the active loop counter (LCn) equals one, and clears the active loop flag. The program execution continues at “label.” The displacement, calculated by the assembler and linker, is a two’s complement integer that represents the relative distance from the current PC to the destination label.
BREAK Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BREAK label 2 4 4 8 0 0 0 0 7 0 0 0 1 0 A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a Instruction Fields displacement A-104 aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit.
BSR BSR BSR Branch to Subroutine (AGU) Operation Assembler Syntax (Next PC) → (SP); SR → (SP + 4); SP + 8 → SP; PC + displacement → PC; (Next PC)→ RAS BSR label Description BSR label Pushes the next PC and SR onto the stack and causes program execution to continue at location PC + displacement. The displacement, calculated by the assembler and linker, is a two’s complement integer that represents the relative distance from the current PC to the destination label.
BSR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 BSR label 2 4 4 1 8 7 0 0 0 0 0 0 1 A A A A A A A A 1 0 0 1 0 a 0 1 1 0 0 A A A A A A A A A A A A a 15 8 7 0 1 A A A 1 1 a a a Instruction Fields displacement (label) A-106 SC140 DSP Core Reference Manual
BSRD BSRD Branch to Subroutine Using a Delay Slot (AGU) Operation Assembler Syntax (next* PC) → (SP); SR → (SP + 4); SP + 8 → SP; PC + displacement → PC, (next* PC)→RAS BSRD label BSRD Description BSRD label Executes the execution set in the delay slot, then pushes the next* PC (the PC of the execution set after the delay slot) and SR onto the stack, and causes program execution to continue at location PC + displacement.
BSRD Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 BSRD label 7 1 7 0 0 0 1 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: The branch uses 4 cycles minus the execution time used by the execution set in the delay slot. The cycle count for this instruction cannot be less than 2 cycles.
BT BT BT Branch If True (AGU) Operation Assembler Syntax If T==1, then PC + displacement → PC BT label Description BT label Branches to label if the true bit is set. If the T bit is set, the program continues executing at location PC + displacement. If the T bit is cleared, the PC is updated to point to the next execution set, and the program continues executing sequentially.
BT Register/Memory Address Before BT After d2 $0000 $0000 pc $0006 $0016 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 BT label 7 0 7 1 A A A 1 0 0 0 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: If the branch is not taken, it uses 1 cycle. If the branch is taken, it uses 4 cycles.
BTD BTD Branch If True Using a Delay Slot (AGU) Operation Assembler Syntax If T==1, then PC + displacement → PC BTD label BTD Description BTD label Branches to label if the true bit is set. If the T bit is set, the program continues executing at location PC + displacement. If the T bit is cleared, the PC is updated to point to the next execution set, and the program continues executing sequentially.
BTD Register/Memory Address Before BTD After d1 $0035 $002A d2 $0000 $0000 d4 $0000 $001A pc $0006 $0016 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 BTD label 2 1/4 4 8 0 a 1 0 0 A A A A A A A A 0 15 BTD 7 0 7 0 A A A 1 0 0 0 1 1 a a a 1 0 0 A A A A A A A A A A A A a Note 1: If the branch is not taken, it uses 1 cycle.
CLB C-D CLB Count Leading Bits (DALU) CLB Operation Assembler Syntax If Da[39] == 0, then 9 – (number of consecutive leading zeros in Da[39:0]) → Dn else 9 – (number of consecutive leading ones in Da[39:0]) → Dn CLB Da,Dn Description CLB Da,Dn Counts the leading 0s or 1s according to bit 39 of source Da. It scans bits [39:0] of Da starting from bit 39. The operation loads nine minus the number of consecutive leading 0s or 1s into destination Dn. The result is sign-extended.
CLB Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 CLB Da,Dn 1 2 1 8 1 0 1 0 0 7 F F F 0 0 0 1 0 J J J Instruction Fields Da JJJ Single Source Data Register 000 001 Note: Dn 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
CLR CLR CLR Clear a Data Register (DALU) Operation Assembler Syntax 0 → Dn CLR Dn Description CLR Dn Clears a data register (Dn). Note: CLR Dn is assembler mapped to SUB Da,Da,Dn where Dn is the register being cleared and Da is an arbitrary register assigned by the assembler for programming rule G.G.5. Any (Da-Da) results in zero being stored in Dn. Da assignment uses the low data registers (D0-D7) where possible to avoid using a prefix. Status and Conditions that Affect Instruction None.
CLR Instruction Fields Dn FFF Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 11110 D6 11 D7 Note: Da JJJJJ 10000 Note: Da Source Data Register D0 11100 D2 10100 D4 This instruction can specify D8-D15 as operands by using a prefix. jj Source Data Register 00 Note: A-116 This instruction can specify D8-D15 as operands by using a prefix. D1 01 D3 10 D5 If registers D8–D15 are accessed instead of D0–D7, a prefix is used.
CMPEQ CMPEQ CMPEQ Compare for Equal (DALU) Operation Assembler Syntax If Da == Dn, then 1→ T, else 0 → T CMPEQ Da,Dn Description CMPEQ Da,Dn Compares the 40-bit contents of two data registers (Da and Dn), setting the T bit if they are equal, and clearing the T bit if they are not. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Sets T bit if equal, otherwise cleared.
CMPEQ Dn FFF 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-118 Single Source/Destination Data Register This instruction can specify D8-D15 as operands by using a prefix.
CMPEQ.W CMPEQ.W Compare for Equal (DALU) CMPEQ.W Operation Assembler Syntax If #u5 == Dn, then 1 → T, else 0 → T CMPEQ.W #u5,Dn {0 ≤ u5 < 32} If #s16 == Dn, then 1 → T, else 0 → T CMPEQ.W #s16,Dn {–215 ≤ s16 < 215} Description CMPEQ.W #u5,Dn Compares an immediate unsigned 5-bit value (range 0–31) with a data register (Dn) for equality. The immediate value is right-aligned and zero-extended. CMPEQ.
CMPEQ.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 CMPEQ.W #u5,Dn 1 1 2 CMPEQ.
CMPEQA CMPEQA Compare for Equal (AGU) Operation Assembler Syntax If rx == Rx, then 1 → T, else 0 → T CMPEQA rx,Rx CMPEQA Description CMPEQA rx,Rx Compares two AGU registers (rx and Rx) for equality. Note that a register cannot be compared to itself using this instruction. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR.
CMPEQA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 CMPEQA rx,Rx 1 2 1 8 1 1 7 0 R R R R 1 0 0 1 0 r r r r Instruction Fields rx rrrr 0000 N0 0100 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx — 1000 R0 1100 R4 This instruction can specify R8-R15 as operands by using a high register prefix.
CMPGT CMPGT CMPGT Compare for Greater Than (DALU) Operation Assembler Syntax Dn > Da → T CMPGT Da,Dn Description CMPGT Da,Dn Compares two data registers (Da and Dn). The T bit is set if the signed value in the second data register (Dn) is greater than the signed value in the first (Da); T is cleared otherwise. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Sets T bit if Dn > Da, otherwise cleared.
CMPGT Dn FFF 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-124 Single Source/Destination Data Register This instruction can specify D8-D15 as operands by using a prefix.
CMPGT.W CMPGT.W Compare for Greater Than (DALU) CMPGT.W Operation Assembler Syntax Dn > #u5 → T CMPGT.W #u5,Dn {0 ≤ u5 < 32} Dn > #s16 → T CMPGT.W #s16,Dn {–215 ≤ s16 < 215} Description These instructions set the T bit if the content of a signed data register (Dn) is greater than the immediate value, or clear the T bit if the content of the data register is not greater than the immediate value. CMPGT.
CMPGT.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 CMPGT.W #u5,Dn 1 1 2 CMPGT.
CMPGTA CMPGTA Compare for Greater Than (AGU) Operation Assembler Syntax Rx > rx → T CMPGTA rx,Rx CMPGTA Description CMPGTA rx,Rx Compares two signed AGU registers (rx and Rx) and sets the T bit if the second AGU register is greater than the first, or clears the T bit if the second AGU register is not greater than the first. Note that a register cannot be compared to itself using this instruction.
CMPGTA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 CMPGTA rx,Rx 1 2 1 8 1 1 7 0 R R R R 1 0 0 0 1 r r r r Instruction Fields rx rrrr 0000 N0 0100 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx — 1000 R0 1100 R4 This instruction can specify R8-R15 as operands by using a high register prefix.
CMPHI CMPHI CMPHI Unsigned Compare for Higher (DALU) Operation Assembler Syntax Dn > Da → T CMPHI Da,Dn Description CMPHI Da,Dn Compares the unsigned value in bits 31:0 of two data registers (Da and Dn) to determine which is greater. It sets the T bit if the unsigned value of Dn[31:0] is greater than the unsigned value of Da[31:0]. Otherwise, it clears the T bit. Status and Conditions that Affect Instruction None.
CMPHI Dn FFF 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-130 Single Source/Destination Data Register This instruction can specify D8-D15 as operands by using a prefix.
CMPHIA CMPHIA Unsigned Compare for Higher (AGU) Operation Assembler Syntax Rx > rx → T CMPHIA rx,Rx CMPHIA Description CMPHIA rx,Rx Compares the unsigned value in two AGU registers (rx and Rx) to determine which is greater. It sets the T bit if the unsigned value of Rx is greater than the unsigned value of rx. It clears the T bit if the unsigned value of Rx is not greater than the unsigned value of rx. Note that a register cannot be compared to itself using this instruction.
CMPHIA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 CMPHIA rx,Rx 1 2 1 8 1 1 7 0 R R R R 1 0 0 0 0 r r r r Instruction Fields rx rrrr 0000 N0 0100 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx — 1000 R0 1100 R4 This instruction can specify R8-R15 as operands by using a high register prefix.
CONT CONT Continue to the Next Loop Iteration (AGU) Operation If LCn > 1, CONT Assembler Syntax then SAn → PC, LCn-1 → LCn else PC + displacement → PC 0 → LFn, 0 → LCn CONT label Description CONT label Continues the active loop n from the start address of the loop (SAn) if its loop counter (LCn) is greater than one. Otherwise, it clears the active loop flag (LFn) and branches to an address determined by a 16-bit signed displacement [–216 ≤ displacement < 216,W] added to the PC.
CONT Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 CONT label 2 3/4 4 8 0 0 0 1 7 1 A A A 0 0 0 0 1 1 0 0 A A A A A A A A A A A A a 0 0 1 1 Note 1: If LC > 1, CONT uses 3 cycles. If LC ≤ 1, CONT uses 4 cycles. Instruction Fields displacement A-134 aAAAAAAAAAAAAAAA0 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit.
CONTD CONTD Continue to Next Loop Iteration Using a Delay Slot (AGU) Operation If LCn > 1, CONTD Assembler Syntax then SAn → PC, LCn-1 → LCn else PC + displacement → PC 0 → LFn, 0 → LCn CONTD label Description CONTD label Continues the active loop n from the start address of the loop (SAn) if its loop counter (LCn) is greater than one. Otherwise, it clears the active loop flag (LFn), and branches to an address determined by a 16-bit signed displacement [–216 ≤ displacement < 216,W] added to the PC.
CONTD loopend0 lbl3 add d0,d1,d2 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 CONTD label 2 3/4 4 8 0 0 0 1 7 0 A A A 0 0 0 0 1 1 0 0 A A A A A A A A A A A A a 0 0 1 1 Note 1: If LC > 1, CONTD uses 3 cycles. If LC = 1, CONTD uses 4 cycles. In both cases, the cycles are decreased by the time used for the execution set in the delay slot. The cycle count for this instruction cannot be less than 1 cycle.
DEBUG DEBUG DEBUG Enter Debug Mode (AGU) Operation Assembler Syntax DEBUG Description DEBUG Causes the device to enter the debug state. It is an Enhanced On-chip Emulator (EOnCE) dedicated instruction that is used for debugging. This instruction cannot be grouped with another debug instruction. Status and Conditions that Affect Instruction None Status and Conditions Changed by Instruction None.
DEBUGEV DEBUGEV DEBUGEV Signal a Debug Event (AGU) Operation Assembler Syntax DEBUGEV Description DEBUGEV Generates a debug event. It is an EOnCE dedicated instruction. If the EOnCE has not been enabled since reset, issuing DEBUGEV has no effect. If the EOnCE is enabled, the effect of this instruction depends on the programming of EOnCE control registers. Receipt of an EOnCE event can cause the core to enter the debug mode, generate an exception, or enable the trace buffer.
DECA DECA DECA Decrement a Register (AGU) Operation Assembler Syntax Rx – 1 → Rx DECA Rx Description DECA Rx Subtracts one from an AGU register (Rx). SP cannot be used as a destination of this instruction. Note: The assembler maps this instruction to SUBA #u5,Rx; where #u5 = 1. Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL.
DECA #u5 A-140 iiiii 5-bit unsigned immediate data = 1, set by the assembler SC140 DSP Core Reference Manual
DECEQ DECEQ DECEQ Decrement and Set T If Equal Zero (DALU) Operation Assembler Syntax Dn – 1 → Dn; if Dn==0, then 1→ T, else 0 → T DECEQ Dn Description DECEQ Dn Decrements a data register (Dn) and sets the T bit if the result is equal to zero. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[0] C Calculates and updates the carry bit in the status register. SR[1] T Set if result = 0, cleared otherwise.
DECEQ Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-142 Single Source/Destination Data Register 000 This instruction can specify D8-D15 as operands by using a prefix.
DECEQA DECEQA DECEQA Decrement and Set T If Equal Zero (AGU) Operation Assembler Syntax Rx – 1 → Rx; if Rx==0, then 1 → T, else 0 → T DECEQA Rx Description DECEQA Rx Decrements an AGU register (Rx) and sets the T bit if the result is zero. SP cannot be used as an operand of this instruction. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if result = 0, cleared otherwise.
DECGE DECGE DECGE Decrement and Set T If Greater Than or Equal to Zero (DALU) Operation Assembler Syntax Dn – 1 → Dn; Dn≥0 → T DECGE Dn Description DECGE Dn Decrements a data register (Dn) and sets the T bit if the result is greater than or equal to zero. In the case of an arithmetic overflow (DECGE on the value $80 0000 0000), the T bit will not be set. Status and Conditions that Affect Instruction None.
DECGE Instruction Fields Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
DECGEA DECGEA Decrement and Set T If Greater Than or Equal to Zero (AGU) Operation Rx – 1 → Rx; DECGEA Assembler Syntax Rx ≥ 0 → T DECGEA Rx Description DECGEA Rx Decrements an AGU register (Rx) and sets the T bit if the result is greater than or equal to zero. In case there is an arithmetic overflow (DECGEA on the value of $80000000), the T bit will not be set by this instruction. SP cannot be used as an operand of this instruction. Status and Conditions that Affect Instruction None.
DECGEA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 DECGEA Rx 1 2 1 8 1 1 7 0 R R R R 1 0 1 1 1 0 1 1 1 Instruction Fields Rx RRRR AGU Source/Destination Register 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 — 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: This instruction can specify R8-R15 as operands by using a high register prefix. SP cannot be used by this instruction.
DI DI DI Disable Interrupts (AGU) Operation Assembler Syntax 1 → DI DI Description DI Sets the DI bit in the status register in order to disable interrupts. The effect is immediate, so the instructions that execute in the same execution set as well as later execution sets are not interruptible by maskable interrupts. Non-maskable interrupts and exceptions are not disabled by this bit.
DI 15 DI 1 1 SC140 DSP Core Reference Manual 4 1 0 0 1 1 1 1 8 7 1 0 0 1 1 1 1 1 0 1 A-149
DIV DIV DIV Divide Iteration (DALU) Operation Assembler Syntax If Dn[39] ⊕ Da[39] = 1, then 2 * Dn + C + (Da & $FF FFFF 0000) → Dn else 2 * Dn + C – (Da & $FF FFFF 0000) → Dn where ⊕ denotes the bitwise exclusive OR operator. DIV Da,Dn Description DIV Da,Dn This instruction is used iteratively to divide the destination operand Dn by the source operand Da and store the result in the destination operand Dn.
DIV 3. Calculate the next quotient bit and the new partial remainder: The 16-bit signed divisor in Da.H is either added to or subtracted from Dn.H, and the result is stored back into Dn.H. If the result of the exclusive OR operation previously described was a “1” (i.e., the sign bits were different), Da.H is added to Dn.H. If the result of the exclusive OR operation was a “0” (i.e., the sign bits were the same), Da.H is subtracted from Dn.H.
DIV Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 DIV Da,Dn Note: 1 1 0 8 * 1 1 0 0 7 F F F 0 1 0 1 0 J J J ** indicates serial grouping encoding. Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Da This instruction can specify D8-D15 as operands by using a prefix.
DMACSS DMACSS DMACSS Multiply Signed By Signed and Accumulate With Right Shifted Data Register (DALU) Operation Assembler Syntax [Dn>>16] + Dc.H * Dd.H → Dn (Dc signed, Dd signed) DMACSS Dc,Dd,Dn Description DMACSS Dc,Dd,Dn Shifts Dn 16 bits to the right with bit 39 sign-extended into bits [39:24]. Adds the result to the product of signed fractions in Dc.H and Dd.H. Places the result into Dn. Dc and Dd are a data register pair. The operands are in the HP of each register.
DMACSS Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 DMACSS Dc,Dd,Dn Note: 1 1 1 0 8 * 1 0 1 1 7 F F F 0 1 1 1 0 1 e e ** indicates serial grouping encoding. Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix.
DMACSU DMACSU DMACSU Multiply Signed By Unsigned and Accumulate With Right Shifted Data Register (DALU) Operation Assembler Syntax [Dn>>16] + Dc.H * Dd.L → Dn (Dc signed, Dd unsigned) DMACSU Dc,Dd,Dn Description DMACSU Dc,Dd,Dn Shifts Dn 16 bits to the right with bit 39 sign-extended into bits [39:24]. Adds the result to the product of a signed fraction in Dc.H and an unsigned fraction in Dd.L. Places the result into Dn. Dc and Dd are a data register pair.
DMACSU Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix. FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-156 D0,D1 This instruction can specify D8-D15 as operands by using a prefix.
DOENn DOENn DO Enable Long Loop (AGU) Operation Assembler Syntax #u6 → LCn; 1 → LFn DOENn #u6 {0 ≤ u6 < 64} #u16 → LCn; 1 → LFn DOENn #u16 {0 ≤ u16 < 216} DR → LCn; 1 → LFn DOENn DR DOENn Description This instruction initializes the selected loop as a long loop by loading the iteration count into the respective loop counter and setting the respective loop flag in the SR. After this instruction is executed, the loop becomes active.
DOENn Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 DOENn #u6 1 1 4 DOENn #u16 2 1 4 1 0 1 0 0 n n 0 8 7 0 0 1 0 0 0 n n 1 0 0 i i i i i 8 7 0 0 1 1 0 n n 0 15 1 1 4 7 0 15 DOENn DR 8 1 0 1 i i i i i i i i i 0 0 1 0 0 i i i i i i i i 1 0 0 H H H H 0 0 Instruction Fields n Loop Identifier 00 DR Loop 0 01 0000 D0 0100 D4 0001 D1 0101 0010 D2 D3 0011 Note: #u6 #u16 A-158 Loop 2 11
DOENSHn DOENSHn Do Enable Short Loop (AGU) Operation #u6 → LCn; Assembler Syntax 1 → LFn; #u16 → LCn; DR → LCn; DOENSHn 1 → SLF 1 → LFn; 1 → LFn; DOENSHn #u6 {0 ≤ u6 < 64} 1 → SLF DOENSHn #u16 {0 ≤ u16 < 216} 1 → SLF DOENSHn DR Description This instruction initializes the selected loop as a short loop by loading the iteration count to the respective loop counter and setting the SLF and respective loop flag in the SR. After this instruction is executed, the loop becomes active.
DOENSHn Register/Memory Address Before After SR $00E4 0000 $A0E4 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 DOENSHn #u6 1 1 4 DOENSHn #u16 2 1 4 8 7 0 0 1 0 1 n n 0 8 7 0 0 1 0 0 1 n n 1 0 0 i i i i i 8 7 0 0 1 1 1 n n 0 1 15 15 1 DOENSHn DR 1 4 1 0 1 i i i i i i i i i 0 0 1 0 0 i i i i i i i i 1 0 0 H H H H 0 0 Instruction Fields n Loop Identifier 00 DR #u16 A-160 01 HHHH Lo
DOSETUPn DOSETUPn DOSETUPn Setup Long Loop Start Address (AGU) Operation Assembler Syntax PC + displacement → SAn DOSETUPn label Description DOSETUPn label This instruction is required for initialization of a long loop, not short loops. In case the loop is nested, the DOSETUPn instruction can be placed outside the enveloping loop as long as SA (Start Address) is not changed by instructions in the loop. DOSETUPn loads a loop start address register (SAn).
DOSETUPn Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 DOSETUPn label 2 1 4 8 0 1 0 n 7 0 0 0 1 n A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a Instruction Fields n Loop Identifier 00 displacement A-162 Loop 0 01 aAAAAAAAAAAAAAAA0 Loop 1 10 Loop 2 11 Loop 3 16-bit signed PC relative displacement. The encoding is the displacement with bit 0 stripped and replaced by the sign bit.
EI E-J EI EI Enable Interrupts (AGU) Operation Assembler Syntax 0 → DI EI Description EI Clears the DI bit in the status register to enable interrupts. The EI instruction and its counterpart, the DI instruction, can be used to delimit a non-interruptible code sequence. For example, a non-interruptible read-modify-write sequence of execution sets can be written like this: DI read modify EI write Where read, modify, and write represent instruction(s).
EI A-164 SC140 DSP Core Reference Manual
EOR EOR Bitwise Exclusive OR (DALU) Operation Assembler Syntax Da ⊕ Dn → Dn EOR Da,Dn EOR Description EOR Da,Dn Performs a bitwise exclusive OR between two data registers (Da and Dn) and stores the result in a destination data register (Dn). Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register.
EOR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 EOR Da,Dn 1 2 1 8 1 0 1 1 1 7 F F F 0 0 0 1 0 J J J Instruction Fields Da JJJ Single Source Data Register 000 001 Note: Dn 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
EOR EOR Bitwise Exclusive OR on a 16-Bit Operand (BMU) Operation Assembler Syntax #u16 ⊕ DR.L → DR.L EOR #u16,DR.L {0 ≤ u16 < 216} #u16 ⊕ DR.H → DR.H EOR #u16,DR.H {0 ≤ u16 < 216} EOR Description EOR #u16,DR.L Performs a bitwise exclusive OR between a 16-bit unsigned immediate value and the LP of an address register or data register (DR). Stores the result in the destination register (DR). This instruction is assembler-mapped to BMCHG #u16,DR.L with the immediate value.
EOR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 EOR #u16,DR.L 2 2 3 2 2 3 7 0 0 0 0 0 1 0 1 0 i i i 0 H H H H 1 0 1 i i i i i i i i i 8 7 15 EOR #u16,DR.
EOR.W EOR.W Bitwise Exclusive OR on a 16-Bit Operand in Memory (BMU) EOR.W Operation Assembler Syntax #u16 ⊕ (R) → (R) EOR.W #u16,(Rn){0 ≤ u16 < 216} #u16 ⊕ (SP–u5) → (SP–u5) EOR.W #u16,(SP-u5){0 ≤ u16 < 216}{0 ≤ u5 < 64,W} #u16 ⊕ (SP + s16) → (SP + s16)EOR.W #u16,(SP+s16){0 ≤ u16 < 216}{-215 ≤ s16 < 215,W} #u16 ⊕ (a16) → (a16) EOR.
EOR.W Example eor.w #$aaaa,(r0) Register/Memory Address Before After immediate $AAAA (r0) $0000 5555 $0000 FFFF Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 EOR.
EXTRACT EXTRACT Extract Signed Bit Field (DALU) Operation EXTRACT Assembler Syntax Db[(offset + width – 1):offset] → Dn[(width – 1):0] Db[offset + width – 1] → Dn[39:width] (sign-extension) width = #U6; offset = #u6 EXTRACT #U6,#u6,Db,Dn {0 ≤ U6 ≤ 40}{0 ≤ u6 ≤ 40} {#U6+#u6 ≤ 40} width = Da[13:8]; offset = Da[5:0] EXTRACT Da,Db,Dn {0 ≤ Da[13:8] ≤ 40} {0 ≤ Da[5:0] ≤ 40} {Da[13:8]+Da[5:0] ≤ 40} Description These operations extract a bit field from a source data register (Db) and place it in a destina
EXTRACT 3 9 D2 3 2 1 6 0 1111111110000110011001010100001100100001 WIDTH = 12 D4 OFFSET = 14 1111111111111111111111111111100110010101 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 EXTRACT #U6,#u6,Db,Dn 2 1 4 2 1 4 7 0 0 0 1 1 j j j 0 1 1 0 0 1 F F F 1 0 0 1 I I I I I I i i i i 8 7 15 EXTRACT Da,Db,Dn 8 i i 0 0 0 1 1 j j j 0 1 0 0 0 1 F F F 1 0 0 1 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da JJ
EXTRACTU EXTRACTU Extract Unsigned Bit Field (DALU) Operation EXTRACTU Assembler Syntax Db[(offset + width – 1):offset] → Dn[(width – 1):0] 0 → Dn[39:width] width = #U6; offset = #u6 EXTRACTU #U6,#u6,Db,Dn {0 ≤ U6 ≤ 40} {0 ≤ u6 ≤ 40} {#U6+#u6 ≤ 40} width = Da[13:8]; offset = Da[5:0] EXTRACTU Da,Db,Dn {0 ≤ Da[13:8] ≤ 40} {0 ≤ Da[5:0] ≤ 40} {Da[13:8]+Da[5:0] ≤ 40} Description These operations extract a bit field from a source data register (Db) and place it in a destination data register (Dn), right
EXTRACTU 3 9 D6 3 2 1 6 0 1111111110000110011001010100001100100001 WIDTH = 12 D7 OFFSET = 14 0000000000000000000000000000100110010101 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 EXTRACTU #U6,#u6,Da,Dn 1 4 2 1 4 7 0 0 0 1 1 j j j 0 1 1 0 0 1 F F F 1 0 0 0 I I I I I I i i i i 8 7 15 EXTRACTU Da,Db,Dn 8 i i 0 0 0 1 1 j j j 0 1 0 0 0 1 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da
IADDNC.W IADDNC.W IADDNC.W Integer Addition Without Changing the Carry Bit Not Affected by Saturation (DALU) Description IADDNC.W #s16,Dn Sign-extends the 16-bit immediate value to 40 bits and adds it to the destination data register Dn. The result is not affected by the arithmetic saturation mode. The carry bit is not affected by this instruction. This instruction is an integer (non-saturating) version of ADDNC.W. Status and Conditions that Affect Instruction None.
IFc IFc Conditionally Execute a Group or Subgroup (PREFIX) Operation IFc Assembler Syntax If T == 0, then execute group/subgroup else treat as NOP IFF group or subgroup of instructions If T == 1, then execute group/subgroup else treat as NOP IFT group or subgroup of instructions execute group/subgroup unconditionally IFA group or subgroup of instructions Description These instructions add conditional control over a group or subgroup of instructions in a VLES.
IFc Status and Conditions that Affect Instruction Register Address Bit Name Description SR[1] T True bit Status and Conditions Changed by Instruction None. Example ift move.
ILLEGAL ILLEGAL Generate an Illegal Exception Request (AGU) ILLEGAL Operation Assembler Syntax upon service: PC → (ESP); SR → (ESP + 4); SP + 8 → SP; VBA[31:12]: illegal_vector → PC; 1 → EXP 111→ I[2:0] 1 → ILIN 0→C 0→T 00 → S[1:0] 0 → SLF 0000 → LF[3:0] ILLEGAL {illegal vector = $080} Description ILLEGAL Generates an imprecise non-maskable illegal exception request. The exact place in the execution flow that the request is serviced depends on the machine state.
ILLEGAL Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[18] EXP Sets EXP to switch active stack pointer to exception stack pointer. SR[23:21] I[2:0] Set interrupt priority level to 111. EMR[0] ILIN Sets illegal instruction bit. SR[0] C Cleared SR[1] T Cleared SR[5:4] S[1:0] Cleared SR[31] SLF Cleared SR[30:27] LF[3:0] Clear loop flags.
IMAC IMAC Integer Multiply-Accumulate (DALU) Operation Assembler Syntax Dn ± (Da.L * Db.L) → Dn IMAC ±Da,Db,Dn IMAC Description IMAC ±Da,Db,Dn Performs signed integer-multiplication on the LP contents of two source data registers (Da and Db) and adds or subtracts the product to or from a destination data register (Dn). The default operation is the addition of the product to the destination register. Status and Conditions that Affect Instruction None.
IMAC –5 x 3 –15 +8 –7 $FFFB $0003 $000F $0008 $FFF9 Example 2 imac -d4,d5,d6 Register/Memory Address Before After D4 $00 1022 002A D5 $FF FF3A 000B L6:D6 $0:$00 0000 1000 $0:$00 0000 0E32 $0000 0000 $0000 0000 EMR –42 x 11 –462 +4096 3,634 $002A $000B $FE32 $1000 $0E32 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMAC ±Da,Db,Dn 1 1 1 IMAC ±Da,Da,Dn 1 1 1 0 8 * 1 0 1 0 F F F * 1 0 1 0 F F F 15 Note: 0 7 8 0 k 0 J J J J 1 1 0
IMAC Da,Db JJJJJ Data Register Pairs 00000 D0,D4 01000 D2,D4 10000 D0,D0 11000 D1,D2 00001 D0,D5 01001 D2,D5 10001 D0,D1 11001 D1,D3 00010 D0,D6 01010 D2,D6 10010 D0,D2 11010 D5,D6 00011 D0,D7 01011 D2,D7 10011 D0,D3 11011 D5,D7 00100 D1,D4 01100 D3,D4 10100 D4,D4 11100 D2,D2 00101 D1,D5 01101 D3,D5 10101 D4,D5 11101 D2,D3 00110 D1,D6 01110 D3,D6 10110 D4,D6 11110 D6,D6 00111 D1,D7 01111 D3,D7 10111 D4,D7 11111 D6,D7 Notes: 1. 2. 3.
IMACLHUU IMACLHUU IMACLHUU Integer Multiply-Accumulate Lower Unsigned By Upper Unsigned (DALU) Operation Assembler Syntax Dn + (Da.L * Db.H) → Dn IMACLHUU Da,Db,Dn Description IMACLHUU Da,Db,Dn Performs an unsigned integer multiplication of the 16-bit LP of one source data register (Da) with the 16-bit HP of another source data register (Db). It then adds the zero-extended 32-bit product to a destination data register (Dn). This instruction is optimized for multi-precision-multiplication support.
IMACLHUU Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMACLHUU Da,Db,Dn 2 1 4 8 7 0 0 0 1 1 1 0 0 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da jjj Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Db JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify
IMACUS IMACUS Integer Multiply Accumulate Unsigned By Signed (DALU) Operation Assembler Syntax Dn + (Da.L * Db.H) → Dn IMACUS Da,Db,Dn IMACUS Description IMACUS Da,Db,Dn Performs a signed integer multiplication of the unsigned 16-bit LP of one source data register (Da) with the signed 16-bit HP of another source data register (Db). It then adds the sign-extended 32-bit product to a destination data register (Dn). This instruction is optimized for multi-precision-multiplication support.
IMACUS 2 x –64 –128 +0 -128 $0002 $FFC0 $FF80 $0000 $FF80 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMACUS Da,Db,Dn 2 1 4 8 7 0 0 1 1 0 0 0 0 j j j 0 0 F F F 0 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da jjj Single Source/Destination Data Register 000 001 Note: Db D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
IMPY IMPY IMPY Integer Multiply (DALU) Operation Assembler Syntax Da.L * Db.L → Dn IMPY Da,Db,Dn Description IMPY Da,Db,Dn Performs a signed integer multiplication on the low portions of two signed source data registers (Da, Db) and stores the product in a destination data register (Dn). Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register.
IMPY Instruction Fields Da,Da jj Data Register Pairs 00 Note: Da,Db D1,D1 10 D5,D5 11 D7,D7 Data Register Pairs 00000 D0,D4 01000 D2,D4 10000 D0,D0 11000 D1,D2 00001 D0,D5 01001 D2,D5 10001 D0,D1 11001 D1,D3 00010 D0,D6 01010 D2,D6 10010 D0,D2 11010 D5,D6 00011 D0,D7 01011 D2,D7 10011 D0,D3 11011 D5,D7 00100 D1,D4 01100 D3,D4 10100 D4,D4 11100 D2,D2 00101 D1,D5 01101 D3,D5 10101 D4,D5 11101 D2,D3 00110 D1,D6 01110 D3,D6 10110 D4,D6 11110 D6,D
IMPY.W IMPY.W Signed Immediate Integer Multiply (DALU) IMPY.W Operation Assembler Syntax #s16 * Dn.L → Dn IMPY.W #s16,Dn {–215 ≤ s16 < 215} Description IMPY.W #s16,Dn Performs a signed integer multiplication on the low portion of a source data register (Dn) and an immediate signed 16-bit word. It then stores the result in a destination data register (Dn). Status and Conditions that Affect Instruction None.
IMPY.W –8 x –2 +16 $FFF8 $FFFE $0010 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMPY.W #s16,Dn 2 1 4 8 7 0 0 0 1 1 1 1 1 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: #s16 A-190 Single Source/Destination Data Register 000 This instruction can specify D8-D15 as operands by using a prefix.
IMPYHLUU IMPYHLUU Integer Multiply Upper Unsigned By Lower Unsigned (DALU) IMPYHLUU Operation Assembler Syntax Da.H * Db.L → Dn IMPYHLUU Da,Db,Dn Description IMPYHLUU Da,Db,Dn Performs an unsigned integer multiplication on the 16-bit HP of one source data register (Da) and the 16-bit LP of another source data register (Db). It then stores the zero-extended 32-bit result in a destination data register (Dn). Status and Conditions that Affect Instruction None.
IMPYHLUU Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMPYHLUU Da,Db,Dn 2 1 4 8 7 0 0 0 1 1 1 0 1 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da jjj Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Db JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify
IMPYSU IMPYSU Integer Multiply Signed By Unsigned (DALU) Operation Assembler Syntax Da.H * Db.L → Dn IMPYSU Da,Db,Dn IMPYSU Description IMPYSU Da,Db,Dn Performs a signed integer multiplication on the signed 16-bit HP of one source data register (Da) and the unsigned 16-bit LP of a second source data register (Db). It then stores the sign-extended 32-bit result in a destination data register (Dn). Status and Conditions that Affect Instruction None.
IMPYSU Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 IMPYSU Da,Db,Dn 2 1 4 8 7 0 0 0 1 1 0 1 0 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da jjj Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Db JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D
IMPYUU IMPYUU IMPYUU Integer Multiply Unsigned By Unsigned (DALU) Operation Assembler Syntax Da.L * Db.L → Dn IMPYUU Da,Db,Dn Description IMPYUU Da,Db,Dn Performs an unsigned integer multiplication on the 16-bit LP (Da) of one data register and the16-bit LP of another data register (Db). It then stores the zero-extended 32-bit result in a data register (Dn). Status and Conditions that Affect Instruction None.
IMPYUU Db JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-196 This instruction can specify D8-D15 as operands by using a prefix. This instruction can specify D8-D15 as operands by using a prefix.
INC INC Increment a Data Register By One (DALU) Operation Assembler Syntax Dn + 1 → Dn INC Dn INC Description INC Dn Adds one to a data register (Dn). Note: The assembler maps this instruction to ADD #u5,Dn, where #u5 = 1. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode. SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the Ln bit calculation.
INC Example 2 inc d15 Register/Memory Address Before SR L15:D15 After $00E0 0004 $00E0 0004 $0:$00 7FFF FFFF $0:$00 7FFF FFFF EMR $0000 0004 Arithmetic saturation mode set, SR[2], 32-bit overflow indicated in EMR[2]. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 INC Dn Note: 1 1 0 8 * 1 1 1 0 7 F F F 0 1 0 0 0 0 0 1 ** indicates serial grouping encoding.
INC.F INC.F Increment HP of a Data Register by One (DALU) Operation Assembler Syntax Dn + $00:00010000 → Dn INC.F Dn INC.F Description INC.F Dn Adds one to the HP of a data register (Dn). Can be used to increment a 16-bit fraction. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode. SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the Ln bit calculation.
INC.F Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 INC.F Dn Note: 1 1 0 8 * 1 0 0 1 7 F F F 0 1 1 0 0 1 1 1 ** indicates serial grouping encoding. Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-200 Single Source/Destination Data Register 000 This instruction can specify D8-D15 as operands by using a prefix.
INCA INCA Increment Register (AGU) Operation Assembler Syntax Rx + 1 → Rx INCA Rx INCA Description INCA Rx Adds one to an AGU register (Rx). The stack pointer (SP) cannot be used as an operand by this instruction. Note: The assembler maps this instruction to ADDA #u5,Rx, where #u5 = 1. Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL.
INCA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 INCA Rx 1 2 1 8 1 1 7 0 R R R R 0 0 1 0 i i i i i Instruction Fields Rx RRRR 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 — 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: #u5 A-202 AGU Source/Destination Register This instruction can specify R8-R15 as operands by using a high register prefix.
INSERT INSERT INSERT Insert Bit Field (DALU) Operation Assembler Syntax Db[(width – 1):0] → Dn[(offset + width – 1):offset] width = #U6; offset = #u6 INSERT #U6,#u6,Db,Dn {0 ≤ U6 ≤ 40} {0 ≤ u6 ≤ 40}[#U6 + #u6 ≤ 40] width = Da[13:8]; offset = Da[5:0] INSERT Da,Db,Dn {0 ≤ Da[5:0] ≤ 40} {0 ≤ Da[13:8] ≤ 16}{Da[13:8] + Da[5:0] ≤ 40} Description These operations insert a bit field from a source data register (Db) into the destination data register (Dn).
INSERT Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 INSERT #U6,#u6,Db,Dn 2 1 4 2 1 4 7 0 0 0 1 1 j j j 0 1 1 1 0 1 F F F 1 0 0 0 I I I I I I i i i i 8 7 15 INSERT Da,Db,Dn 8 i i 0 0 0 1 1 j j j 0 1 0 1 0 1 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 001 D1 011 D3 101 D5 Note: This instruction can specify D8-D15 as operands by using
JF JF Jump If False (AGU) Operation Assembler Syntax If T==0, then label → PC JF label {0 ≤ label < 232,W} If T==0, then Rn → PC JF Rn JF Description If the T bit is cleared, program execution continues at a specified 32-bit memory destination address. If the T bit is set, the PC is updated to point to the next execution set. Program execution continues sequentially. The destination address cannot be in the middle of an execution set.
JF Register/Memory Address Before After d1 $00 0000 0000 $00 0000 0029 d2 $00 0000 0000 $00 0000 0000 d4 $00 0000 0000 $00 0000 001A pc $0000 0006 $0000 0016 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 3 JF label 1/4 3 0 8 0 1 1 0 1 1 1 1/4 4 0 1 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a 15 JF Rn 7 1 0 0 1 a a 8 7 1 R R R 0 a a a a a a a 0 1 1 0 0 1 1 1 Note 1: If the branch is not
JFD JFD Jump If False Using a Delay Slot (AGU) Operation Assembler Syntax If T==0, then label → PC JFD label [0 ≤ label < 232,W] If T==0, then Rn → PC JFD Rn JFD Description If the T bit is cleared, program execution continues at a specified 32-bit memory destination address after executing the execution set in the delay slot. If the T bit is set, the PC is updated to point to the next execution set and program execution continues sequentially.
JFD Register/Memory Address Before After SR $00E0 0000 D1 $00 0000 0000 $00 0000 002A D2 $00 0000 0000 $00 0000 0000 D4 $00 0000 0000 $00 0000 001A PC $0000 0006 $0000 0016 Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 3 JFD label 1/4 3 0 8 0 1 1 0 1 1 1 1/4 4 0 0 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a 15 JFD Rn 7 1 0 0 1 a a 8 7 1 R R R 0 a a a a a a a 0 1 1 0 0 1 1 0 Note 1: I
JFD JMP JMP Jump (AGU) Operation Assembler Syntax label → PC JMP label {0 ≤ label < 232,W} Rn → PC JMP Rn Description These operations continue program execution at a specified 32-bit memory destination address. The destination address cannot be in the middle of an execution set. JMP label Jumps to an absolute memory address specified by a label. The assembler and the linker calculate the destination address from the label. JMP Rn Jumps to a memory address specified by an address register (Rn).
JFD Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3 JMP label 3 3 0 8 0 1 1 1 3 4 0 0 0 1 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a 15 JMP Rn 0 7 1 0 0 1 a a a a a 8 7 1 R R R 0 a a a a a a a 0 1 1 0 0 0 0 1 Instruction Fields Rn RRR Address Register 000 R0 010 R2 100 R4 110 001 R1 011 R3 101 R5 111 Note: This instruction can specify R8-R15 as operands by using a high register prefix.
JMPD JMPD Jump Using a Delay Slot (AGU) JMPD Operation Assembler Syntax label → PC JMPD label {0 ≤ label < 232,W} Rn → PC JMPD Rn Description JMPD label Jumps to an absolute memory destination address specified by a label after executing the execution set in the delay slot. The assembler and the linker calculate the destination address from the label. The destination address cannot be in the middle of an execution set.
JMPD Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3 JMPD label 31 3 0 8 0 1 1 0 0 0 1 JMPD Rn 4 0 0 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a 15 31 7 1 0 0 1 a a 8 7 1 R R R 0 a a a a a a a 0 1 1 0 0 0 0 0 Note 1: The jump uses 3 cycles minus the execution time used by execution set in the delay slot. The cycle count for this instruction cannot be less than 1 cycle.
JSR JSR Jump to Subroutine (AGU) JSR Operation Assembler Syntax (Next PC) → (SP); SR → (SP + 4); SP + 8 → SP; label → PC JSR label {0 ≤ label < 232,W} (Next PC) → (SP); SR → (SP + 4); SP + 8 → SP; Rn → PC JSR Rn Description These operations jump to the subroutine location in program memory that is given by the instruction’s effective address. The operation includes an implicit push of the status register (SR) and the program counter (PC) onto the stack.
JSR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3/41 3 JSR label 3 8 1 0 1 0 0 1 A A A A A A A A A A A A A 1 0 a a 0 a 1 a 15 3/41 1 JSR Rn 4 0 0 a 0 7 1 0 0 1 1 A A A a a a 8 7 a a a a a 1 a 0 a 0 a 0 1 R R R 0 1 1 0 0 0 1 1 Note 1: The cycle time is 4 if the largest execution time of the other instructions grouped with JSR is ≥ 3. Instruction Fields label Note: Rn Label must be word-aligned, LSBit = 0.
JSRD JSRD Jump to a Subroutine Using a Delay Slot (AGU) JSRD Operation Assembler Syntax (Next* PC) → (SP); SR → (SP + 4); SP + 8 → SP; (Next* PC) →RAS; label → PC JSRD label {0 ≤ label < 232,W} (Next* PC) → (SP); SR → (SP + 4); SP + 8 → SP; (Next* PC) → RAS; Rn → PC JSRD Rn Description Executes the execution set in the delay slot, then pushes the next* PC (the PC of the execution set after the delay slot) and SR onto the stack, and causes program execution to continue at the address defined by lab
JSRD Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3 JSRD label 1 2/3 3 8 1 0 1 0 0 1 A A A A A A A A A A A A A 1 0 a a 0 a 15 1 JSRD Rn 1 2/3 4 1 0 0 1 1 0 0 a 0 7 a 0 A A A a a a 8 7 1 R R R 0 a a a a a 1 a 0 0 a a 0 1 1 0 0 0 1 0 Note 1: The jump uses three cycles if the largest cycle time of the instructions grouped with JSRD is 3 or greater.
JT JT JT Jump If True (AGU) Operation Assembler Syntax If T=1, then label → PC JT label {0 ≤ label < 232,W} If T=1, then Rn → PC JT Rn Description If the T bit is set, these operations continue program execution at a specified 32-bit memory destination address. If the T bit is cleared, the PC is updated to point to the next execution set. Program execution continues sequentially. The destination address cannot be in the middle of an execution set.
JT Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3 JT label 1 1/4 3 8 1 0 1 0 0 1 A A A A A A A A A A A A A 1 0 a a 1 a 0 a 15 1 JT Rn 1/41 4 0 0 a 0 7 1 0 0 1 1 A A A a a a 8 7 1 R R R 0 a a a a a 1 a 0 a 0 a 0 1 1 0 0 1 0 1 Note 1: If not taken, the jump uses 1 cycle. If taken, the jump uses 4 cycles. Instruction Fields label Note: Rn Label must be word-aligned, LSBit = 0.
JTD JTD Jump If True Using Delay Slot (AGU) JTD Operation Assembler Syntax If T=1, then label → PC JTD label {0 ≤ label < 232,W} If T=1, then Rn → PC JTD Rn Description If the T bit is set, this instruction continues program execution at a specified 32-bit memory destination address after executing the execution set in the delay slot. If the T bit is cleared, the PC is updated to point to the next execution set. Program execution continues sequentially.
JTD Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 3 JTD label 1 1/4 3 8 1 0 1 0 0 1 A A A A A A A A A A A A A 1 0 a a 1 a 0 a 15 1 JTD Rn 1/41 4 0 0 a 0 7 1 0 0 1 0 A A A a a a 8 7 1 R R R 0 a a a a a 1 a 0 a 0 a 0 1 1 0 0 1 0 0 Note 1: If the jump is not taken, it uses 1 cycle. If the jump is taken, it uses 4 cycles minus the time used by the execution set in the delay slot.
LPMARKx L-M LPMARKx End-of-Loop Mark (PREFIX) Operation If LCn > 1, LPMARKx Disassembler Syntax Only then SAn → PC LCn – 1 → LCn LPMARKB (long loop) else next PC → PC 0 → LCn 0 → LFn If LCn > 1, then SAn → PC LCn – 1 → LCn LPMARKA (external of nested loops) else next PC → PC 0 → LCn 0 → LFn If LCn > 1, then SAn → PC LCn – 1 → LCn LPMARKB (short loop of 2 sets) else next PC → PC 0 → LCn 0 → LFn 0 → SLF If LCn > 1, then SAn → PC LCn – 1 → LCn LPMARKA (short loop of 1 set) else next PC → PC 0 →
LPMARKx LPMARKB For long loops (SLF=0), this prefix bit is placed at LA-2 (two sets before the last set of the loop). It instructs the active loop to decrement LCn and issue a jump delayed operation (with 2 delay slots) to SAn, if LCn is greater than one. If LCn is less than or equal to one, then the LCn register and the LFn bit are cleared. For short loops (SLF=1) of two execution sets, this prefix bit is placed at the first set of the loop (SA).
LPMARKx Status and Conditions Changed by LPMARK Execution The loop flag (LFn) and short loop flag (SLFn) are cleared as described in the operation field. Example Insertion of lpmarkb by assembler. Instruction Disassembled Instruction Comments dosetup0 _lab dosetup0 *+e Sets up loop 0 with a start address at _lab. doen0 d6 doen0 d6 Initializes a long loop with the iteration count from d6. move.w #1,d1 move.w #<$1,d1 Puts the number one into d1. move.w #2,d2 move.
LSLL LSLL LSLL Multiple-Bit Bitwise Shift Left (DALU) Operation Assembler Syntax If Da[6:0] > 0, then Dn << Da[6:0] → Dn else Dn >>> ⏐Da[6:0]⏐ → Dn LSLL Da,Dn {–40 ≤ Da[6:0] ≤ 40} Description LSLL Da,Dn Logically shifts a 40-bit data register (Dn) left or right N bits. N is a signed 6-bit integer contained in Da[6:0]. If N is positive, Dn is shifted left. Bit (40 – N) is stored in the C bit. Bits [(39 – N):0] are copied to bits [39:N]. Bits [(N – 1):0] are cleared.
LSLL 3 9 3 2 1 6 0 1111111110000111011001010100001100100001 C 1 1111111000011101100101010000110010000100 Example 2 lsll d4,d2 Register/Memory Address Before After D4 $FF FFFF FFFE SR $00E4 0000 $00E4 0000 $0:$FF 8765 4321 $0:$3F E1D9 50C8 L2:D2 3 9 3 2 1 6 0 1111111110000111011001010100001100100001 0011111111100001110110010101000011001000 C 0 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 LSLL Da,Dn Note: 1 2 1 8 1 0 1 0 1 7 0 F F F 0 0
LSR LSR LSR Bitwise Shift Right One Bit (DALU) Operation Assembler Syntax (Dn>>>1) → Dn; 0 → Dn[39] LSR Dn Description LSR Dn Shifts the contents of a data register (Dn) right one bit. The LSB (bit 0) is shifted into the carry (C) bit in the status register. Bits [39:1] are copied to bits [38:0]. Bit 39 is cleared. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[0] C Dn[0] is stored in the C bit.
LSRA LSRA LSRA Bitwise Shift Right By One Bit (AGU) Operation Assembler Syntax (Rx>>>1) → Rx; 0 → Rx[31] LSRA Rx Description LSRA Rx Shifts the contents of an AGU register (Rx) right one bit. Bits [31:1] are copied to bits [30:0]. Bit 31 is cleared. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR.
LSRR LSRR Multiple-Bit Bitwise Shift Right (DALU) LSRR Operation Assembler Syntax If Da[6:0] > 0, then Dn>>>Da→ Dn else Dn << ⏐Da⏐→ Dn LSRR Da,Dn {–40 ≤ Da[6:0] ≤ 40} Dn >>> #u5 → Dn LSRR #u5,Dn {0 ≤ u5 < 32} |Description LSRR Da,Dn Logically shifts the contents of a 40-bit data register (Dn) left or right N bits. N is a signed 6-bit integer contained in Da bits [6:0]. If N is positive, Dn is shifted right. Bit (N – 1) is stored in the C bit. Bits [39:N] are copied to bits [(39 – N):0].
LSRR Status and Conditions Changed by Instruction Register Address Bit Name Description SR[0] C Bit (N – 1) of Dn is stored in the C bit for a right shift. Or, bit (40 – |N|) of Dn is stored in the C bit for a left shift. Ln L Clears the Ln bit in the destination register.
LSRR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 LSRR Da,Dn 1 1 2 LSRR #u5,Dn 1 1 2 1 8 1 0 1 0 1 F F F 1 0 1 1 1 F F F 15 1 7 8 0 0 0 0 1 J J 0 1 i i i i 7 J 0 i Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn FFF 000 001 Note: #u5 A-230 This instruction can specify D8-D15 as operands by using a prefix.
LSRW LSRW Word Bitwise Shift Right (DALU) Operation Assembler Syntax Da>>>16 → Dn LSRW Da,Dn LSRW Description LSRW Da,Dn Copies a source data register (Da) to the destination data register (Dn), logically shifted right 16 bits. Bit 15 of the source register is copied to the C bit. Bits [39:16] of the source register are copied to bits [23:0] of the destination register. Bits [39:24] of the destination register are cleared.
LSRW 3 9 3 2 1 6 0 1111111110000111011001010100001100100001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 C 0 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 LSRW Da,Dn 1 2 1 8 1 0 1 1 0 7 F F F 0 0 0 0 1 J J J Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4
MAC MAC Signed Fractional Multiply-Accumulate (DALU) MAC Operation Assembler Syntax Dn + (#s16 * Da.H) → Dn MAC #s16,Da,Dn {–215 ≤ s16 < 215} Dn ± (Da.H * Db.H) → Dn MAC ±Da,Db,Dn Description These operations perform signed fractional multiplication of two 16-bit signed operands (Da.H and Db.H). They then add or subtract the product to or from a data register (Dn). One operand is the HP of a data register. The other operand is either the HP of a data register or an immediate 16-bit signed data.
MAC Register/Memory Address Before D5 After $00 3000 0000 L6:D6 $0:$00 4000 0000 $0:$00 4600 0000 EMR $0000 0000 0.001 $1000 x 0.011$3000 0.0000110$0600 +0.1000000$4000 0.
MAC Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Da,Db This instruction can specify D8-D15 as operands by using a prefix.
MACR MACR Signed Fractional Multiply-Accumulate and Round (DALU) Operation Assembler Syntax Rnd(Dn ± (Da.H * Db.H)) → Dn MACR ±Da,Db,Dn MACR Description MACR ±Da,Db,Dn This instruction performs signed fractional multiplication of two 16-bit signed operands (Da.H and Db.H). It then adds or subtracts the product to or from a destination data register (Dn) and rounds the final result.
MACR Register/Memory Address Before After EMR $0000 0000 0.000 0000 1000$0080 x 0.000 0000 1000$0080 0.000 0000 0000 0000 1000$000080000 +0.000 0000 0000 0111 0000$0007 rnd0.000 0000 0000 0111 1000$00078 0.
MACR Da,Da jj Data Register Pairs 00 Note: Dn FFF 000 001 Note: A-238 D1,D1 01 D3,D3 10 D5,D5 11 D7,D7 This instruction can specify D8-D15 as operands by using a prefix. Single Source/Destination Data Register D0 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
MACSU MACSU Fractional Multiply-Accumulate Signed By Unsigned (DALU) MACSU Operation Assembler Syntax Dn + (Dc.H * Dd.L) → Dn MACSU Dc,Dd,Dn Description MACSU Dc,Dd,Dn Performs signed fractional multiplication of the signed 16-bit HP of one data register (Dc) in a register pair (Dc and Dd) by the unsigned 16-bit LP of the other data register (Dd). It then adds the sign-extended 32-bit product to a destination data register (Dn). Status and Conditions that Affect Instruction None.
MACSU 1.100 $C000 x 0.000 0000 0000 0001$0001 (2–15) 1.111 1111 1111 1111 1000 $FFFF 8000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MACSU Dc,Dd,Dn Note: 1 1 1 0 8 * 1 0 0 0 7 F F F 0 1 1 1 0 0 e e ** indicates serial grouping encoding. Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix.
MACUS MACUS Fractional Multiply-Accumulate Unsigned By Signed (DALU) MACUS Operation Assembler Syntax Dn + (Dc.L * Dd.H) → Dn MACUS Dc,Dd,Dn Description MACUS Dc,Dd,Dn Performs signed fractional multiplication of the unsigned 16-bit LP of one data register (Dc) in a register pair by the signed 16-bit HP of the other data register (Dd). It then adds the sign-extended 32-bit product to a data register (Dn). Status and Conditions that Affect Instruction None.
MACUS Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MACUS Dc,Dd,Dn Note: 1 1 1 0 8 * 1 0 1 1 7 F F F 0 1 1 0 0 0 e e ** indicates serial grouping encoding. Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix.
MACUU MACUU Fractional Multiply-Accumulate Unsigned By Unsigned (DALU) MACUU Operation Assembler Syntax Dn + (Dc.L * Dd.L) → Dn MACUU Dc,Dd,Dn Description MACUU Dc,Dd,Dn Performs unsigned fractional multiplication of the unsigned 16-bit LP of one data register (Dc) by the unsigned 16-bit LP of the other data register (Dd). It then adds the zero-extended 32-bit product to a data register (Dn). Status and Conditions that Affect Instruction None.
MACUU Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MACUU Dc,Dd,Dn Note: 1 1 1 0 8 * 1 0 1 1 7 F F F 0 1 1 0 0 1 e e ** indicates serial grouping encoding. Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix.
MARK MARK MARK Push the PC into the Trace Buffer (AGU) Operation Assembler Syntax PC → trace buffer MARK Description MARK Writes PC (the address of the MARK instruction) to the trace buffer if the trace buffer is enabled (TMARK bit in the TB_CTRL register is set). It is an EOnCE dedicated instruction used for debugging. This instruction can appear only once in an execution set. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction None.
MAX MAX MAX Transfer Maximum Signed Value (DALU) Operation Assembler Syntax If Dg > Dh, then Dg → Dh MAX Dg,Dh Description MAX Dg,Dh Writes the larger of two signed values in a data register pair (Dg and Dh) to the second of the two registers (Dh). If the first register is greater than the second, the value of the first register is written to the second. Otherwise, the second register is unchanged. Only certain pairs of registers are allowed; see Instruction Fields below.
MAX2 MAX2 MAX2 Transfer Two 16-Bit Maximum Signed Values (DALU) Operation Assembler Syntax If Dg.H > Dh.H, then Dg.H → Dh.H MAX2 Dg,Dh If Dg.L > Dh.L, then Dg.L → Dh.L Description MAX2 Dg,Dh Writes the larger of each of the corresponding portions in a data register pair (Dg and Dh) to the second of the two registers (Dh). The high and low portions of the two registers are compared independently as 16-bit signed values and written (or not written) based on the comparison.
MAX2 Instruction Fields Dg,Dh GG Data Register Pairs 00 Note: A-248 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 This instruction can specify D8-D15 as operands by using a prefix.
MAX2VIT MAX2VIT MAX2 for Viterbi Kernel (DALU) MAX2VIT Operation Assembler Syntax If Da.L > Db.L, then 0 → VFn, Da.L → Db.L else 1 → VFn MAX2VIT Da,Db Da Db VFn D4.L D2.L VF0 D4.H D2.H VF1 D0.L D6.L VF2 D0.H D6.H VF3 D12.L D10.L VF0 D12.H D10.H VF1 D8.L D14.L VF2 D8.H D14.H VF3 Description These operations independently compare the 16-bit contents of the HP and LP of a data register pair to find the larger value.
MAX2VIT Status and Conditions Changed by Instruction Register Address Bit Name Description SR[8] VF0 Updated by MAX2VIT D4,D2 and MAX2VIT D12,D10. SR[9] VF1 Updated by MAX2VIT D4,D2 and MAX2VIT D12,D10. SR[10] VF2 Updated by MAX2VIT D0,D6 and MAX2VIT D8,D14. SR[11] VF3 Updated by MAX2VIT D0,D6 and MAX2VIT D8,D14. Ln L Clears the Ln bit in the destination register.
MAXM MAXM MAXM Transfer Maximum Absolute Value (DALU) Operation Assembler Syntax If⏐Dg⏐ > ⏐Dh⏐, then Dg → Dh MAXM Dg,Dh If Dg == –Dh, then ⏐Dg⏐→ Dh Description MAXM Dg,Dh Compares the absolute values of a data register pair (Dg and Dh). If the absolute value of the first register (Dg) is greater than the absolute value of the second (Dh), the value of the first register is written to the second (Dh). Otherwise, the second register is unchanged.
MAXM Instruction Fields Dg,Dh GG Data Register Pairs 00 Note: A-252 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 This instruction can specify D8-D15 as operands by using a prefix.
MIN MIN MIN Transfer Minimum Signed Value (DALU) Operation Assembler Syntax If Dg < Dh, then Dg → Dh MIN Dg,Dh Description MIN Dg,Dh Writes the smaller of two signed values in a data register pair (Dg and Dh) to the second of the two registers (Dh). If the first register is less than the second, the value of the first register is written to the second. Otherwise, the second register is unchanged. Status and Conditions that Affect Instruction None.
MIN2 MOVE.2F Move Two Fractional Words from Memory to a Register Pair (AGU) MOVE.2F Operation Assembler Syntax (EA) → Da:Db MOVE.2F (EA),Da:Db {0 ≤ EA < 232,L} Description MOVE.2F (EA),Da:Db Moves two signed fractional words from memory to a data register pair (Da:Db). The effective memory address of the two words is contained in an address register with an optional offset or post-increment (EA).
MOVE.2F Register/Memory Address Before After $0050 $6000 $0052 $2000 L2:D2 $0:$00 6000 0000 L3:D3 $0:$00 2000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVE.2F (EA),Da:Db Notes: 1. 2. 12 1 0 * 0 1 1 h h 8 7 0 1 0 1 M M M R R R ** indicates serial grouping encoding. When the form (Rn + N0) is used in EA, the cycle count is increased by 1.
MOVE.2L MOVE.2L Move Two Integer Longs to/from a Register Pair (AGU) MOVE.2L Operation Assembler Syntax Da,Db ↔ (EA) MOVE.2L Da:Db,(EA){0 ≤ EA < 232,Q} MOVE.2L (EA),Da:Db {0 ≤ EA < 232,Q} Description These operations move two long words from registers to memory, or from memory to registers. MOVE.2L Da:Db,(EA) MOVE.2L (EA),Da:Db Move two long signed integer words from a data register pair (Da:Db) to memory, or from memory to a data register pair.
MOVE.2L Register/Memory Address Before After R0 $0000 0050 L0:D0 $0:$00 12345 678 L1:D1 $0:$00 5432 9876 $0050 $1234 5678 $0054 $5432 9876 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVE.2L Da:Db,(EA) 11 2 1 8 1 0 0 0 h 7 0 h w 0 0 M M M R R R MOVE.2L (EA),Da:Db Note 1: When the form (Rn + N0) is used in EA, the cycle count is increased by 1.
MOVE.2W MOVE.2W Move Two Integer Words to/from a Register Pair (AGU) MOVE.2W Operation Assembler Syntax (EA) ↔ Da:Db MOVE.2W (EA),Da:Db {0 ≤ EA < 232,L} MOVE.2W Da:Db,(EA) {0 ≤ EA < 232,L} Description MOVE.2W (EA),Da:Db MOVE.2W Da:Db,(EA) Moves two signed integer words from memory to a data register pair (Da:Db), or from the registers to memory. The effective memory address of the two words is obtained from an address register with an optional offset or post-increment (EA).
MOVE.2W Register/Memory Address Before After D0 $FF FFFF AF44 D1 $00 0000 2377 R0 $0000 0050 $0050 $AF44 $0052 $2377 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVE.2W (EA),Da:Db 12 1 0 * 0 w 1 h h 8 7 0 0 0 1 M M M R R R MOVE.2W Da:Db,(EA) Notes: 1. 2. ** indicates serial grouping encoding. When the form (Rn + N0) is used in EA, the cycle count is increased by 1.
MOVE.4F MOVE.4F Move Four Fractional Words from Memory to a Register Quad (AGU) MOVE.4F Operation Assembler Syntax (EA) → Da:Db:Dc:Dd MOVE.4F (EA),Da:Db:Dc:Dd {0 ≤ EA < 232,Q} Description MOVE.4F (EA),Da:Db:Dc:Dd Reads four signed fractional words from memory to a data register quad (Da:Db:Dc:Dd). The effective memory address of the four words is contained in an address register with an optional offset or post-increment (EA).
MOVE.4F move.4f (r0),d0:d1:d2:d3 Register/Memory Address Before After MCTL $0000 0000 R0 $0000 0100 $0100 $943C $0102 $5AB1 $0104 $33E4 $0106 $A7AC L0:D0 $0:$FF 943C 0000 L1:D1 $0:$00 5AB1 0000 L2:D2 $0:$00 33E4 0000 L3:D3 $0:$FF A7AC 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVE.4F(EA),Da:Db:Dc:Dd Notes: 1. 2. 1 12 1 0 * 0 0 1 k 0 8 7 0 1 1 1 M M M R R R ** indicates serial grouping encoding.
MOVE.4W MOVE.4W Move Four Integer Words to/from a Register Quad (AGU) MOVE.4W Operation Assembler Syntax (EA) ↔ Da:Db:Dc:Dd MOVE.4W (EA),Da:Db:Dc:Dd {0 ≤ EA < 232,Q} MOVE.4W Da:Db:Dc:Dd,(EA){0 ≤ EA < 232,Q} Description MOVE.4W (EA),Da:Db:Dc:Dd MOVE.4W Da:Db:Dc:Dd,(EA) Moves four signed integer words from memory to a data register quad (Da:Db:Dc:Dd), or from the register quad to memory.
MOVE.4W move.4w d0:d1:d2:d3,(r0) Register/Memory Address Before After MCTL $0000 0000 R0 $0000 0050 L0:D0 $0:$00 0000 1FEC L1:D1 $0:$00 0000 2354 L2:D2 $0:$00 0000 38C0 L3:D3 $0:$00 0000 4151 $0050 $1FEC $0052 $2354 $0054 $38C0 $0056 $4151 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVE.4W (EA),Da:Db:Dc:Dd 11 1 2 1 8 1 0 0 1 k 7 0 0 w 0 0 M M M R R R MOVE.
MOVE.B MOVE.B MOVE.B Byte Move (AGU) Operation Assembler Syntax (aa) ↔ DR MOVE.B (a16),DR {0 ≤ a16 < 216} MOVE.B DR,(a16) {0 ≤ a16 < 216} DR → (aa) MOVE.B DR,(a32) {0 ≤ a32 < 232} DR→(Rn+s15) MOVE.B DR,(Rn+s15) {–214 ≤ s15 < 214} (ea) ↔ DR MOVE.B (ea),DR MOVE.B DR,(ea) (SP+s15) ↔ DR MOVE.B (SP+s15),DR {–214 ≤ s15 < 214} MOVE.B DR,(SP+s15) {–214 ≤ s15 < 214} Description These operations move 8-bit data from memory to a data or address register, or from a register to memory.
MOVE.B MOVE.B DR,(ea) Writes a byte to memory. The effective memory address is obtained from an address register with an optional offset or post-increment. MOVE.B (SP+s15),DR Reads a byte from memory, sign-extending it into a register. The effective memory address is obtained from the active stack pointer (SP) with a signed 15-bit offset. MOVE.B DR,(SP+s15) Writes a byte to memory. The address is obtained from the stack pointer with a signed 15-bit offset.
MOVE.B Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 MOVE.B (a16),DR 1 3 8 2 1 3 0 0 1 H H H H A A A 0 1 0 0 A A A A A A A A A A A A A 8 3 1 3 2 2 1 MOVE.B DR,(ea) 1 11 4 MOVE.B (SP+s15),DR 2 2 3 MOVE.
MOVE.B Rn RRR 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note: ea This instruction can specify R8-R15 as operands by using a high register prefix.
MOVE.F MOVE.F MOVE.F Move Fractional Word to/from Memory (AGU) Operation Assembler Syntax #s16 → Db MOVE.F #s16,Db {–215 ≤ s16 < 215} (aa) → Db MOVE.F (a16),Db {0 ≤ a16 < 216,W} (aa) → Db MOVE.F (a32),Db {0 ≤ a32 < 232,W} (EA) → Db MOVE.F (EA),Db {0 ≤ EA < 232,W} (Rn+s15) → Db MOVE.F (Rn+s15),Db {–214 ≤ s15 < 214,W} (SP+s15) → Db MOVE.F (SP+s15),Db {–214 ≤ s15 < 214,W} Db → (ea) MOVE.
MOVE.F MOVE.F (SP+s15),Db Reads a fractional word from memory. The effective memory address is obtained from the active stack pointer (SP) with a signed 15-bit offset. MOVE.F Db,(ea) Writes an unsaturated fractional word to memory without being affected by the scaling mode. This is the only instruction available for moving the HP of a data register to memory without saturation. The effective memory address is obtained from an address register with an optional offset or post-increment.
MOVE.F Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 MOVE.F #s16,Db 1 4 2 1 3 3 1 3 1 0 0 j j j i i i 0 0 0 0 1 1 0 0 i i i i i i i i i i i i i 8 7 j A A A 0 0 0 j j 1 MOVE.F (EA),Db 1 0 0 1 0 0 A A A A A A A A A A A A A 0 0 0 0 1 j j 2 2 3 2 2 3 MOVE.F Db,(ea) Notes: 1. 2.
MOVE.F ea MM Effective Address Notation 00 Rn (Rn)+ RRR (Rn)– 10 (Rn+N0) 11 (Rn) Address Register 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note: This instruction can specify R8-R15 as operands by using a high register prefix.
MOVE.L MOVE.L MOVE.L Move Long Word (AGU) Operation Assembler Syntax #s32 → C4 MOVE.L #s32,C4 {–231 ≤ s32 < 231} #u32 → C1 MOVE.L #u32,C1 {0 ≤ u32 < 232} C4 ↔ Db MOVE.L C4,Db MOVE.L Db,C4 C2 ↔ Db MOVE.L C2,Db MOVE.L Db,C2 Description These operations move an immediate long word (32-bit data) into a register, or move a long word between registers. MOVE.L instructions that write to a data register clear the destination register’s limit tag bit (Ln bit). 39 32 SIGN Db EXTENSION 0 MOVE.
MOVE.L 0 0 1 i i i i i i i i i i i i i 1 0 I I I I I I I I I I I I I I 8 7 0 0 1 1 0 C C C i i i I I 0 1 1 0 0 1 i i i i i i i i i i i i i 1 0 I I I I I I I I I I I I I I 8 7 1 0 0 D D D D 0 1 0 D w j j 15 MOVE.L #u32,C1 3 1 3 15 1 MOVE.L C4,Db 1 2 1 0 0 j MOVE.L Db,C4 15 1 MOVE.L C2,Db 1 2 1 8 1 0 7 0 C C C C 0 0 1 1 0 w j j j MOVE.
MOVE.
MOVE.L MOVE.L Move Long Register Extensions (AGU) MOVE.L Operation Assembler Syntax ((SP+s15)[8:0]) → De.E MOVE.L (SP+s15),De.E {–214 ≤ s15 < 214,L} Da.E:Db.E → (SP+s15) MOVE.L Da.E:Db.E,(SP+s15) {–214 ≤ s15 < 214,L} ((SP+s15)[24:16]) → Do.E MOVE.L (SP+s15),Do.E {–214 ≤ s15 < 214,L} (aa[8:0]) → De.E MOVE.L (a32),De.E {0 ≤ a32 < 232,L} Da.E:Db.E → (aa) MOVE.L Da.E:Db.E,(a32) {0 ≤ a32 < 232,L} (aa[24:16]) → Do.E MOVE.L (a32),Do.
MOVE.L Stores the L and extension bits from one even and one odd data register into a 32-bit memory address that is pointed to by the active stack pointer (SP) and a signed 15-bit offset. MOVE.L (SP+s15),Do.E Reads from a memory address pointed to by the active stack pointer (SP) and a signed 15-bit offset into the extension and Ln bit of an odd numbered data register. MOVE.L (a32),De.E Reads from a 32-bit absolute memory address into the extension and Ln bit of an even numbered data register. MOVE.L Da.
MOVE.L Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVE.L (SP+s15),De.E 2 2 3 MOVE.L Da.E:Db.E,(SP+s15) 2 2 3 MOVE.L (SP+s15),Do.E 2 2 3 MOVE.L (a32),De.E 3 1 3 MOVE.L Da.E:Db.E,(a32) 3 1 3 MOVE.L (a32),Do.
MOVE.
MOVE.L MOVE.L Move Long (AGU) MOVE.L Operation Assembler Syntax (aa) ↔ DR MOVE.L (a32),DR {0 ≤ a32 < 232,L} MOVE.L DR,(a32) (aa) ↔ C4 MOVE.L (a16),C4 {0 ≤ a16 < 216,L} MOVE.L C4,(a16) (Rn + u3) ↔ DR MOVE.L (Rn+u3),DR {0 ≤ u3 < 32,L} MOVE.L DR,(Rn+u3) (Rn + s15) ↔ DR MOVE.L (Rn+s15),DR {–214 ≤ s15 < 214,L} MOVE.L DR,(Rn+s15) (Rn + Rr) ↔ DR MOVE.L (Rn+Rr),DR MOVE.L DR,(Rn+Rr) (EA) ↔ DR MOVE.L (EA),DR MOVE.L DR,(EA) (Rn) ↔ C3 MOVE.L (Rn),C3 MOVE.L C3,(Rn) (SP – u6) ↔ DR MOVE.
MOVE.L MOVE.L (a32),DR MOVE.L DR,(a32) Moves a 32-bit long word between a data or address register and a memory address pointed to by a 32-bit absolute address. MOVE.L (a16),C4 MOVE.L C4,(a16) Moves a 32-bit long word between a general register and a memory address pointed to by a 16-bit unsigned absolute address. MOVE.L (Rn+u3),DR MOVE.
MOVE.L MOVE.L (SP+s15),C4 MOVE.L C4,(SP+s15) Moves a 32-bit long word between a general register and a memory address pointed to by the active stack pointer plus a 15-bit signed offset. Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3-AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand.
MOVE.L MOVE.L DR,(Rn+u3) 15 MOVE.L (Rn+s15),DR 2 2 3 MOVE.L DR,(Rn+s15) 8 1 2 4 0 0 0 0 w H H H H 1 s s 0 0 R R R 1 0 0 s s s s s s s s 15 MOVE.L (Rn+Rr),DR 7 1 0 1 s s 8 7 s s s 0 0 H H H H w 1 R R R r r r MOVE.L DR,(Rn+Rr) 15 MOVE.L (EA),DR 1 1 1 1 0 8 * Note: MOVE.L DR,(EA) 7 0 0 w H H H H 1 0 M M M R R R ** indicates serial grouping encoding. 15 MOVE.L (Rn),C3 1 1 4 1 8 0 0 7 1 D D D D 0 0 0 0 1 w R R R MOVE.
MOVE.
MOVE.
MOVE.W MOVE.W Move Immediate Integer Word (AGU) MOVE.W Operation Assembler Syntax #s7 → DR MOVE.W #s7,DR {–64 ≤ s7 < 64} #s16 → C4 MOVE.W #s16,C4 {–215 ≤ s16 < 215} #s16 → (aa) MOVE.W #s16,(a16) {–215 ≤ s16 < 215}{0 ≤ a16 < 216,W} #s16 → (SP–u5) MOVE.W #s16,(SP–u5) {–215 ≤ s16 < 215}{0 ≤ u5 < 64,W] #s16 → (Rn) MOVE.W #s16,(Rn) {–215 ≤ s16 < 215} #s16 → (SP+sa16) MOVE.
MOVE.W Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register. Example move.
MOVE.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVE.W #s7,DR 1 1 2 MOVE.W #s16,C4 2 1 4 1 8 0 0 H H H H 1 8 7 0 0 1 0 D D D D 1 0 0 i i i i 0 0 1 1 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 i 15 3 1 3 i i i i 15 MOVE.
MOVE.W DR HHHH 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note: Rn #s16 This instruction can specify D8-D15 or R8-R15 as operands by using a high register prefix. RRR Address Register 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note: #s7 Data/Address Register This instruction can specify R8-R15 as operands by using a high register prefix.
MOVE.W MOVE.W Move Integer Word (AGU) MOVE.W Operation Assembler Syntax (aa) ↔ DR MOVE.W (a32),DR {0 ≤ a32 < 232,W} MOVE.W DR,(a32) (aa) ↔ C4 MOVE.W (a16),C4 {0 ≤ a16 < 216,W} MOVE.W C4,(a16) (Rn+u3) ↔ DR MOVE.W (Rn+u3),DR {0 ≤ u3 < 16,W} MOVE.W DR,(Rn+u3) (Rn+s15) ↔ DR MOVE.W (Rn+s15),DR {–214 ≤ s15 < 214,W} MOVE.W DR,(Rn+s15) (Rn+Rr) ↔ DR MOVE.W (Rn+Rr),DR MOVE.W DR,(Rn+Rr) (EA) ↔ DR MOVE.W (EA),DR MOVE.W DR,(EA) (Rn) ↔ C3 MOVE.W (Rn),C3 MOVE.W C3,(Rn) (SP-u6) ↔ DR MOVE.
MOVE.W MOVE.W (Rn+u3),DR MOVE.W DR,(Rn+u3) Moves a signed word between a data or address register (DR) and a memory address pointed to by an address register (Rn) with an unsigned 3-bit offset that is preshifted right by 1 bit. The offset u3, defined by the programmer, must be an even integer from 0–14. It is encoded by the assembler with 3 bits, thus creating a 3-bit offset, which is coded in the instruction.
MOVE.W Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers. Example move.
MOVE.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVE.W (a32),DR 3 1 3 MOVE.W DR,(a32) 0 8 0 0 2 1 3 MOVE.W C4,(a16) 1 2 4 a w 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a 8 7 a a a a a a a 0 0 0 0 w D D D D A A A 0 1 0 0 A A A A A A A A A A A A A 15 MOVE.W (Rn+u3),DR 0 0 H H H H A A A a 15 MOVE.W (a16),C4 7 1 8 0 1 1 0 D 0 7 0 1 H H H H w 0 R R R s s s MOVE.W DR,(Rn+u3) 15 MOVE.
MOVE.
MOVE.
MOVEc MOVEc Conditional Address Register Move (AGU) Operation Assembler Syntax If T=1, then Rq → Rn MOVET Rq,Rn If T=0, then Rq → Rn MOVEF Rq,Rn MOVEc Description This instruction conditionally copies the value of one address register to another, depending on the value of the T bit in SR. These operations have the same timing as other move instructions. MOVEc is performed in the execution stage of the pipeline, unlike TFRA, which is performed in the address generation stage.
MOVEc Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVET Rq,Rn 1 4 1 8 0 0 1 1 R R R 0 15 1 MOVEF Rq,Rn 1 4 1 8 0 0 1 7 0 1 0 1 0 q q 7 1 R R R 0 q 0 1 0 1 1 q q q Instruction Fields Rq qqq 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note: Rn This instruction can specify R8-R15 as operands by using a high register prefix.
MOVES.2F MOVES.2F Move Two Fractional Words to Memory With Scaling and Saturation (AGU) MOVES.2F Operation Assembler Syntax Da:Db → (EA) MOVES.2F Da:Db,(EA) Description The data that is moved from each register to memory is scaled according to the scaling mode. If the Ln bit is set, the moved data is also saturated. The address register values must be long aligned. This instruction is affected by by SM (Saturation Mode bit - SR[2]).
MOVES.2F Register/Memory Address Before After SR $00E0 0000 d0 $1:$00 8000 0000 d1 $0:$00 7EAC F00D R0 $0000 0054 $00E0 0000 $0054 $7FFF $0056 $7EAC The Ln bit is set in d0, and the number in d0 is positive (bit 39 = 0), so the saturated value $7FFF is written to memory. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVES.2F Da:Db,(EA) Notes: 1. 2. 12 1 0 * 0 0 1 h h 8 7 0 1 0 1 M M M R R R ** indicates serial grouping encoding.
MOVES.4F MOVES.4F MOVES.4F Move Four Fractional Words to Memory With Scaling and Saturation (AGU) Operation Assembler Syntax Da:Db:Dc:Dd → (EA) MOVES.4F Da:Db:Dc:Dd,(EA) Description The data that is moved from each register to memory is scaled according to the scaling mode. If the Ln bit is set, it is also saturated. The address register values must be quad word-aligned (a multiple of 8). This instruction is affected by by SM (Saturation Mode bit - SR[2]).
MOVES.4F Register/Memory Address Before After R0 $0000 0050 L0:D0 $1:$0 08000 0000 L1:D1 $0:$00 7FFF FFFF L2:D2 $1:$87 6543 2100 L3:D3 $0:$FF 8765 4321 $0050 $7FFF $0052 $7FFF $0054 $8000 $0056 $8765 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 MOVES.4F 12 1 0 * 0 0 1 k 0 8 7 0 0 1 1 M M M R R R Da:Db:Dc:Dd,(EA) Notes: 1. 2. ** indicates serial grouping encoding. When the form (Rn + N0) is used in EA, the cycle count is increased by 1.
MOVES.F MOVES.F MOVES.F Move Fractional Word to Memory With Scaling and Saturation (AGU) Operation Assembler Syntax Db → (aa) MOVES.F Db,(a16) {0 ≤ a16 < 216,W} Db → (aa) MOVES.F Db,(a32) {0 ≤ a32 < 232,W} Db → (Rn + s15) MOVES.F Db,(Rn+s15) {–214 ≤ s15 < 214,W} Db → (EA) MOVES.F Db,(EA) Db → (SP + s15) MOVES.F Db,(SP+s15) {–214 ≤ s15 < 214,W} Description This operation moves a fractional word from a data register to memory.
MOVES.4F Status and Conditions that Affect Instruction Register Address Bit Name MCTL[31:0] AM3–AM0 Address modification bits for R0–R7. SR[5:4] S[1:0] Scaling mode bits choose: no scaling, scale up one bit, or scale down one bit. Ln L Limited values are written to the destination if the Ln bit is set. SR[18] EXP Determines the stack pointer used in instructions that have a stack pointer as an operand.
MOVES.4F Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 MOVES.F Db,(a16) 1 3 0 0 j j 3 1 3 2 2 1 MOVES.F Db,(EA) Notes: 1. 2.
MOVES.
MOVES.L MOVES.L MOVES.L Move Long to Memory With Scaling and Saturation (AGU) Operation Assembler Syntax Db → (EA) MOVES.L Db,(EA) Description The data is scaled according to the scaling mode, and saturated if the Ln bit is set. The address register values must be long word-aligned. This instruction is affected by by SM (Saturation Mode bit - SR[2]). When SM is set, scaling is not performed, and the scale bits S[1:10] have no effect MOVES.
MOVES.L Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVES.L Db,(EA) Notes: 1. 2. 1 1 2 1 0 * 0 0 0 j j 8 7 0 j 1 1 M M M R R R ** indicates serial grouping encoding. When the form (Rn + N0) is used in EA, the cycle count is increased by 1. Instruction Fields Rn RRR 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note: Db A-306 This instruction can specify R8-R15 as operands by using a high register prefix.
MOVEU.B MOVEU.B Move Unsigned Byte from Memory (AGU) MOVEU.B Operation Assembler Syntax (aa) → DR MOVEU.B (a16),DR {0 ≤ a16 < 216} (aa) → DR MOVEU.B (a32),DR {0 ≤ a32 < 232} (Rn + s15) → DR MOVEU.B (Rn+s15),DR {–214 ≤ s15 < 214} (ea) → DR MOVEU.B (ea),DR (SP + s15) → DR MOVEU.B (SP+s15),DR {–214 ≤ s15 < 214} Description These operations move an unsigned byte from memory into a data or address register (DR). Data is placed in bits 7:0 of the destination register (DR) and zero-extended.
MOVEU.B Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers.
MOVEU.B Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 MOVEU.B (a16),DR 1 3 8 3 1 3 0 0 1 H H H H A A A 0 1 0 0 A A A A A A A A A A A A A 0 8 0 0 2 2 3 1 MOVEU.B (ea),DR 4 2 2 0 0 a 1 0 1 0 1 A A A A A A A A A A A A A 0 a a a a a a a 8 7 a a a a a a a 0 0 0 0 1 H H H H 0 s s 1 0 R R R 1 0 0 s s s s s 1 3 0 1 s s s 0 0 s s 8 7 1 H H H H 1 15 MOVEU.
MOVEU.
MOVEU.L MOVEU.L Move Unsigned Immediate Long to a Data Register (AGU) MOVEU.L Operation Assembler Syntax #u32 → Db MOVEU.L #u32,Db {0 ≤ u32 < 232} Description MOVEU.L #u32,Db Loads an unsigned long word (32-bit) immediate value into a data register (Db), zero-extending it. 39 32 ZERO EXTENSION Db 0 Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register.
MOVEU.L Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MOVEU.L #u32,Db 3 1 3 0 1 0 j j 8 7 j i 0 0 1 i i I I 0 0 1 0 0 1 i i i i i i i i i i i i i 1 0 I I I I I I I I I I I I I I Instruction Fields Db jjj Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: #u32 A-312 This instruction can specify D8-D15 as operands by using a prefix.
MOVEU.W MOVEU.W Move Unsigned Immediate Word to a Register Portion (AGU) MOVEU.W Operation Assembler Syntax #u16 → Db[31:16] MOVEU.W #u16,Db.H {0 ≤ u16 < 216} #u16 → Db[15:0] MOVEU.W #u16,Db.L {0 ≤ u16 < 216} Description These operations move an immediate unsigned word to a high/low part of a data register (Db) without changing the other bits in the data register (Db). MOVEU.W #u16,Db.H Loads an immediate unsigned word into the HP of a data register (Db).
MOVEU.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 MOVEU.W #u16,Db.H 1 3 2 1 3 7 0 0 0 0 1 1 0 0 1 i i i 1 0 j j j 1 0 1 i i i i i i i i i i i i i 8 7 15 MOVEU.W #u16,Db.
MOVEU.W MOVEU.W Move Unsigned Word from Memory to a Register (AGU) MOVEU.W Operation Assembler Syntax (aa) → C4 MOVEU.W (a16),C4 {0 ≤ a16 < 216} (aa) → DR MOVEU.W (a32),DR {0 ≤ a32 < 232} (Rn + s15) → DR MOVEU.W (Rn+s15),DR {–214 ≤ s15 < 214} (EA) → DR MOVEU.W (EA),DR (SP + s15) → C4 MOVEU.W (SP+s15),C4 {–214 ≤ s15 < 214} Description These operations move an unsigned word from memory to the LP of a register and zero-extend it. The address of the access must be word-aligned.
MOVEU.W Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the instruction is not affected by MCTL. SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers.
MOVEU.W Instruction Formats and Opcodes Instructions Words Cycles Type Opcode 15 2 MOVEU.W (a16),C4 1 3 8 3 1 3 0 0 1 D D D D A A A 0 1 0 0 A A A A A A A A A A A A A 0 8 0 0 2 2 3 1 MOVEU.W (EA),DR Notes: 1. 2.
MOVEU.W EA Rn MMM 000 (Rn+N0) 010 (Rn) 100 (Rn)+N0 110 (Rn)+N2 001 (Rn)– 011 (Rn)+ 101 (Rn)+N1 111 (Rn)+N3 RRR 000 001 Note: a16 Effective Address Notation Address Register R0 010 R2 100 R4 110 R6 R1 011 R3 101 R5 111 R7 This instruction can specify R8-R15 as operands by using a high register prefix.
MPY MPY Signed Fractional Multiply (DALU) Operation Assembler Syntax Da.H * Db.H → Dn MPY Da,Db,Dn MPY Description MPY Da,Db,Dn Performs signed fractional multiplication of the high portions of two data registers (Da, Db) and stores the product in a destination data register (Dn). Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode.
MPY 0.010 $2000 1/4 x 1.100$C000 –1/2 1.111 $F000 –1/8 Example 2 mpy d6,d6,d7 Register/Memory Address Before After D6 $FF C000 0000 L7:D7 $0:$00 2000 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MPY Da,Da,Dn 1 1 1 MPY Da,Db,Dn 1 1 1 0 8 1 0 1 0 F F F * 1 0 0 0 F F F 15 Note: 0 7 * 8 0 1 1 1 0 0 j 0 1 J J J J 7 j 0 J ** indicates serial grouping encoding.
MPY Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
MPYR MPYR MPYR Signed Fractional Multiply and Round (DALU) Operation Assembler Syntax Rnd((Da.H * Db.H)) → Dn MPYR Da,Db,Dn Description MPYR Da,Db,Dn Performs signed fractional multiplication of the high portions of a data register pair (Da, Db), rounds the product, and stores the result in a destination data register (Dn). Rounding adjusts the LSB of the high part of the destination register according to the value of the low part of the register and then zeros the low part.
MPYR Register/Memory Address Before After L6:D6 $0:$00 2002 0000 EMR $0000 0000 0.100 0000 0000 0001$4001 x 0.100 0000 0000 0010$4002 0.010 0000 0000 0001 1000 0000 0000 0000$2001 8000 rounded 0.010 0000 0000 0010$2002 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 MPYR Da,Db,Dn 1 1 1 MPYR Da,Da,Dn 1 1 1 0 8 1 0 0 1 F F F * 1 0 0 0 F F F 15 Note: 0 7 * 8 0 0 1 J J J J 1 1 0 1 0 j 7 J 0 j ** indicates serial grouping encoding.
MPYR A-324 SC140 DSP Core Reference Manual
MPYSU MPYSU MPYSU Fractional Multiply Signed By Unsigned (DALU) Operation Assembler Syntax Dc.H * Dd.L → Dn MPYSU Dc,Dd,Dn Description MPYSU Dc,Dd,Dn Performs signed fractional multiplication between the signed 16-bit HP of the first register (Dc) of a data register pair with the unsigned 16-bit LP of the second register (Dd). It then stores the sign-extended 32-bit product in a destination data register (Dn). Status and Conditions that Affect Instruction None.
MPYSU Dn FFF 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-326 Single Source/Destination Data Register This instruction can specify D8-D15 as operands by using a prefix.
MPYUS MPYUS MPYUS Fractional Multiply Unsigned By Signed (DALU) Operation Assembler Syntax Dc.L * Dd.H → Dn MPYUS Dc,Dd,Dn Description MPYUS Dc,Dd,Dn Performs signed fractional multiplication between the unsigned 16-bit LP of the first register (Dc) of a data register pair with the signed 16-bit HP of the second register (Dd). It then stores the sign-extended 32-bit product in a destination data register (Dn). Status and Conditions that Affect Instruction None.
MPYUS Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix. FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-328 D0,D1 This instruction can specify D8-D15 as operands by using a prefix.
MPYUU MPYUU MPYUU Fractional Multiply Unsigned By Unsigned (DALU) Operation Assembler Syntax Dc.L * Dd.L → Dn MPYUU Dc,Dd,Dn Description MPYUU Dc,Dd,Dn Performs unsigned fractional multiplication between the unsigned 16-bit LP of the first register (Dc) of a data register pair with the unsigned 16-bit LP of the second register (Dd). It then stores the sign-extended 32-bit product in a destination data register (Dn). Status and Conditions that Affect Instruction None.
MPYUU Instruction Fields Dc,Dd ee Data Register Pairs 00 Note: Dn 01 D2,D3 10 D4,D5 11 D6,D7 This instruction can specify D8-D15 as operands by using a prefix. FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-330 D0,D1 This instruction can specify D8-D15 as operands by using a prefix.
NEG N-R NEG NEG Negate (DALU) Operation Assembler Syntax 0 – Dn → Dn NEG Dn Description NEG Dn Negates the contents of a source data register (Dn) and stores the 40-bit two’s complement result in a destination data register (Dn). Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode. SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the Ln bit calculation.
NEG Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 NEG Dn Note: 1 1 0 8 * 1 0 0 1 7 0 F F F 1 1 0 0 1 0 0 ** indicates serial grouping encoding. Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: A-332 Single Source/Destination Data Register 000 This instruction can specify D8-D15 as operands by using a prefix.
NOP NOP NOP No Operation (PREFIX) Operation Assembler Syntax no operation NOP Description NOP This instruction is encoded as a one-word prefix inside the set, or alone. If the NOP is the only instruction in the execution set, it takes one cycle to execute although no operation is done. This is useful in case delays are needed in a program for various reasons (for example, to account for pipeline delays). The NOP instruction is not dispatched to any execution unit.
NOT NOT NOT Bitwise Complement (DALU) Operation Assembler Syntax ~Da → Dn NOT Da,Dn Description NOT Da,Dn Replaces the contents of the destination data register (Dn) with the 40-bit one’s complement of the source data register (Da). Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination register.
NOT Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
NOT NOT Binary Inversion of a 16-Bit Operand (BMU) Operation Assembler Syntax ~DR.L → DR.L NOT DR.L ~DR.H→ DR.H NOT DR.H NOT Description NOT DR.L Inverts the LP of a source data or address register (DR). The other bits are unchanged. This instruction is assembler-mapped to BMCHG DR.L with the full mask enabled. NOT DR.H Inverts the HP of a source data or address register (DR). The other bits are unchanged. This instruction is assembler-mapped to BMCHG DR.H with the full mask enabled.
NOT Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 NOT DR.L 2 2 3 2 2 3 7 0 0 0 0 0 1 0 1 0 1 1 1 0 H H H H 1 0 1 1 1 1 1 1 1 1 1 1 8 7 15 NOT DR.
NOT.W NOT.W Binary Inversion of a 16-Bit Operand in Memory (BMU) NOT.W Operation Assembler Syntax ~(R) → (R) NOT.W (Rn) ~(SP–u5) → (SP–u5) NOT.W (SP–u5) {0 ≤ u5 < 64,W] ~(SP+s16) → (SP+s16) NOT.W (SP+s16) {–215 ≤ s16 < 215,W} ~(a16) → (a16) NOT.W (a16) {0 ≤ a16 < 216,W} Description These operations read from memory, invert the retrieved value, and write the new value back to the same memory address, resulting in two memory accesses.
NOT.W Example not.w (r1) Register/Memory Address Before After R1 $0000 0050 ($50) $FFFB $0004 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 NOT.
OR OR OR Bitwise Inclusive OR (DALU) Operation Assembler Syntax Da ⏐ Dn → Dn OR Da,Dn Description OR Da,Dn Performs a bitwise inclusive OR of two data registers (Da and Dn) and stores the result in the second data register (Dn). This is a full 40-bit operation. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers.
OR Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
OR OR Bitwise OR on a 16-Bit Operand (BMU) Operation Assembler Syntax #u16 ⏐ DR.L → DR.L OR #u16,DR.L {0 ≤ u16 < 216} #u16 ⏐ DR.H → DR.H OR #u16,DR.H {0 ≤ u16 < 216} OR Description OR #u16,DR.L Performs a bitwise inclusive OR of an immediate value with the LP of a data or address register (DR). It then stores the result in the LP of the destination data or address register (DR). The other register bits are not affected. This instruction is assembler-mapped to BMSET #u16,DR.
OR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 OR #u16,DR.L 2 3 2 2 3 7 0 0 0 0 0 1 0 0 1 i i i 0 H H H H 1 0 1 i i i i i i i i i 8 7 15 OR #u16,DR.
OR.W OR.W Bitwise OR on a 16-Bit Operand in Memory (BMU) OR.W Operation Assembler Syntax #u16 ⏐ (R) → (R) OR.W #u16,(Rn) {0 ≤ u16 < 216} #u16 ⏐ (SP–u5) → (SP–u5) OR.W #u16,(SP–u5) {0 ≤ u16 < 216} {0 ≤ u5 < 64,W] #u16 ⏐ (SP+s16) → (SP+s16) OR.W #u16,(SP+s16) {0 ≤ u16 < 216} {–215 ≤ s16 < 215,W} #u16 ⏐ (a16) → (a16) OR.
OR.W Example or.w #$f01a,(r1) Register/Memory Address Before After Immediate $F01A R1 $0000 0050 ($0050) $1235 $F23F 1111 0000 0001 1010 or 0001 0010 0011 0101 1111 0010 0011 1111 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 2 OR.
OR.
POP POP Pop a Register from the Software Stack (AGU) Operation Assembler Syntax (SP – 8) → De; SP – 8 → SP POP De (SP – 4) → Do; SP – 8 → SP POP Do POP Description These operations read the memory address pointed to by the active stack pointer (SP) into an even or odd register (De or Do) and adjust SP. All memory accesses are 32-bit long words. The registers are divided into two groups (even and odd) which determines the memory offset relative to the SP of the data being read.
POP Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer used, and which execution working mode . Status and Conditions Changed By Instruction Register Address Bit Name Description Ln L Pops of extensions restore the Ln bit in the destination register. Pops to data registers clear the Ln bit.
POP De EEEEE 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 — 01010 — 10010 SA0 11010 SA2 00011 D0.E 01011 D4.E 10011 D0.E:D1.E 11011 D4.E:D5.E 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 - 01110 — 10110 SA1 11110 SA3 00111 D2.E 01111 D6.E 10111 D2.E:D3.E 11111 D6.E:D7.
POPN POPN Pop a Register from the Software Stack Using the Normal Stack Pointer (AGU) Operation Assembler Syntax (NSP – 8) → De; NSP – 8 → ΝSP POPN De (NSP – 4) → Do; NSP – 8 → ΝSP POPN Do POPN Description These operations read the memory address pointed to by the normal stack pointer (NSP) into an even or odd register (De or Do) and adjust NSP regardless of the state of the exception (EXP) bit. All memory accesses are 32-bit long words.
POPN POPN De Restores data register extension pairs, even registers, and loop start registers from the normal stack. Data register extension pairs are popped the same as even numbered registers. POPN Do Restores modifier control, odd registers, and loop counter registers from the normal stack. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines execution working mode.
POPN De EEEEE 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 — 01010 — 10010 SA0 11010 SA2 00011 D0.E 01011 D4.E 10011 D0.E:D1.E 11011 D4.E:D5.E 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 - 01110 — 10110 SA1 11110 SA3 00111 D2.E 01111 D6.E 10111 D2.E:D3.E 11111 D6.E:D7.E Note: Do eeeee If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used.
PUSH PUSH Push a Register onto the Software Stack (AGU) Operation Assembler Syntax De → (SP); SP + 8 → SP PUSH De Do → (SP + 4); SP + 8 → SP PUSH Do PUSH Description These operations move an even or odd register (De or Do) to the active stack in memory and adjust SP. All memory accesses are 32-bit long words. The registers are divided into two groups (even and odd) which determines the memory offset relative to SP of the data being written.
PUSH Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer used, and execution working mode. Status and Conditions Changed By Instruction None Example push d0.e:d1.
PUSH Instruction Fields De EEEEE D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 — 01010 — 10010 SA0 11010 SA2 00011 D0.E 01011 D4.E 10011 D0.E:D1.E 11011 D4.E:D5.E 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 - 01110 — 10110 SA1 11110 SA3 D2.E 01111 D6.E 10111 D2.E:D3.E 11111 D6.E:D7.
PUSHN PUSHN Push a Register onto the Software Stack Using the Normal Stack Pointer (AGU) Operation Assembler Syntax De → (NSP); NSP + 8 → ΝSP PUSHN De Do → (NSP + 4); NSP + 8 → ΝSP PUSHN Do PUSHN Description These operations move an even or odd register (De or Do) to the normal stack in memory and adjusts the NSP, regardless of the state of the exception (EXP) bit. All memory accesses are 32-bit long words.
PUSHN Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines execution working mode. Status and Conditions Changed By Instruction Register Address Bit Name Description Ln L Pops of extensions restore the Ln bit in the destination register. Pops to data registers clear the Ln bit. Example pushn d0.e:d1.
PUSHN Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 PUSHN De 1 1 4 PUSHN Do 1 1 4 1 7 0 0 0 1 E E E 0 0 0 1 15 1 8 e e e 8 7 1 0 0 0 1 E 0 1 E 0 0 1 1 0 e 0 e 0 Instruction Fields De EEEEE 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 — 01010 — 10010 SA0 11010 SA2 00011 D0.E 01011 D4.E 10011 D0.E:D1.E 11011 D4.E:D5.
RND RND RND Round (DALU) Operation Assembler Syntax Rnd(Da) → Dn RND Da,Dn Description RND Da,Dn Rounds the 40-bit value in the source data register (Da) and stores the result in the destination data register (Dn). In the round function, the contribution of the least significant bits is rounded into the HP of the destination data register by adding a rounding constant RC to the LS bits of the source data register.
RND Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode. SR[3] RM Rounding mode SR[5:4] S[1:0] Scaling bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding.
RND Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 RND Da,Dn Note: 1 1 0 8 * 1 1 0 1 7 0 F F F 1 0 0 1 J J J ** indicates serial grouping encoding. Instruction Fields Dn FFF D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Da Single Source/Destination Data Register 000 This instruction can specify D8-D15 as operands by using a prefix.
ROL ROL Rotate One Bit Left Through the Carry Bit (DALU) Operation Assembler Syntax (Dn[38:0]<<1) → Dn[39:1] ROL Dn ROL Dn[39] → C C → Dn[0] Description ROL Dn Rotates the contents of a data register (Dn) one bit to the left. The carry bit C is shifted to bit 0, bit 39 is copied to the carry bit, and bits [38:0] are copied to bits [39:1]. C 39 32 31 16 15 0 Status and Conditions that Affect Instruction Register Address Bit Name Description SR[0] C The carry bit is copied into Dn[0].
ROL Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ROL Dn Note: 1 1 0 8 * 1 0 0 1 7 F F F 0 1 1 0 0 0 1 0 ** indicates serial grouping encoding. Instruction Fields Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
ROR ROR Rotate One Bit Right Through the Carry Bit (DALU) Operation Assembler Syntax (Dn[39–1]>>>1) → Dn[38–0] ROR Dn ROR C → Dn[39] Dn[0] → C Description ROR Dn Rotates the contents of a data register (Dn) one bit to the right. The carry bit C is shifted to bit 39, bit 0 is copied to the carry bit, and bits [39:1] are copied to bits [38:0]. C 39 32 31 16 15 0 Status and Conditions that Affect Instruction Register Address Bit Name Description SR[0] C The carry bit is copied into Dn[39].
ROR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 ROR Dn Note: 1 1 0 8 * 1 0 0 1 7 F F F 0 1 1 0 0 0 1 1 ** indicates serial grouping encoding. Instruction Fields Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
ROR RTE Return From Exception (AGU) Operation Assembler Syntax (SP – 8) → PC (SP – 4) → SR SP – 8 → SP 0 → NMID RTE RTE Description RTE Returns from an exception routine. The program counter and status register are popped from the active stack in memory, and program execution continues at the address specified in the PC. This instruction cannot appear in an execution set with another AGU instruction or a set that uses IFT and IFF, IFT and IFA, or IFF and IFA because RTE uses both AGUs.
ROR Example rte Register/Memory Address Before After ESP $00000010 ($000C) $00E00000 ($0008) $0000000A $00000008 PC $0000000A SR $00E40000 $00E00000 EMR $00000000 Instruction Formats and Opcodes Instruction Words Cycles1 Type 1 5/6 4 Opcode 15 RTE 1 0 0 1 1 1 1 8 7 1 0 0 1 1 1 0 0 1 1 Note 1: The shadow SP is valid or not valid. RTE uses 5 cycles if the shadow SP is valid. RTE uses 6 cycles if the shadow SP is not valid.
RTED RTED Return From Exception With a Delay Slot (AGU) Operation Assembler Syntax (SP – 8) → PC (SP – 4) → SR SP – 8 → SP 0 → NMID RTED RTED Description RTED Returns from an exception routine after executing the execution set in the delay slot. The program counter and status register are popped from the active stack in memory, and program execution continues at the address specified in PC.
RTED Example rted Instruction Comment move.w #$2000,vba Load the vector base address register. trap Issue a software interrupt and enter the exception state. - - - Instructions in the trap routine located at the address found at $2000 and trap_vector offset. rted not d4,d2 inc d1 Execute the not instruction and the inc d1 instruction in the delay slot. Return to the original working mode (see example for RTE).
RTS RTS Return From Subroutine (AGU) Operation Assembler Syntax If (RAS valid), then RAS → PC; else (SP – 8) → PC; RTS RTS always SP – 8 → SP Description RTS Returns from a subroutine. If the RAS is valid, the PC is restored from the RAS. Otherwise, the PC is popped from the active stack in memory as a 32-bit long word. The stack pointer always decrements by 8, RAS becomes invalid, and program execution continues at the address specified in the PC.
RTS Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 RTS 1 3/5/6 4 1 0 0 1 1 1 1 8 7 1 0 0 1 1 1 0 0 0 1 Note 1: RTS uses 3 cycles if the RAS is valid. RTS uses 5 cycles if the RAS is not valid and the shadow SP is valid. RTS uses 6 cycles if neither the RAS nor the shadow SP are valid.
RTSD RTSD Return From Subroutine With Delay Slot (AGU) Operation Assembler Syntax If (RAS valid), then RAS → PC; else (SP – 8) → PC; RTSD RTSD always SP – 8 → SP Description RTSD Returns from a subroutine after executing the execution set in the delay slot. If the RAS is valid, the PC is restored from the RAS. Otherwise, the PC is popped from the active stack in memory as a 32-bit long word. The implicit pop is done before the execution set in the delay slot is executed.
RTSD Instruction Formats and Opcodes Instruction Words Cycles1 Type Opcode 15 RTSD 1 3/5/6 4 1 0 0 1 1 1 1 8 7 1 0 0 1 1 1 0 0 0 0 Note 1: RTSD uses 3 cycles if the RAS is valid. RTSD uses 5 cycles if the RAS is not valid and the shadow SP is valid.RTSD uses 6 cycles if neither the RAS nor the shadow SP are valid. To get the correct cycle count for this instruction, subtract the execution time taken by the execution set in the delay slot.
RTSTK RTSTK Restore PC from Stack (AGU) Operation Assembler Syntax (SP – 8) → PC SP – 8 → SP RTSTK RTSTK Description RTSTK Forces a return from a subroutine or exception by restoring the program counter (PC) from the active stack in memory. The restore to the PC is not from the RAS register, even if RAS is valid. The implicit pop is done before the execution set in the delay slot is executed. The stack pointer decrements by 8 and RAS becomes invalid.
RTSTK Example rtstk Instruction Comment - - - SUB jsr SUB Jump to subroutine at SUB. Push the PC and SR onto the stack. - - - Skip over these instructions. MOVE.w #$16,d4 Execute the subroutine here. - - - lbl move.w #lbl,(SP-8) Change the original value in the stack for PC to lbl. rtstk Restore the new value lbl to PC. move.l #$16,d5 This instruction skipped. move.l #$16,d6 Continue executing here.
RTSTKD RTSTKD RTSTKD Restore PC from Stack Using a Delay Slot (AGU) Operation Assembler Syntax (SP – 8) → PC SP – 8 → SP RTSTKD Description RTSTKD Forces a return from a subroutine or exception by restoring the program counter (PC) from the active stack in memory after executing the execution set in the delay slot. The restore to the PC is not from the RAS register, even if RAS is valid. The implicit pop is done before the execution set in the delay slot is executed.
RTSTKD Example rtstkd Instruction Comment - - - SUB jsr SUB Jump to subroutine at SUB. Push the PC and SR onto the stack. - - - Skip over these instructions. MOVE.w #$16,d4 Execute the subroutine here. - - move.w #lbl,(SP-8) Change the original value in the stack for PC to lbl. rtstk move.l #$35,d1Restore the new value lbl to PC. Load $35 into d1. Increinc d1 ment d1 to $36, the delay slot instruction. lbl move.l #$16,d5 This instruction skipped. move.l #$16,d6 Continue executing here.
SAT.F S SAT.F Saturate Fractional Data Register (DALU) SAT.F Operation Assembler Syntax If Da > $007FFFFFFF then $007FFF0000 → Dn SAT.F Da,Dn If Da < $FF80000000 then $FF80000000 → Dn Else Da & $FFFFFF0000 → Dn Description SAT.F Da,Dn If the values of the extension bits [39:32] and bit 31 of the source register are all zeros or all ones (no overflow), the source register is transferred to the destination register, and the LP is cleared.
SAT.F Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 SAT.F Da,Dn Note: 1 1 0 8 * 1 1 0 1 7 0 F F F 1 0 1 1 J J J ** indicates serial grouping encoding. Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D15 as operands by using a prefix.
SAT.L SAT.L SAT.L Saturate 32-Bit Data Register (DALU) Operation Assembler Syntax If Dn > $007FFFFFFF then $007FFFFFF → Dn SAT.L Dn If Dn < $FF80000000 then $FF80000000 → Dn Else Dn → Dn Description SAT.L Dn If the values of the extension bits [39:32] and bit 31 of the source register are all zeros or all ones (no overflow), Dn is left alone.
SAT.L Instruction Fields Dn FFF Single Source/Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: This instruction can specify D8-D15 as operands by using a prefix.
SBC SBC Subtract With Borrow (DALU) Operation Assembler Syntax Db – Dc – C → Dd SBC Dc,Dd SBC Description SBC Dc,Dd Subtracts the first data register (Dc) from the second (Dd), then subtracts the borrow (C bit) and stores the result in the second data register (Dd). The source operands are a data register pair. The destination register is the second register of the pair. This instruction can be used in multiple-precision subtraction as illustrated in the example, which is a 64-bit subtraction.
SBC Register/Memory Address Before After SR $00E4 0001 $00E4 0000 EMR $0000 0000 The two instructions shown can be used for a 64-bit subtraction, with the sub d0,d1,d1 performing the lower 32 bits, and the resultant borrow used for the LSB calculation of the upper 32 bits calculated by sbc d2,d3. Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 SBC Dc,Dd Note: 1 1 0 * 1 0 1 1 e 8 7 e 0 0 1 1 1 1 0 1 1 ** indicates serial grouping encoding.
SBR SBR Subtract And Round (DALU) Operation Assembler Syntax Rnd(Dn – Da) → Dn SBR Da,Dn SBR Description SBR Da,Dn Subtracts the first data register (Da) of a pair from the second (Dn), then rounds the result and stores the result in the second data register (Dn). Rounding adjusts the LSB of the high part of the destination register according to the value of the low part of the register, and then zeros the low part. The two modes of the round function, Rnd(), are described on page A-359.
SBR 0010 1010 1110 0111 0000 0000 1000$2AE7 0080 – 0001 0101 0011 0000 0000 0000 0011$1539 0030 0001 0101 1010 1110 0000 0000 0101$15AE 0050 rounded $15AE 0000 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 SBR Da,Dn Note: 1 1 0 8 * 1 1 0 0 7 F F F 0 1 0 0 1 J J J ** indicates serial grouping encoding.
SKIPLS SKIPLS Skip Loop If LC Less Than or Equal to Zero (AGU) Operation If LCn ≤ 0, SKIPLS Assembler Syntax then PC + displacement → PC 0 → LFn SKIPLS label Description SKIPLS label Branches to an address that is the current PC plus the displacement and disables the active loop if its loop counter (LCn) is less than or equal to zero. The displacement is calculated by the assembler and linker.
SKIPLS Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 SKIPLS label 2 1/41 4 8 0 0 0 0 7 1 A A A 0 0 0 0 1 1 0 0 A A A A A A A A A A A A a 0 0 1 1 Note 1: If LC>1, the instruction takes 1 cycle. If LC<=0 and the branch is taken, the instruction takes 4 cycles. Instruction Fields displacement aAAAAAAAAAAAAAAA0 SC140 DSP Core Reference Manual 16-bit signed PC relative displacement.
STOP STOP Stop Instruction Processing (AGU) Operation Assembler Syntax Enter the stop processing state. STOP STOP Description STOP Halts instruction execution and enters the STOP processing state. This state is intended for the lowest power consumption mode. The core informs the system about the intention to enter the STOP processing state, and it is up to the system to shut down the clocks.
SUB SUB SUB Subtract (DALU) Operation Assembler Syntax Dn – #u5 → Dn SUB #u5,Dn {0 ≤ u5 < 32} Db – Da → Dn SUB Da,Db,Dn Description SUB #u5,Dn Subtracts an immediate unsigned 5-bit value from a data register (Dn) and stores the result in the destination data register (Dn). SUB Da,Db,Dn Subtracts one source data register (Da) from a second data register (Db) and stores the result in a destination data register (Dn).
SUB Register/Memory Address Before After L2:D2 $0:$FF FFFF FFFD EMR $0000 0000 Example 2 sub d0,d1,d2 Register/Memory Address Before After D0 $FF D000 0000 D1 $00 2000 0000 SR $00E4 0020 $00E4 0021 L2:D2 $1:$00 5000 0000 EMR $0000 0000 Scaling up is set in SR[5], so L2 bit is set from overflow from bit 30.
SUB Instruction Fields Da,Db JJJJJ Data Register Pairs 00000 D0,D4 01000 D2,D4 10000 D0,D0 11000 D1,D2 00001 D0,D5 01001 D2,D5 10001 D0,D1 11001 D1,D3 00010 D0,D6 01010 D2,D6 10010 D0,D2 11010 D5,D6 00011 D0,D7 01011 D2,D7 10011 D0,D3 11011 D5,D7 00100 D1,D4 01100 D3,D4 10100 D4,D4 11100 D2,D2 00101 D1,D5 01101 D3,D5 10101 D4,D5 11101 D2,D3 00110 D1,D6 01110 D3,D6 10110 D4,D6 11110 D6,D6 D1,D7 01111 D3,D7 10111 D4,D7 11111 D6,D7 00111 Notes:
SUB2 SUB2 Subtract Two 16-Bit Values (DALU) Operation Assembler Syntax Dn.H – Da.H → Dn.H Dn.L – Da.L → Dn.L SUB2 Da,Dn SUB2 Description SUB2 Da,Dn Performs a 32-bit subtraction of source register Da from Dn with borrow disabled between bits 15 and 16 so that the high and low words of each register are subtracted separately. The result is stored back in Dn. The extension byte of the result is undefined. Status and Conditions that Affect Instruction None.
SUB2 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 SUB2 Da,Dn 1 2 1 8 1 0 1 0 0 7 0 F F F 1 0 0 1 J J J Instruction Fields Dn FFF 000 001 Note: Da Single Source/Destination Data Register D0 010 D2 100 D4 110 D6 D1 011 D3 101 D5 111 D7 This instruction can specify D8-D15 as operands by using a prefix.
SUBA SUBA SUBA Subtract (AGU) Operation Assembler Syntax Rx – #u5 → Rx SUBA #u5,Rx {0 ≤ u5 < 64} Rx – rx → Rx SUBA rx,Rx Description This instruction subtracts an immediate or an AGU register from another AGU register. For R0-R7 destinations, this instruction is affected by the modifier mode selected in MCTL. SUBA #u5,Rx Subtracts an immediate unsigned 5-bit integer from an AGU register (Rx) and stores the result in the same register.
SUBA Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 SUBA #u5,Rx 1 1 2 SUBA rx,Rx 1 1 2 1 8 0 1 1 0 R R R R 0 1 1 0 R R R R 0 15 1 7 8 1 1 i i i i 0 1 1 r r r 7 i 0 r Instruction Fields rx rrrr 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: Rx This instruction can specify R8-R15 as operands by using a high register prefix.
SUBL SUBL Shift Left and Subtract (DALU) Operation Assembler Syntax (2 * Dn) – Da → Dn SUBL Da,Dn SUBL Description SUBL Da,Dn Subtracts the source register (Da) from two times the destination register (Dn) and stores the result in the destination register. Dn is arithmetically shifted left one bit prior to the subtraction operation. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SUBL Example 2 subl d0,d1 Register/Memory Address Before D0 After $00 0000 000A L1:D1 $0:$00 0000 0004 $0:$FF FFFF FFFE $00E4 0000 $00E4 0001 SR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 SUBL Da,Dn Note: 1 1 0 8 * 1 1 0 0 7 0 F F F 1 0 1 1 J J J ** indicates serial grouping encoding.
SUBNC.W SUBNC.W Subtract Without Changing the Carry Bit (DALU) SUBNC.W Operation Assembler Syntax Dn – #s16 → Dn SUBNC.W #s16,Dn {–215 ≤ s16 < 215} Description SUBNC.W #s16,Dn Subtracts an immediate signed 16-bit value from a source data register (Dn) and stores the result in the destination data register (Dn). The first operand is a 16-bit immediate data that is interpreted as a signed integer. The 16 bits are sign-extended to form a 32-bit operand.
SUBNC.W Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 SUBNC.W #s16,Dn 2 1 4 8 7 0 0 0 1 1 1 1 0 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i Instruction Fields Dn FFF 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: #s16 Single Source/Destination Data Register This instruction can specify D8-D15 as operands by using a prefix.
SXT.x SXT.x SXT.x Sign-Extension (DALU) Operation Assembler Syntax Da[7:0] → Dn[7:0]; Da[7] → Dn[39:8] SXT.B Da,Dn Da[15:0] → Dn[15:0]; Da[15] → Dn[39:16] SXT.W Da,Dn Dn[31] → Dn[39:32] SXT.L Dn Description These operations sign-extend a data register. The sign bit (bit 7 in a byte, bit 15 in a word, and bit 31 in a long word) is copied to the upper bits in a 40-bit data register. SXT.B Da,Dn Sign-extends a byte from a source data register (Da[7:0]) into a destination data register (Dn). SXT.
SXT.x Register/Memory Address Before L2:D2 After $0:00 B400 0000 $0:$00 0000 7056 Example 3 sxt.l d3 Register/Memory Address Before L3:D3 After $0:$B4 8E60 6EC6 $0:$FF 8E60 6EC6 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 SXT.B Da,Dn 1 1 1 SXT.W Da,Dn 1 1 1 SXT.
SXTA.x SXTA.x SXTA.x Sign-Extension (AGU) Operation Assembler Syntax rx[7:0] → Rx[7:0]; rx[7] → Rx[31:8] SXTA.B rx,Rx Rx[15] → Rx[31:16] SXTA.W Rx Description These operations sign-extend an AGU register (address or offset register, program counter, or stack pointer). The sign bit (bit 7 in a byte or bit 15 in a word) is copied to the upper bits in a 32-bit AGU register. SXTA.B rx,Rx Sign-extends a byte from a source AGU register (rx[7:0]) into a destination AGU register (Rx). SXTA.
SXTA.x Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 SXTA.B rx,Rx 1 1 2 SXTA.
TFR T-Z TFR Transfer Data Register to Data Register (DALU) Operation Assembler Syntax Da → Dn TFR Da,Dn TFR Description TFR Da,Dn Copies a source data register (Da) to a destination data register (Dn). The Ln bit is re-calculated (not copied) in the destination register. Saturation mode is ignored and no saturation is done.
TFR Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 TFR Da,Dn Note: 1 1 0 8 * 1 1 0 1 7 F F F 0 1 0 1 0 J J J ** indicates serial grouping encoding. Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D15 as operands by using a prefix.
TFRA TFRA TFRA Transfer Address Register (AGU) Operation Assembler Syntax rx → Rx TFRA rx,Rx Description TFRA rx,Rx Copies a source AGU register (rx) to a destination AGU register (Rx). Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR. Status and Conditions Changed by Instruction None.
TFRA Rx RRRR AGU Source/Destination Register 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 — 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: This instruction can specify R8-R15 as operands by using a high register prefix.
TFRA TFRA Move the Other Stack Pointer to/from a Register (AGU) Operation TFRA Assembler Syntax If (SR[EXP] = 1), then NSP → Rn else ESP → Rn TFRA OSP,Rn If (SR[EXP] = 1), then Rn → NSP else Rn → ESP TFRA Rn,OSP Description TFRA OSP,Rn Writes the value of the inactive (other) stack pointer (OSP) to an address register (Rn). If EXP (SR[18]) is set, then OSP is the normal stack pointer (NSP). Otherwise, OSP is the exception stack pointer (ESP).
TFRA Example tfra r0,osp Register/Memory Address Before After SR $00E40000 R0 $2A33217B NSP $2A332178 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 TFRA OSP, Rn 1 4 1 0 0 1 1 0 1 15 1 TFRA Rn, OSP 1 4 1 0 0 1 1 0 1 8 7 0 0 8 7 0 0 0 1 1 1 0 R R R 0 1 1 1 1 R R R Instruction Fields Rn RRR 000 001 Note: Address Register R0 010 R2 100 R4 110 R6 R1 011 R3 101 R5 111 R7 If registers R8–R15 are accessed instead of R0
TFRc TFRc Conditionally Transfer Data Register to Data Register (DALU) Operation Assembler Syntax If T=1, then Da → Dn TFRT Da,Dn If T=0, then Da → Dn TFRF Da,Dn TFRc Description TFRT Da, Dn Copies a source data register (Da) to a destination data register (Dn) if the T bit is set. TFRF Da, Dn Copies a source data register (Da) to a destination data register (Dn) if the T bit is cleared.
TFRc Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 TFRT Da,Dn 1 1 2 TFRF Da,Dn 1 1 2 1 8 1 0 1 0 0 F F F 1 0 1 0 0 F F F 15 1 7 8 0 1 0 1 0 J J J 1 0 1 1 J J J 7 0 Instruction Fields Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note: Dn This instruction can specify D8-D15 as operands by using a prefix.
TRAP TRAP Execute a Software Exception (AGU) Operation Next PC → (ESP), SR → (ESP + 4), ESP + 8 → ESP VBA[31:12]:trap_vector → PC 0 → EXP 0→C 0→T 00 → S[1:0] 0 → SLF 0000 → LS[3:0] TRAP Assembler Syntax TRAP {trap_vector = $000} Description TRAPn The TRAP instruction creates a precise software interrupt, halting execution and jumping to a code section pointed to from the exception table.
TRAP Status and Conditions Changed by Instruction Register Address Bit Name Description SR[18] EXP Set SR[0] C Cleared SR[1] T Cleared SR[5:4] S[1:0] Cleared SR[31] SLF Cleared SR[30:27] LF[3:0] Cleared SR[23:21] I[2:0] Set interrupt priority level to 111.
TSTEQ TSTEQ TSTEQ Test for Equal to Zero (DALU) Operation Assembler Syntax If Dn == 0, then 1 → T, else 0 → T TSTEQ Dn Description TSTEQ Dn Sets the T bit in SR if the source data register (Dn) is equal to zero; otherwise, it clears the T bit. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if the source operand is equal to zero and cleared if the source operand is not equal to zero.
TSTEQA.x TSTEQA.x Test for Equal to Zero (AGU) Operation Assembler Syntax If Rx[15:0] == 0, then 1 → T, else 0 → T TSTEQA.W Rx If Rx[31:0] == 0, then 1 → T, else 0 → T TSTEQA.L Rx TSTEQA.x Description Set the T bit if the source AGU register (Rx) is equal to zero; otherwise, clears the T bit. TSTEQA.W Rx Tests only the lower word (bits [15:0]) of the source operand. TSTEQA.L Rx Tests all 32 bits of the source operand.
TSTEQA.x Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 TSTEQA.W Rx 1 1 2 TSTEQA.
TSTGE TSTGE TSTGE Test for Greater Than or Equal to Zero (DALU) Operation Assembler Syntax If Dn >= 0, then 1 → T, else 0 → T TSTGE Dn Description TSTGE Dn Sets the T bit if the source data register (Dn) is greater than or equal to zero; otherwise, clears the T bit. The value in Dn is treated as a signed number Status and Conditions that Affect Instruction None.
TSTGEA.L TSTGEA.L Test for Greater Than or Equal to Zero (AGU) Operation Assembler Syntax If Rx ≥ 0, then 1 → T, else 0 → T TSTGEA.L Rx TSTGEA.L Description TESTGEA.L Rx Sets the T bit if the source AGU register (Rx) is greater than or equal to zero; otherwise, it clears the T bit. The value in Rx is treated as a signed number.
TSTGEA.L Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 1 TSTGEA.L Rx 1 2 1 8 1 1 7 0 R R R R 1 0 1 1 1 0 0 1 1 Instruction Fields Rx RRRR AGU Source/Destination Register 0000 N0 0100 — 1000 R0 1100 R4 0001 N1 0101 — 1001 R1 1101 R5 0010 N2 0110 — 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note: This instruction can specify R8-R15 as operands by using a high register prefix.
TSTGT TSTGT TSTGT Test for Greater Than Zero (DALU) Operation Assembler Syntax If Dn > 0, then 1 → T, else 0 → Τ TSTGT Dn Description TSTGT Dn Sets the T bit if the source data register (Dn) is greater than zero; otherwise, clears the T bit. Status and Conditions that Affect Instruction None. Status and Conditions Changed by Instruction Register Address Bit Name Description SR[1] T Set if the source operand is greater than zero and cleared if the source operand is not greater than zero.
TSTGTA TSTGTA TSTGTA Test for Greater Than Zero (AGU) Operation Assembler Syntax If Rx > 0, then 1 → T, else 0 → Τ TSTGTA Rx Description TSTGTA Rx Sets the T bit if the source AGU register (Rx) is greater than zero; otherwise, clears the T bit. Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines which stack pointer is used when the stack pointer is an operand. Otherwise, the instruction is not affected by SR.
VSL VSL Viterbi Shift Left Move (AGU) Operation VSL Assembler Syntax If VF2 == 1, then (D3.L << 1+1) → (word 3)* else (D1.L << 1+1) → (word 3) If VF0 == 1, then (D3.L << 1) → (word 2) else (D1.L << 1) → (word 2) VSL.4W D2:D6:D1:D3,(Rn)+N0 D2.L → (word 0) D6.L → (word 1) If VF3 == 1, then (D3.H << 1+1) → (word 3) else (D1.H << 1+1) → (word 3) If VF1 == 1, then (D3.H << 1) → (word 2) else (D1.H << 1) → (word 2) VSL.4F D2:D6:D1:D3,(Rn)+N0 D2.H → (word 0) D6.
VSL Description The VSL instructions are intended to optimize the implementation of the Viterbi decoder algorithm. They are used in conjunction with the MAX2VIT instruction, which sets the Viterbi flags and stores the maximum portions of data register pairs into the destination registers for use with VSL. See MAX2VIT, page A-249. The VSL instructions do not behave the same in little and big endian modes, meaning that data in source registers is written to different memory locations in the two modes.
VSL Status and Conditions that Affect Instruction Register Address Bit Name Description MCTL[31:0] AM3–AM0 Address modification bits for R0–R7. SR[8] VF0 Viterbi flag 0 set by MAX2VIT D4,D2. SR[9] VF1 Viterbi flag 1 set by MAX2VIT D4,D2. SR[10] VF2 Viterbi flag 2 set by MAX2VIT D0,D6. SR[11] VF3 Viterbi flag 3 set by MAX2VIT D0,D6. EMR[16] BEM Set if big endian mode, cleared if little endian mode. Status and Conditions Changed by Instruction None. Example vsl.
VSL Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 VSL.4W 1 1 2 1 1 2 1 1 2 1 8 7 0 1 0 0 1 0 1 0 8 7 1 0 0 1 0 1 0 0 8 7 1 0 0 1 0 1 0 0 8 7 0 0 0 0 0 0 0 R R R 0 0 1 0 R R R 0 1 0 0 R R R D2:D6:D1:D3,(Rn)+N0 15 VSL.4F 1 0 D2:D6:D1:D3,(Rn)+N0 15 VSL.2W D1:D3,(Rn)+N0 1 15 1 VSL.
WAIT WAIT Wait for an Interrupt (AGU) Operation Assembler Syntax Enters the low-power standby WAIT processing state. WAIT WAIT Description WAIT Enters the low-power standby WAIT processing state. All internal core processing is halted until an unmasked interrupt occurs, the DSP is reset, the EE0 is asserted, or a JTAG debug request command is issued.
WAIT Status and Conditions that Affect Instruction Register Address Bit Name Description SR[18] EXP Determines execution working mode.
ZXT.x ZXT.x ZXT.x Zero Extension (DALU) Operation Assembler Syntax Da[7:0] → Dn[7:0]; 0 → Dn[39:8] ZXT.B Da,Dn Da[15:0] → Dn[15:0]; 0 → Dn[39:16] ZXT.W Da,Dn 0 → Dn[39:32] ZXT.L Dn Description These operations zero-extend a data register. ZXT.B Da,Dn Copies bits [7:0] from a source data register (Da) to a 40-bit destination data register (Dn) and zero-extends bits [39:8] of Dn. ZXT.
ZXT.x Register/Memory Address Before After L6:D6 $0:$00 0000 5EC4 Example 3 zxt.l d0 Register/Memory Address Before L0:D0 After $0:$FF A836 A7C4 $0:$00 A836 A7C4 Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 ZXT.B Da,Dn 1 1 1 ZXT.W Da,Dn 1 1 1 ZXT.
ZXTA.x ZXTA.x ZXTA.x Zero Extension (AGU) Operation Assembler Syntax rx[7:0] → Rx[7:0]; 0 → Rx[31:8] ZXTA.B rx,Rx 0 → Rx[31:16] ZXTA.W Rx Description These operations zero-extend an AGU source register (address or offset register, program counter, or stack pointer). ZXTA.B rx,Rx Copies bits [7:0] from a source AGU register (rx) to a 32-bit destination AGU register (Rx) and zero-extends bits [31:8] of Rx. ZXTA.W Rx Zero-extends bits [31:16] of Rx.
ZXTA.x Instruction Formats and Opcodes Instruction Words Cycles Type Opcode 15 ZXTA.B rx,Rx 1 1 2 ZXTA.
ZXTA.
Appendix B StarCore Registry The StarCore registry (SCR) is a system that identifies the core version. B.1 Using the StarCore Registry The SCR is to be used for debugging software and run-time software. A StarCore Identification number, SCID, is encoded in bits 23-17 of the EOnCE Status Register (ESR). This 32-bit, memory-mapped, read-only register is located at offset 00 from the EOnCE register base address defined by each System-on-a-Chip (SoC) derivative.
StarCore Registry Table B-1.
Index A AAU (address arithmetic unit) 1-3, 2-4 ABS A-20 Accelerator 2-5, 6-57 Access width support 2-42 ADC A-22 ADD A-24 ADD2 A-27 ADDA A-29 ADDL1A A-32 ADDL2A A-34 ADDNC.
CCS (comparator condition selection bits) 4-60 Change-of-flow instructions 2-68 CLB A-113 CLR A-115 CMPEQ A-117 CMPEQ.W A-119 CMPEQA A-121 CMPGT A-123 CMPGT.
CS 4-55 EDCAEN 4-55 EDCAST5-0 (EDCA #5-0 status) 4-42 EDCD (data event detection channel) 4-24, 4-58 control register (EDCD_CTRL) 4-58 mask register (EDCD_MASK) 4-61 reference value register (EDCD_REF) 4-61 EDCD_CTRL (EDCD control register) 4-58 ATS 4-60 AWS 4-59 CCS 4-60 EDCDEN 4-60 EDCD_MASK (EDCD mark register) 4-61 EDCD_REF (reference value register) 4-61 EDCDEN (EDCD enable) 4-60 EDCDST (EDCD status) 4-42 EDU (event detection unit) 4-54 address event detection channel (EDCA) 4-22, 4-54 data event detec
ESEL_DTB (ES mask disable trace register) 4-26, 4-65 ESEL_ETB (ES mask enable trace register) 4-26, 4-64 ESP (exception stack pointer register) 2-35 ESR (EOnCE status register) 4-37 CORES 4-38 CORETP 4-39 DRCOUNTER 4-40 DREE4-0 4-39 DRSW 4-39 DRTBFULL 4-39 NOCHOF 4-39 PCKILL 4-38 RCV 4-38 REVNO 4-39 TBFULL 4-39 TRSMT 4-38 ESR register 4-38 DREDCA7-0 4-40 Event counter control register (ECNT_CTRL) 4-50 programming model 4-18, 4-50 value register (ECNT_VAL) 4-52 Event counter control 4-18 Event selector ESEL_
BMSET.W A-82 BMTSET A-84 BMTSET.W A-86 BMTSTC A-89 BMTSTC.W A-91 BMTSTS A-94 BMTSTS.W A-96 BRA A-99 BRAD A-101 BREAK A-103 BSR A-105 BSRD A-107 BT A-109 BTD A-111 CLB A-113 CLR A-115 CMPEQ A-117 CMPEQ.W A-119 CMPEQA A-121 CMPGT A-123 CMPGT.W A-125 CMPGTA A-127 CMPHI A-129 CMPHIA A-131 CONT A-133 CONTD A-135 DEBUG A-137 DEBUGEV A-138 DECA A-139 DECEQ A-141 DECEQA A-143 DECGE A-144 DECGEA A-146 DI A-148 DIV A-150 DMACSS A-153 DMACSU A-155 DOENn A-157 DOENSHn A-159 DOSETUPn A-161 EI A-163 EOR A-165, A-167 EOR.
NOT.W A-338 OR A-340, A-342 OR.W A-344 POP A-347 POPN A-350 PUSH A-353 PUSHN A-356 RND A-359 ROL A-362 ROR A-364 RTE A-366 RTED A-368 RTS A-370 RTSD A-372 RTSTK A-374 RTSTKD A-376 SAT.F A-378 SAT.L A-380 SBC A-382 SBR A-384 SKIPLS A-386 STOP A-388 SUB A-389 SUB2 A-392 SUBA A-394 SUBL A-396 SUBNC.W A-398 SXT.x A-400 SXTA.x A-402 TFR A-404 TFRA A-406, A-408 TFRc A-410 TRAP A-412 TSTEQ A-414 TSTEQA.x A-415 TSTGE A-417 TSTGEA.L A-418 TSTGT A-420 TSTGTA A-421 VSL A-422 WAIT A-426 ZXT.x A-428 ZXTA.
MIN A-253 Modifier registers (M0-M3) 2-36 Modulo adder 2-33 Modulo addressing 2-4 Modulo addressing mode 2-45 Move instructions 2-51, 2-52 fractional moves 2-54 integer moves 2-53 MOVE.2F A-254 MOVE.2L A-256 MOVE.2W A-258 MOVE.4W A-262 MOVE.B A-264 MOVE.F A-268 MOVE.L A-272, A-275, A-279 MOVE.W A-285, A-289 MOVEc A-295 MOVES.2F A-297 MOVES.F A-299 MOVES.L A-301 MOVEU.B A-307 MOVEU.L A-311 MOVEU.
RM (rounding mode bit) 3-5 RND A-359 ROL A-362 ROR A-364 Rounding 2-21, 2-23 RTE A-366 RTED A-368 RTS A-370 RTSD A-372 RTSTK A-374 RTSTKD A-376 S S (scaling bit) 3-5 S1-0 (scaling mode bits) 3-5 SAT.F A-378 SAT.
Trace unit control register (TB_CTRL) 4-65 read pointer register (TB_RD) 4-69 register set 4-30 virtual register (TB_BUFF) 4-69 write pointer register (TB_WR) 4-69 TRAP 5-37, A-412 TRSINT (transmit interrupt) 4-41 TRSMT (transmit) 4-38 TRST (test reset pin) 4-2 True bit 3-6 TSTEQ A-414 TSTEQA.x A-415 TSTGE A-417 TSTGEA.
I-10 Index
SC140 DSP Core Reference Manual i