DSP Core Reference Manual

4-40 SC140 DSP Core Reference Manual
EOnCE Controller Registers
DREE3
Bit 13
Debug Reason is EE3 — Set when the core enters debug state or executes a
debug exception as a result of EE3 assertion. It is cleared by the EOnCE when the
core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE2
Bit 12
Debug Reason is EE2 — Set when the core enters debug state or executes a
debug exception as a result of EE2 assertion. It is cleared by the EOnCE when the
core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE1
Bit 11
Debug Reason is EE1 — Set when the core enters debug state or executes a
debug exception as a result of the EE1 assertion. It is cleared by the EOnCE when
the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE0
Bit 10
Debug Reason is EE0 — Set when the core enters debug state or executes a
debug exception as a result of EE0 assertion. It is cleared by the EOnCE when the
core exits debug state, or when the DIS bit in EMCR is reset by the user.
DRCOUNTER
Bit 9
Debug Reason is Counter — Set when the core enters debug state or executes a
debug exception as a result of a count event. It is cleared by the EOnCE when the
core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCAD
Bit 8
Debug Reason is EDCD — Set when the core enters debug state or executes a
debug exception as a result of detection by the EDCD. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA7
Bit 7
Debug Reason is EDCA7 — Set when the core enters debug state or executes a
debug exception as a result of detection by the optional external EDCA7. It is
cleared by the EOnCE when the core exits debug state, or when the DIS bit in
EMCR is reset by the user.
DREDCA6
Bit 6
Debug Reason is EDCA6 — Set when the core enters debug state or executes a
debug exception as a result of detection by the optional external EDCA6. It is
cleared by the EOnCE when the core exits debug state, or when the DIS bit in
EMCR is reset by the user.
DREDCA5
Bit 5
Debug Reason is EDCA5 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA5. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA4
Bit 4
Debug Reason is EDCA4 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA4. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA3
Bit 3
Debug Reason is EDCA3 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA3. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA2
Bit 2
Debug Reason is EDCA2 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA2. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA1
Bit 1
Debug Reason is EDCA1 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA1. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA0
Bit 0
Debug Reason is EDCA0 — Set when the core enters debug state or executes a
debug exception as a result of detection by EDCA0. It is cleared by the EOnCE
when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
Table 4-14. ESR Description (Continued)
Name Description