DSP Core Reference Manual

MOVES.4F
SC140 DSP Core Reference Manual A-67
BFD Branch If False Using a Delay Slot (AGU) BFD
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None.
Example
BFD lbl
Operation Assembler Syntax
If T==0, then PC + displacement → PC
BFD <label
BFD >label
BFD <label
BFD >label
Branches to label if the true bit is cleared. If the T bit is cleared, the program continues executing at
location PC + displacement. If the T bit is set, the PC is updated to point to the next execution set, and the
program continues executing sequentially. The displacement, calculated by the assembler and linker, is a
two’s complement integer that represents the relative distance from the current PC to the destination label.
The assembler determines if the PC relative displacement is a short branch (<label [–2
8
≤ displacement <
2
8
, W]) or a long branch (>label [–2
20
≤ displacement < –2
8
, W and 2
8
≤ displacement < 2
20
, W]). The
execution set in the delay slot immediately following the BFD instruction is executed unconditionally after
the execution set containing the BFD instruction.
Register Address Bit Name Description
SR[1] T True bit
Instruction Result
cmpeq.w #$35,d1 Not equal, so T bit in SR cleared.
bfd lbl move.w #$29,d1 Branch taken, move.w executed.
inc d1 Increment executed in the delay slot.
move.w #$47,d2 Skipped over.
- - - - Skipped over.
- - - - Skipped over.
- - - - Skipped over.
lbl move.w #$1A,d4 Execution continues here at lbl.
Register/Memory Address Before After
SR
$00E0 0000