DSP Core Reference Manual

A-108 SC140 DSP Core Reference Manual
BSRD
Instruction Formats and Opcodes
Instruction Fields
Instruction Words
Cycles
1
Note 1: The branch uses 4 cycles minus the execution time used by the execution set in the delay slot. The cycle
count for this instruction cannot be less than 2 cycles. The branch uses 5 cycles, minus the execution time
used by the execution set in the delay slot, if the total of the largest cycle time of the instructions grouped
with the BSRD and the execution time of the delay slot set is ≥ 4. One cycle is used by the core to push the
return address onto the stack.
Type Opcode
15 8 7 0
BSRD <label 1 4/5 4 1000001AAAAAAAA0
15 8 7 0
BSRD >label 2 4/5 4 0010a010AAA11aaa
100AAAAAAAAAAAAa
displacement
(<label)
AAAAAAAA0 8-bit signed PC relative displacement
displacement
(>label)
aaaaaAAAAAAAAAAAAAA
A0
20-bit signed PC relative displacement