DSP Core Reference Manual

DALU

SC140 DSP Core Reference Manual 2-13

2.2.1.4 Data Shifter/Limiter

The data shifters/limiters provide special post-processing on data written from a Dn register to the XDBA

or XDBB buses. There are eight independent shifters/limiters, four for the XDBA bus and four for the

XDBB bus, allowing transfers to memory of up to four words per MOVES instruction with scaling and

limiting. Each consists of a shifter for scaling followed by a limiter. Note that arithmetic saturation from

DALU operations is a different function. Saturation occurs in the DALU before data is written to a

destination register.

Table 2-6. DALU Logical Instructions (BFU)

Instruction Description

AND Logical AND

ASLL Multi-bit arithmetic shift left

ASLW Word arithmetic shift left (16-bit shift)

ASRR Multi-bit arithmetic shift right

ASRW Word arithmetic shift right (16-bit shift)

CLB Count leading bits (ones or zeros)

EOR Bit-wise exclusive OR

EXTRACT Extract signed bit-field

EXTRACTU Extract unsigned bit-field

INSERT Insert bit-field

LSLL Multi-bit logical shift left

LSR Logical shift right by one bit

LSRR Multi-bit logical shift right

LSRW Word logical shift right (16-bit shift)

NOT One’s complement (inversion)

OR Bit-wise inclusive OR

ROL Rotate one bit left through the carry bit

ROR Rotate one bit right through the carry bit

SXT.B Sign extend byte

SXT.L Sign extend long

SXT.W Sign extend word

ZXT.B Zero extend byte

ZXT.L Zero extend long

ZXT.W Zero extend word