DSP Core Reference Manual

DECEQ
SC140 DSP Core Reference Manual A-141
DECEQ Decrement and Set T If Equal Zero (DALU) DECEQ
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
deceq d7
Instruction Formats and Opcodes
Note: ** indicates serial grouping encoding.
Operation Assembler Syntax
Dn – 1 → Dn; if Dn==0, then 1→ T, else 0 → T
DECEQ Dn
DECEQ Dn
Decrements a data register (Dn) and sets the T bit if the result is equal to zero.
Register Address Bit Name Description
SR[0] C Calculates and updates the carry bit in the status register.
SR[1] T Set if result = 0, cleared otherwise.
EMR[2] DOVF Set if the result cannot be represented in 40 bits.
Ln L Clears the Ln bit in the destination register.
Register/Memory Address Before After
L7:D7
$0:$00 0000 0001 $0:$00 0000 0000
SR
$00E4 0000 $00E4 0002
EMR
$0000 0000
Instruction Words Cycles Type Opcode
15 8 7 0
DECEQ Dn 1 1 1 0*1001FFF1101101