DSP Core Reference Manual

MPYUS
SC140 DSP Core Reference Manual A-327
MPYUS Fractional Multiply MPYUS
Unsigned By Signed (DALU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
mpyus d2,d3,d4
1.100 $C000 (–2
–1
)
x 0.000 0000 0000 0010$0002 (2
–14
)
1.111 1111 1111 1111$FFFF (–2
–15
)
Instruction Formats and Opcodes
Note: ** indicates serial grouping encoding.
Operation Assembler Syntax
Dc.L * Dd.H → Dn
MPYUS Dc,Dd,Dn
MPYUS Dc,Dd,Dn
Performs signed fractional multiplication between the unsigned 16-bit LP of the first register (Dc) of a data
register pair with the signed 16-bit HP of the second register (Dd). It then stores the sign-extended 32-bit
product in a destination data register (Dn).
Register Address Bit Name Description
Ln L Clears the Ln bit in the destination registers.
Register/Memory Address Before After
D2
$FF FF00 0002
D3
$FF C000 0042
L4:D4
$0:$FF FFFF 0000
Instruction Words Cycles Type Opcode
15 8 7 0
MPYUS Dc,Dd,Dn 1 1 1 0*1000FFF11101ee