DSP Core Reference Manual

A-396 SC140 DSP Core Reference Manual

SUBL

SUBL Shift Left and Subtract (DALU) SUBL

Description

Status and Conditions that Affect Instruction

Status and Conditions Changed by Instruction

Example 1

subl d0,d1

Operation Assembler Syntax

(2 * Dn) – Da → Dn

SUBL Da,Dn

Subtracts the source register (Da) from two times the destination register (Dn) and stores the result in the

destination register. Dn is arithmetically shifted left one bit prior to the subtraction operation.

SR[2] SM If set, selects 32-bit arithmetic saturation mode.

SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the

Ln bit calculation.

SR[0] C Calculates the borrow and updates the carry bit in the status

EMR[2] DOVF Set if the MS bit of the result cannot be represented in 40 bits, or

saturates to 32 bits in arithmetic saturation mode, or the MS bit of

the result changed due to the instruction’s left shift operation.

Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and

updates the Ln bit in the destination register. If in arithmetic

saturation mode (SR [SM] = 1), clears the Ln bit in the destination

$00E0 0000 $00E0 0000

$00 0000 0003

L1:D1

$0:$00 0000 0004 $0:$00 0000 0005

EMR

$0000 0000