DSP Core Reference Manual
Index I-7
MIN A-253
Modifier registers (M0-M3) 2-36
Modulo adder 2-33
Modulo addressing 2-4
Modulo addressing mode 2-45
Move instructions 2-51
, 2-52
fractional moves 2-54
integer moves 2-53
MOVE.2F A-254
MOVE.2L A-256
MOVE.2W A-258
MOVE.4W A-262
MOVE.B A-264
MOVE.F A-268
MOVE.L A-272
, A-275, A-279
MOVE.W A-285
, A-289
MOVEc A-295
MOVES.2F A-297
MOVES.F A-299
MOVES.L A-301
MOVEU.B A-307
MOVEU.L A-311
MOVEU.W A-313
, A-315
MPY A-319
MPYR A-322
MPYSU A-325
MPYUS A-327
MPYUU A-329
Multiple wrap-around modulo addressing mode 2-47
Multiplication 2-20
Multiply-accumulate (MAC) 1-3
Multiply-accumulate (MAC) unit 2-10
Multi-precision arithmetic support 2-28
, 2-30
N
N0-N3 (offset registers) 2-36
NEG A-331
Nested loop 5-31
NMI (non-maskable interrupts) 5-50
NMID (NMI disable bit) 3-8
NOCHOF (no CHOF in debug mode) 4-39
NOP A-333
definition 7-60
NOT A-334
, A-336
NOT.W A-338
NSP (normal stack pointer register) 2-35
O
Offset adder 2-4
Offset registers (N0-N3) 2-36
OR A-340
, A-342
OR.W A-344
OVE (overflow exception enable bit) 3-4
P
PAB (program address bus) 2-1
PAG (program address generator) 2-5
PC (program counter) 1-3
, 2-5
PC relative addressing modes 2-40
PC relative mode 2-40
PC_DETECT (PC breakpoint detection register) 4-49
PC_EXCP (PC of the exception execution set) 4-49
PC_LAST (PC of last execution set) 4-49
PC_NEXT (PC of the next execution set) 4-49
PCKILL (PC killed) 4-38
PCU (program control unit) 2-5
PDB (program data bus) 2-1
PDU (program dispatch unit) 2-5
Pipeline 5-1
address generation 5-4
execution 5-5
instruction dispatch 5-4
instruction pre-fetch and fetch 5-4
stages 5-2
, 5-3
POP A-347
POPN A-350
Power saving considerations 4-16
Pre-fetch and fetch stages 5-4
Prefix Grouping 5-7
Prefix word encoding A-7
Processing states 5-41
debug mode 5-44
exception 5-37
reset 5-43
stop 5-45
wait 5-44
Program control 5-1
Program control instructions 5-41
Programming rules
ISAP-specific 6-67
PSEQ (program sequencer and control unit) 1-3
, 2-5
PSEQ (program sequencer unit) 2-5
PUSH A-353
PUSHN A-356
R
R/W (read or write command bit) 4-36
R0–R7 registers 2-35
, 2-37
RCV (receive) 4-38
RCVINT (receive interrupt) 4-41
Register direct addressing modes 2-38
Register indirect addressing modes 2-38
REGSEL (register select) 4-37
Reset processing state 5-43
Reverse-carry addressing mode 2-45
REVNO (revision number) B-1
bits 4-39