User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
10 Freescale Semiconductor
• Supports active promiscuous mode
3.3.5 Packet buffering
The packet buffer is a 128-byte random access memory (RAM) dedicated to the storage of 802.15.4 packet
contents for both TX and RX sequences. For TX sequences, software stores the contents of the packet
buffer starting with the frame length byte at packet buffer address 0, followed by the packet contents at the
subsequent packet buffer addresses. For RX sequences the incoming packet’s frame length is stored in a
register, external to the packet buffer. Software will read this register to determine the number of bytes of
packet buffer to read. This facilitates DMA transfer through the SPI. For receive packets, an LQI byte is
stored at the byte immediately following the last byte of the packet (frame length +1). Usage of the packet
buffer for RX and TX sequences is on a time-shared basis; receive packet data will overwrite the contents
of the packet buffer. Software can inhibit receive-packet overwriting of the packet buffer contents by
setting the PB_PROTECT bit. This will block RX packet overwriting, but will not inhibit TX content
loading of the packet buffer via the SPI.
3.3.5.1 Features
• 128 byte buffer stores maximum length 802.15.4 packets
• Same buffer serves both TX and RX sequences
• The entire Packet Buffer can be uploaded or downloaded in a single SPI burst.
• Automatic address auto-incrementing for burst accesses
• Single-byte access mode supported.
• Entire packet buffer can be accessed in hibernate mode
• Under-run error interrupt supported
3.4 Dual PAN ID
In the past, radio transceivers designed for 802.15.4 and ZigBee applications allowed a device to associate
to one and only one PAN (Personal Area Network) at any given time. MKW2xDxxxV represents a
high-performance SoC that includes hardware support for a device to reside in two networks
simultaneously. In optional Dual PAN mode, the device alternates between the two (2) PANs under
hardware or software control. Hardware support for Dual PAN operation consists of two (2) sets of PAN
and IEEE addresses for the device, two (2) different channels (one for each PAN), a programmable timer
to automatically switch PANs (including on-the-fly channel changing) without software intervention.
There are control bits to configure and enable Dual PAN mode and read only bits to monitor status in Dual
PAN mode. A device can be configured to be a PAN coordinator on either network, both networks, or
neither.
For the purpose of defining PAN in the content of Dual PAN mode, two (2) sets of network parameters are
maintained, PAN0 and PAN1. PAN0 and PAN1 will be used to refer to the two (2) PANs where each
parameter set uniquely identifies a PAN for Dual PAN mode. These parameters are described in Table 2.