User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
Freescale Semiconductor 11
During device initialization if Dual PAN mode is used, software will program both parameter sets to
configure the hardware for operation on two (2) networks.
4 System and power management
The MKW2xDxxxV is a low power device that also supports extensive system control and power
management modes to maximize battery life and provide system protection.
4.1 Modes of operation
The transceiver modes of operation include:
• Idle mode
• Doze mode
• Low power (LP) / hibernate mode
• Reset / powerdown mode
• Run mode
4.2 Power management
The MKW2xDxxxV power management is controlled through programming the modes of operation.
Different modes allow for different levels of power-down and RUN operation. For the receiver,
programmable power modes available are:
• Receiver modes of operation:
— RX preamble search
— RX Preamble search sniff
— X FAD Preamble search
— RX packet decoding
• The RF section of the radio only powered-up as required to do a TX, RX, or CCA/ED operation.
Table 2. PAN0 and PAN1 descriptions
PAN0 PAN1
Channel0 (PHY_INT0, PHY_FRAC0) Channel1 (PHY_INT1, PHY_FRAC1)
MacPANID0 (16-bit register) MacPANID1 (16-bit register)
MacShortAddrs0 (16-bit register) MacShortAddrs1 (16-bit register)
MacLongAddrs0 (64-bit registers) MacLongAddrs1 (64-bit registers)
PANCORDNTR0 (1-bit register) PANCORDNTR1 (1-bit register)