User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
12 Freescale Semiconductor
5 Radio Peripherals
The MKW2xDxxxV provides a set of I/O pins useful for suppling a system clock to the MCU, controlling
external RF modules/circuitry, and GPIO. In addition, there is a special option for streaming the digital
packet data for external monitoring (BSM).
5.1 Clock output (CLK_OUT)
MKW2xDxxxV integrates a programmable clock to source numerous frequencies for connection with
various MCUs. Package pin 39 can be used to provide this clock source as required allowing the user to
make adjustments per their application requirement.
The transceiver CLK_OUT pin is internally connected to the MCU EXTAL pin so that no external
connection is needed to drive the MCU clock.
Care must be taken that the clock output signal does not “talk” or interfere with the reference oscillator or
the radio. Additional functionality this feature supports is:
• 3 clock domains (XTAL, SCLK, SDM_CK).
• Built in synchronization at all clock domain crossings.
• Aggressive clock gating in the XTAL domain to minimize dynamic current consumption based on
the power mode selected.
• XTAL domain can be completely gated off (hibernate mode)
• SPI communication allowed in hibernate
• Single-clock domain in scan mode
Table 3. CLK_OUT table
There is an enable and disable bit for CLK_OUT. When disabling, the clock output will optionally
continue to run for 128 clock cycles after disablement. There will also be one (1) bit available to adjust the
CLK_OUT I/O pad drive strength.
5.2 Bit streaming mode (BSM)
Another peripheral option is bit streaming mode that when activated allows all 802.15.4 packet data,
received or transmitted, to be serialized and shifted out to external hardware for further processing. A
simple development system can be crafted to consume the BSM outputs and generate packet trace data for
CLK_OUT_DIV [2:0] CLK_OUT frequency Comments
032 MHz
116 MHz
28 MHz
3 4 MHz DEFAULT if GPIO5/BOPT=0
42 MHz
51 MHz
6 62.5 kHz
7 32.786 kHz DEFAULT if GPIO5/BOPT=1