User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
Freescale Semiconductor 13
all 802.15.4 traffic appearing on a network within the range of the MKW2xDxxxV device allowing for
PAN-level monitoring and debugging.
BSM uses a simple synchronous 3-wire interface consisting of BSM_CLK, BSM_DATA, and BSM_
FRAME outputs. Packet data is shifted out serially at the 802.15.4 bit rate (250 kHz). Signaling is provided
on BSM_FRAME to indicate start-of-packet and end-of-packet and to discriminate between TX and RX
packet types. BSM_DATA and BSM_FRAME are synchronous to BSM_CLK. BSM_DATA and BSM_
FRAME are shifted out on the falling BSM_CLK and intended to be captured on rising BSM_CLK.
A single shift register control bit activates or deactivates BSM. Aside from controlling this bit, BSM
requires no software support while the mode is engaged. BSM outputs are multiplexed with GPIO, so that
the pins are available for general-purpose use when BSM is disabled. BSM does not interfere with packet
processing or transmit data handling in any way, it is merely a monitoring tool. BSM when engaged will
not measurably increase current consumption because the hardware (including the external I/O) operates
at the 250 kHz rate.
5.3 General-purpose input output (GPIO)
MKW2xDxxxV embedded transceiver supports up to 8 GPIO pins where all I/O pins will have the same
supply voltage, which depending on the battery can vary from 1.8 V up to 3.6 V. Not all 8 are available on
the MKW2xDxxxV. When a die pin is configured as a general-purpose output or for peripheral use, there
will be specific settings required per use case. Pin configuration will be executed by software to adjust
input/output direction and drive strength, capability. When a die pin is configured as a general-purpose
input or for peripheral use, software (see Table 4) can enable a pull-up or pull-down device. Immediately
after reset, all pins are configured as high-impedance general-purpose inputs with “internal pull-up or
pull-down devices enabled”.
Features for these pins include:
• Programmable output drive strength
• Programmable output slew rate
• Hi-Z mode
• Programmable as outputs or inputs (default)
• Pins shared with BSM mode outputs