User Manual

MKW2xDxxxV Product Electrical Specification, Rev. 0.1
14 Freescale Semiconductor
5.3.1 Serial peripheral interface (SPI)
MKW2xDxxxV’s SPI interface allows an MCU to communicate with MKW2xDxxxV’s register set and
packet buffer. The SPI is a slave-only interface; the MCU must drive R_SSEL_B, R_SCLK and R_MOSI.
Write and read access to both direct and indirect registers is supported, and transfer length can be
single-byte, or bursts of unlimited length. Write and read access to the Packet buffer can also be
single-byte, or a burst mode of unlimited length. The SPI interface is asynchronous to the rest of the IC.
No relationship between R_SCLK and MKW2xDxxxV’s internal oscillator is assumed. And no
relationship between R_SCLK and the CLK_OUT pin is assumed. All synchronization of the SPI interface
to the IC takes place inside the SPI module. SPI synchronization takes place in both directions: SPI-to-IC
(register writes), and IC-to-SPI (register reads). The SPI is capable of operation in all power modes, except
Reset. Operation in hibernate mode allows most MKW2xDxxxV registers and the complete packet buffer
to be accessed in the lowest-power operating state enabling minimal power consumption, especially during
the register-initialization phase of the IC. The SPI design features a compact, single-byte control word,
reducing SPI access latency to a minimum. Most SPI access types require only a single-byte control word,
with the address embedded in the control word. During control word transfer (the first byte of any SPI
access), the contents of the IRQSTS1 register (MKW2xDxxxV’s highest-priority status register) are
Table 4. Pin configuration summary
Pin function configuration Details
Tolerance
Units
Min. Typ. Max.
I/O buffer full drive mode
1
1
For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.
Source or sink
— 10 — mA
I/O buffer partial drive mode
2
2
For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.
Source or sink
— 2—mA
I/O buffer high impedance
3
3
Leakage current applies for the full range of possible input voltage conditions.
Off state — — 10 nA
No slew, full drive
Rise and fall time
4
4
Rise and fall time values in reference to 20% and 80%
246ns
No slew, partial drive
Rise and fall time
246ns
Slew, full drive
Rise and fall time
61224ns
Slew, partial drive
Rise and fall time
61224ns
Propagation delay
5
, no slew
5
Propagation Delay measured from/to 50% voltage point.
Full drive
6
6
Full drive values provided are in reference to a 75 pF load.
——11ns
Propagation delay, no slew
Partial drive
7
7
Partial drive values provided are in reference to a 15 pF load.
——11ns
Propagation delay, slew
Full drive
— — 50 ns
Propagation delay, slew
Partial drive
— — 50 ns