User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
Freescale Semiconductor 15
always shifted out, so that the MCU gets access to IRQSTS1, with the minimum possible latency, on every
SPI access.
5.3.1.1 Features
• 4-wire industry standard interface, supported by all MCUs
• SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses).
• SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses).
• Write and read access to all Coconino registers (direct and indirect)
• Write and read access to packet buffer
• SPI accesses can be single-byte or burst.
• Automatic address auto-incrementing for burst accesses
• The entire packet buffer can be uploaded or downloaded in a single SPI burst.
• Entire packet buffer, and most registers, can be accessed in hibernate mode
• Built-in synchronization inside the SPI module to/from the rest of the IC.
• R_MISO can be tristated when SPI inactive, enabling multi-slave configurations
5.3.2 Antenna diversity
To improve the reliability of RF connectivity to long range applications, the antenna diversity feature is
supported without using the MCU through use of four dedicated control pins (package pins 44, 45, 46, and
47) by direct register antenna selection. The digital regulator supplies bias to analog switches that can be
programmed to sink and source current or operate in a high impedance mode.
Fast antenna diversity (FAD) mode supports this radio feature and, when enabled, will allow the choice of
selection between two antennas during the preamble phase. By continually monitoring the received signal,
the FAD block will select the first antenna on which the received signal has a correlation factor above a
predefined progammable threshold. The FAD accomplishes the antenna selection by sequentially
switching between the two antennas testing for the presence of a suitably strong signals/symbols where the
first antenna to reach this condition is then selected for the reception of the packet.
The first antenna is monitored for a period equal to 1 symbol, t
s
= 16 s, then antenna monitoring is
switched to the second antenna, t
a
= 8 s. The period t
a
is required to allow for the external module control
circuitry to turn on/off to select the antenna. t
s
+ t
a
= 24 s that will allow enough time to test both antennas
within the first 4 preamble symbols, t
fad
= 3 x t
a
+ 2 x t
s
= 56 s, thus t
fad
< 4 x t
s
< 64 s. Operationally,
FAD will continue to switch between the two antennas until one is found that has a sufficiently strong
detected signal. FAD’s operation covers less than four s0 symbols before the antenna that is selected
allowing the symbol demodulator to detect at least four s0 symbols before declaring “Preamble Detect”.
6 MKW2xDxxxV operating modes
The radio has these 6 operating modes:
• Reset / power down
• Low power (LP) / hibernate