User Manual

MKW2xDxxxV Product Electrical Specification, Rev. 0.1
Freescale Semiconductor 69
9.2.1 SPI timing: R_SSEL_B to R_SCLK
The following diagram describes timing constraints that must be guaranteed by the system designer.
Figure 24. SPI timing: R_SSEL_B to R_SCLK
t
CSC
(CS-to-SCK delay): 31.25 ns
t
ASC
(After SCK delay): 31.25 ns
t
DT
(Minimum CS idle time): 62.5 ns
t
CKH
(Minimum R_SCLK high time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)
t
CKL
(Minimum R_SCLK low time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)
NOTE
The SPI master device deasserts R_SSEL_B only on byte boundaries, and
only after guaranteeing the t
ASC
constraint shown above.
9.2.2 SPI timing: R_SCLK to R_MOSI and R_MISO
The following diagram describes timing constraints that must be guaranteed by the system designer. These
constraints apply to the Master SPI (R_MOSI), and are guaranteed by the radio SPI (R_MISO).
Figure 25. SPI timing: R_SCLK to R_MOSI and R_MISO
t
DSU
(data-to-SCK setup): 10 ns
t
DH
(SCK-to-data hold): 10 ns
R_SSEL_B
R_SCLK
t
CSC
t
ASC
t
DT
t
CKL
t
CKH
R_SCLK
t
DSU
t
DH
R_MOSI
R_MISO