User Manual
Table Of Contents
- 1 Introduction
- 2 Features
- 3 Transceiver description
- 4 System and power management
- 5 Radio Peripherals
- 6 MKW2xDxxxV operating modes
- 7 MKW2xDxxxV electrical characteristics
- 8 MCU Electrical characteristics
- 8.1 Maximum ratings
- 8.2 General
- 8.3 LVD and POR operating requirements
- 8.4 Switching specification
- 8.5 Core modules
- 8.6 Clock modules
- 8.7 Memories and memory interfaces
- 8.8 Analog
- 8.9 Communication interfaces
- 8.9.1 USB electrical specifications
- 8.9.2 USB DCD electrical specifications
- 8.9.3 VREG electrical specifications
- 8.9.4 DSPI switching specifications (limited voltate range)
- 8.9.5 DSPI switching specification (full voltage range)
- 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range
- 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range
- 9 Transceiver electrical characteristics
- 10 Crystal oscillator reference frequency
- 11 Pin assignments
- 12 Packaging information
MKW2xDxxxV Product Electrical Specification, Rev. 0.1
Freescale Semiconductor 9
3.3.3.4 Energy detection (ED)
Energy detection (ED) is based on receiver signal strength indicator (RSSI) and correlator output for the
802.15.4 standard. energy detect (ED) is an average value of signal strength. The magnitude from this
measurement is calculated from the digital RSSI value that is averaged over an 128 s duration.
3.3.3.5 Link quality indicator (LQI)
Link quality indicator (LQI), is based on receiver signal strength indicator (RSSI) or correlator output for
the 802.15.4 standard. In this mode, RSSI measurement is done during normal packet reception. LQI
computations for MKW2xDxxxV are based on either digital RSSI or correlator peak values. This setting
is executed through a register bit where the final LQI value is available 64 s after preamble is detected.
If a continuous update of LQI based on RSSI throughout the packet is desired, it can be read in a separate
8-bit register by enabling continuous update in a register bit.
3.3.4 Packet processor
The MKW2xDxxxV packet processor performs sophisticated hardware filtering of the incoming received
packet, to determine whether the packet is both PHY- and MAC-compliant, whether the packet is
addressed to this device, and if the device is a PAN coordinator, whether a message is pending for the
sending device. The packet processor greatly reduces the packet filtering burden on software, allowing
software to tend to higher-layer tasks with a lower latency and smaller software footprint.
3.3.4.1 Features
• Aggressive packet filtering to enable long, uninterrupted MCU sleep periods
• Fully compliant with both 2003 and 2006 versions of the 802.15.4 wireless standard
• Supports all frame types, including reserved types
• Supports all valid 802.15.4 frame lengths
• Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame control field and
sequence number
• Supports all source and destination address modes, and also PAN ID compression
• Supports broadcast address for PAN ID and short address mode
• Supports “promiscuous” mode, to receive all packets regardless of address- and rules-checking
• Allows frame type-specific filtering (e.g., reject all but beacon frames)
• Supports SLOTTED and non-SLOTTED modes
• Includes special filtering rules for PAN coordinator devices
• Enables minimum-turnaround Tx-acknowledge frames for data-polling requests by automatically
determining message-pending status
• Assists MCU in locating pending messages in its indirect queue for data-polling end devices
• Makes available to MCU detailed status of frames that fail address- or rules-checking.
• Supports Dual PAN mode, allowing the device to exist on 2 PAN’s simultaneously
• Supports 2 IEEE addresses for the device