User's Manual
Table Of Contents
- About This Document
- Table Index
- Figure Index
- 1 Introduction
- 2 Product Concept
- 2.1 General Description
- 1.1 Simplified Block Diagram
- 1.2 Features and Application
- 1.3 Evaluation Board
- 1.4 List of Applicable FCC Rules
- 1.5 The Specific Operational Use Conditions
- 1.6 Limited Module Procedures
- 1.7 Trace Antenna Designs
- 1.8 Antennas
- 1.9 Label and Compliance Information
- 1.10 Information on Test Modes and Additional Testing R
- 2 Pin Definitions
- 3 Technical Specifications
- 4 Application Interface
- 5 Application Function
- 6 Data Business
- 7 Mechanical Dimensions
- 8 Appendix
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Figure 5- 7 SPI connection
After the module detects that the SPI_NSS pin is pulled low, it wakes up from sleep mode (if
in sleep mode) and begins to initialize the SPI peripherals. The peripheral controller must
wait until the BUSY pin is pulled low to start the transmission.The module will pull the BUSY
pin high again before the current byte transfer is completed. After the module receives a
byte of data and stores the data in the receive buffer it pulls the BUSY pin low again. The
peripheral controller must wait until BUSY is pulled low before transmitting the next byte. The
transmission timing is shown below:
Figure 5- 8 SPI communication timing diagram
4.3.3 Communication Port Selection
By default, the UART interface is used as a communication interface with the user's external
host. The UART interface is forced to open when the module is powered on or reset. When
both UART and SPI interfaces are enabled, the module can adaptively switch the interface
according to user input.