User's Manual
Table Of Contents
- QUICK REFERENCE
- CHAPTER 1 INTRODUCTION
- CHAPTER 2 SETTING UP
- CHAPTER 3 PAPER HANDLING
- CHAPTER 4 PRINTING
- CHAPTER 5 USING SETUP MODE
- HOW TO USE THIS CHAPTER
- ENTERING SETUP MODE
- OVERVIEW OF SETUP MODE
- PRINTING A LIST OF SELECTED OPTIONS
- DECIDING WHICH OPTIONS TO CHANGE
- CHANGING MENU1 AND MENU2 OPTIONS
- CHANGING HARDWARE OPTIONS
- CHANGING PRINT POSITION ADJUSTMENT OPTIONS
- CHANGING CONFIGURATION OPTIONS
- EXITING AND SAVING
- RESETTING DEFAULTS
- USING THE DIAGNOSTIC FUNCTIONS
- SETUP MODE REFERENCE
- ONLINE SETUP MODE
- CHAPTER 6 MAINTENANCE
- CHAPTER 7 TROUBLE-SHOOTING
- APPENDIX A SUPPLIES AND OPTIONS
- APPENDIX B PRINTER AND PAPER SPECIFICATIONS
- CHAPTER C COMMAND SETS
- APPENDIX D INTERFACE INFORMATION
- APPENDIX E CHARACTER SETS
- CHARACTER SETS 1 AND 2 (DPL24C PLUS AND IBM XL24E EMULATION)
- ITALIC AND GRAPHICS CHARACTER SETS (ESC/P2 EMULATION)
- NATIONAL CHARACTER SETS (ALL EMULATIONS)
- NATIONAL CHARACTER SETS (DPL24C PLUS AND IBM XL24E EMULATION)
- NATIONAL CHARACTER SETS (ESC/P2 EMULATION)
- NATIONAL CHARACTER SETS AND SUPPORTED RESIDENT FONTS (ALL EMULATIONS)
- APPENDIX F RESIDENT FONTS
- GLOSSARY OF TERMS
Interface
D-5
User's Manual
INTERFACE INFORMATION
Nibble Mode
Pin numbers 2 to 9, 15 to 31, and 33 to 35 are the same as the conventional
mode.
Pin Return Signal Direc- Description
No. Pin No. name tion
1 19 Host Clock Input This signal is set high when the
host requests the reverse data
transfer phase (nibble mode).
10 28 Printer Clock Output Reverse data transfer phase:
This signal goes high when data
being sent to the host is
established.
Reverse idle phase:
This signal is set low then goes
high to interrupt the host,
indicating that data is available.
11 29 Printer Busy Output Reverse data transfer phase:
Data bit 3, data bit 7, then
forward path (host to printer)
busy status
12 30 Ack Data Req Output Reverse data transfer phase:
Data bit 2, then data bit 6
Reverse idle phase:
This signal is set high until the
host requests data and, after that,
follows the
Data Available
signal.
13 – X Flag Output Reverse data transfer phase:
Data bit 1, then data bit 5