Quad-Core Intel® Xeon® Processor 5300 Series Datasheet September 2007 Order Number: 315569-003
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Contents 1 Introduction............................................................................................................... 11 1.1 Terminology ..................................................................................................... 13 1.2 State of Data .................................................................................................... 15 1.3 References .......................................................................................................
6.3 6.4 Processor Thermal Features ................................................................................ 98 6.3.1 Thermal Monitor Features........................................................................ 98 6.3.2 Thermal Monitor (TM1) ........................................................................... 98 6.3.3 Thermal Monitor 2 .................................................................................. 99 6.3.4 On-Demand Mode ...............................................
2-10 Quad-Core Intel® Xeon® Processor X5365 Series VCC Static and Transient Tolerance Load Lines ........................................................................... 39 2-11 Quad-Core Intel® Xeon® Processor L5318 VCC Static and Transient Tolerance Load Lines ........................................................................... 41 2-12 VCC Overshoot Example Waveform...................................................................... 43 2-13 Electrical Test Circuit .............................
2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 8-1 8-2 8-3 6 Signal Reference Voltages .................................................................................. 25 PECI DC Electrical Limits .................................................................................... 26 Processor Absolute Maximum Ratings...................................................................
Revision History Revision 001 Description Date Initial Release November 2006 002 Added Quad-Core Intel® Xeon® Processor L5300 Series 003 Included the G-step information. Added the Quad-Core Intel® Xeon® Processor L5318.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Introduction 1 Introduction The Quad-Core Intel® Xeon® Processor 5300 Series are 64-bit server/workstation processors utilizing four Intel Core™ microarchitecture cores. These processors are based on Intel’s 65 nanometer process technology combining high performance with the power efficiencies of low-power Intel Core™ microarchitecture cores. The QuadCore Intel® Xeon® Processor 5300 Series consists of two die, each containing two processor cores.
Introduction Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/vt. The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance server and workstation systems. The processors support a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction • LGA771 socket – The Quad-Core Intel® Xeon® Processor 5300 Series interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket. • Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the processor die.
Introduction • Intel® Virtualization Technology (Intel® VT) – Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. • VRM (Voltage Regulator Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits.
Introduction Document Number1 Document Notes Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines Clovertown Processor Boundary Scan Descriptive Language (BSDL) Model Debug Port Design Guide for UP/DP Systems 10 1 Notes: Contact your Intel representative for the latest revision of these documents.
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® Xeon® Processor 5300 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 VCC (power) and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions.
Electrical Specifications 2.3.3 Front Side Bus AGTL+ Decoupling The processor integrates signal termination on the die, as well as a portion of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation.
Electrical Specifications Table 2-1. Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Multiplier Core Frequency with 333.333 MHz Bus Clock Core Frequency with 266.666 MHz Bus Clock Notes 1/6 2 GHz 1.60 GHz 1, 2, 3, 4 1/7 2.33 GHz 1.86 GHz 1, 2, 3 1/8 2.66 GHz 2.13 GHz 1, 2, 3 1/9 3 GHz 2.40 GHz 1, 2, 3 1/10 3.33 GHz 2.66 GHz 1, 2, 3 1/11 3.66 GHz 2.93 GHz 1, 2, 3 1/12 4 GHz 3.20 GHz 1, 2, 3 Notes: 1.
Electrical Specifications 2.4.2 PLL Power Supply An on-die PLL filter solution is implemented on the processor. The VCCPLL input is used to provide power to the on chip PLL of the processor. Please refer to Table 2-12 for DC specifications. Refer to the appropriate platform design guidelines for decoupling and routing guidelines. 2.
Electrical Specifications Table 2-3. HEX VID6 400 mV Voltage Identification Definition VID5 200 mV VID4 100 mV VID3 50 mV VID2 25 mV VID1 12.5 mV VCC_MAX HEX VID6 400 mV VID5 200 mV VID4 100 mV VID3 50 mV VID2 25 mV VID1 12.5 mV VCC_MAX 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.
Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 0 0 Reserved 0 1 Dual-Core Intel® Xeon® Processor 5000 Series Dual-Core Intel® Xeon® Processor 5100 Series 1 0 Reserved 1 1 Quad-Core Intel® Xeon® Processor 5300 Series Note: Table 2-5. The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor.
Electrical Specifications 2.7 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Electrical Specifications Table 2-6.
Electrical Specifications Note: 1. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series NDA Specification Update. 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers.
Electrical Specifications Table 2-10. PECI DC Electrical Limits (Sheet 2 of 2) Symbol Notes1 Definition and Conditions Min Max Units Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V Isource High level output source -6.0 N/A mA 0.5 1.0 mA N/A 50 µA 2 N/A 10 µA 2 Bus capacitance per node N/A 10 pF 3 Signal noise immunity above 300 MHz 0.1 * VTT N/A Vp-p (VOH = 0.75 * VTT) Low level output sink Isink (VOL = 0.
Electrical Specifications Note: Processors within a system must operate at the same frequency per bits [12:8] of the CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep® Technology transitions, or assertion of the FORCEPR# signal. Not all operating systems can support dual processors with mixed frequencies. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported.
Electrical Specifications 2.13 Processor DC Specifications The processor DC specifications in this section are defined at the processor die (pads) unless noted otherwise. See Table 4-1 for the Quad-Core Intel® Xeon® Processor 5300 Series land listings and Table 5-1 for signal definitions. Voltage and current specifications are detailed in Table 2-12. For platform planning refer to Table 2-13, which provides VCC Static and Transient Tolerances.
Electrical Specifications Table 2-12.
Electrical Specifications Table 2-12.
Electrical Specifications Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. 16. ICC_VTT_OUT is specified at 1.2 V. 17. ICC_RESET is specified while PWRGOOD and RESET# are asserted. Refer to Table 2-26 for the PWRGOOD to RESET# de-assertion time specification and Table 2-23 for the RESET# Pulse Width specification . Figure 2-2.
Electrical Specifications Figure 2-4. Quad-Core Intel® Xeon® Processor X5365 Series Load Current versus Time Sustained Current (A) 160 155 150 145 140 135 130 125 120 0.01 0.1 1 10 100 1000 Time Duration (s) Notes: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Figure 2-5.
Electrical Specifications 2. Figure 2-6. Not 100% tested. Specified by design characterization. Quad-Core Intel® Xeon® Processor L5318 Load Current versus Time Notes: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-13.
Electrical Specifications Table 2-13. VCC Static and Transient Tolerance for Quad-Core Intel® Xeon® Processor E5300 Series, Quad-Core Intel® Xeon® Processor X5300 Series, Quad-Core Intel® Xeon® Processor L5300 Series (Sheet 2 of 2) ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 90 VID - 0.113 VID - 0.128 VID - 0.143 1, 2, 3, 4 95 VID - 0.119 VID - 0.134 VID - 0.149 1, 2, 3, 4 100 VID - 0.125 VID - 0.140 VID - 0.155 1, 2, 3, 4 105 VID - 0.131 VID - 0.146 VID - 0.
Electrical Specifications 4. Figure 2-8. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.
Electrical Specifications Figure 2-9. Quad-Core Intel® Xeon® Processor L5300 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 VID - 0.000 VID - 0.010 VCC Maximum VID - 0.020 VID - 0.030 Vcc [V] VID - 0.040 VID - 0.050 VID - 0.060 VID - 0.070 VCC Typical VID - 0.080 VID - 0.090 VCC Minimum VID - 0.100 Notes: 1. 2. 3. 4. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.
Electrical Specifications Table 2-14. VCC Static and Transient Tolerance for Quad-Core Intel® Xeon® Processor X5365 Series (Sheet 2 of 2) ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 50 VID - 0.063 VID - 0.073 VID - 0.083 1,2,3 55 VID - 0.069 VID - 0.079 VID - 0.089 1,2,3 60 VID - 0.075 VID - 0.085 VID - 0.095 1,2,3 65 VID - 0.081 VID - 0.091 VID - 0.101 1,2,3 70 VID - 0.087 VID - 0.097 VID - 0.108 1,2,3 75 VID - 0.094 VID - 0.104 VID - 0.114 1,2,3 80 VID - 0.
Electrical Specifications Figure 2-10. Quad-Core Intel® Xeon® Processor X5365 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID - 0.000 VCC Maximum VID - 0.050 Vcc [V] VID - 0.100 VID - 0.150 VCC Typical VID - 0.200 VCC Minimum VID - 0.250 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.
Electrical Specifications Table 2-15. VCC Static and Transient Tolerance for Quad-Core Intel® Xeon® Processor L5318 Series ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.015 VID - 0.030 1,2,3 5 VID - 0.005 VID - 0.020 VID - 0.035 1,2,3 10 VID - 0.010 VID - 0.025 VID - 0.040 1,2,3 15 VID - 0.015 VID - 0.030 VID - 0.045 1,2,3 20 VID - 0.020 VID - 0.035 VID - 0.050 1,2,3 25 VID - 0.025 VID - 0.040 VID - 0.055 1,2,3 30 VID - 0.030 VID - 0.
Electrical Specifications Figure 2-11. Quad-Core Intel® Xeon® Processor L5318 VCC Static and Transient Tolerance Load Lines Notes: 1. 2. 3. 4. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.2 for VCC overshoot specifications. Refer to Table 2-12 for processor VID information. Refer to Table 2-15 for VCCStatic and Transient Tolerance.
Electrical Specifications 6. 7. 8. GTLREF should be generated from VTT with a 1% tolerance resistor divider. The VTT referred to in these specifications is the instantaneous VTT. Specified when on-die RTT and RON are turned off. VIN between 0 and VTT. This is the measurement at the pin. Table 2-17. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage -0.10 0.00 0.3*VTT V 2,3 VIH Input High Voltage 0.
Electrical Specifications Figure 2-12. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.13.
Electrical Specifications Table 2-20. AGTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Unit Notes1 GTLREF_DATA_MID GTLREF_DATA_END Data Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 GTLREF_ADD_MID GTLREF_ADD_END Address Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 RTT Termination Resistance (pull up) 45 50 55 Ω 4 COMP Resistance 49.4 49.9 50.4 Ω 5 COMP Note: 1.
Electrical Specifications 7. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 8. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 9. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 10.
Electrical Specifications Figure 2-15. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-16. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.
Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5300 Series are packaged in a Flip Chip Land Grid Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The package consists of two processor dies mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Mechanical Specifications Figure 3-2. Note: 48 Processor Package Drawing (Sheet 1 of 3) Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
Mechanical Specifications Figure 3-3.
Mechanical Specifications Figure 3-4.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear 311 70 N lbf 1,4,5 Tensile 111 25 N lbf 2,4,5 Torque 3.95 35 N-m LBF-in 3,4,5 Notes: 1.
Mechanical Specifications 3.8 Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram aids in the identification of the Quad-Core Intel® Xeon® Processor 5300 Series. Figure 3-5. Processor Top-side Markings (Example) GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 LOT ATPO NO S/N S/N Legend: Mark Text (Production Mark): GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 2.
Mechanical Specifications Figure 3-6.
Mechanical Specifications Figure 3-7.
Mechanical Specifications 56 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Land Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 23) Pin Name Pin No. Signal Buffer Type Direction Table 4-1.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 3 of 23) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 4 of 23) Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 5 of 23) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 6 of 23) Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 7 of 23) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 8 of 23) Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 10 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 11 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 12 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 14 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 16 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 18 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 19 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 20 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 21 of 23) Pin Name Pin No. Signal Buffer Type Table 4-1. Land Listing by Land Name (Sheet 22 of 23) Direction Pin Name Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 23 of 23) Pin Name Pin No.
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. A10 Pin Name D08# Signal Buffer Type Source Sync Direction Table 4-2. Land Listing by Land Number (Sheet 2 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 3 of 20) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 4 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 5 of 20) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 6 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 7 of 20) Pin No. AJ8 Pin Name Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 8 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 9 of 20) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 10 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 11 of 20) Pin No. Pin Name Signal Buffer Type C20 DBI3# C21 C22 C23 RESERVED C24 VSS Power/Other C25 VTT C26 VTT C27 C28 Direction Table 4-2. Land Listing by Land Number (Sheet 12 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 13 of 20) Pin No. F11 Pin Name D23# Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 14 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 15 of 20) Pin No. Pin Name Signal Buffer Type Direction H29 VSS Power/Other H3 VSS Power/Other H30 BSEL1 CMOS Asynchronous Output H4 RSP# Common Clk H5 BR1# Common Clk H6 VSS H7 VSS H8 H9 Table 4-2. Land Listing by Land Number (Sheet 16 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 17 of 20) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 18 of 20) Pin No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 19 of 20) Pin No. Pin Name Signal Buffer Type Table 4-2. Land Listing by Land Number (Sheet 20 of 20) Pin No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 7) Name Description Notes I/O A[37:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In subphase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]#4 are protected by parity signals AP[1:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 2 of 7) Type Description Notes BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 7.
Signal Definitions Table 5-1. Name D[63:0]# Signal Definitions (Sheet 3 of 7) Type Description Notes I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. 3 D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 7) Name DSTBN[3:0]# DSTBP[3:0]# Type I/O I/O Description Data strobe used to latch in D[63:0]#. Signals Associated Strobes D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 5 of 7) Type Description Notes IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 6 of 7) Type Description Notes PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 7) Name TESTIN1 TESTIN2 THERMTRIP# Type I I Description Notes Connect the TESTIN1 and TESTIN2 signals together, then terminate the net with a 51 Ω resistor to VTT. O Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor.
Signal Definitions 86 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5300 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications power-intensive applications. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelinesfor details on system thermal solution design, thermal profiles and environmental considerations. For the Quad-Core Intel® Xeon® Processor X5300 Series, Intel has developed two thermal profiles, either of which can be implemented. Both ensure adherence to Intel reliability requirements.
Thermal Specifications To provide greater flexibility in environmental conditions and thermal solution design, the Nominal Thermal Profile and the Short-Term Thermal Profile are each specified 5°C above the NEBS Level 3 ambient operating temperature requirements of 40°C nominal and 55°C short-term. The Nominal Thermal Profile is defined at an ambient operating temperature of 45°C, and the Short-Term Thermal Profile is defined at an ambient operating temperature of 60°C.
Thermal Specifications Figure 6-1.Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile 70 65 Thermal Profile Y = 0.293*x + 42.6 Tcase [C] 60 55 50 45 40 0 10 20 30 40 50 60 70 80 Power [W] Notes: 1. Please refer to Table 6-2 for discrete points that constitute the thermal profile. 2. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. Table 6-2.
Thermal Specifications Table 6-3. Quad-Core Intel® Xeon® Processor X5300 Series Thermal Specifications Core Frequency Launch to FMB Maximum Power (W) Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 145 120 5 See Figure 6-2; Table 6-4; Table 6-5 Notes 1, 2, 3, 4, 5, 6 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications Table 6-4. Table 6-5. 92 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile A Table Power (W) TCASE_MAX (° C) P_PROFILE_MIN_A=43.9 50.0 45 50.2 50 51.1 55 51.9 60 52.8 65 53.6 70 54.5 75 55.3 80 56.2 85 57.0 90 57.9 95 58.7 100 59.6 105 60.5 110 61.3 115 62.2 120 63.0 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile B Table Power (W) TCASE_MAX (° C) P_PROFILE_MIN_B=30.8 50.0 35 50.9 40 52.1 45 53.2 50 54.
Thermal Specifications Table 6-6. Quad-Core Intel® Xeon® Processor X5365 Series Thermal Specifications Core Frequency Launch to FMB Maximum Power (W) Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 180 150 5 See Figure 6-3; Table 6-7 Notes 1, 2, 3, 4, 5, 6 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications Table 6-7. Table 6-8. Quad-Core Intel® Xeon® Processor X5365 Series Thermal Profile (Sheet 1 of 2) Power (W) TCASE_MAX (° C) P_PROFILE_MIN=50 44.3 55 45.3 60 46.2 65 47.1 70 48.1 75 49.0 80 49.9 85 50.9 90 51.8 95 52.7 100 53.7 105 54.6 110 55.5 115 56.5 120 57.4 125 58.3 130 59.3 135 60.2 140 61.1 145 62.1 150 63.
Thermal Specifications Figure 6-4. Quad-Core Intel® Xeon® Processor L5300 Series Thermal Profile 65 60 Thermal Profile 55 Tcase [C] Y = 0.360*x + 42.0 50 45 40 0 10 20 30 40 50 Pow er [W] Notes: 1. Please refer to Table 6-9 for discrete points that constitute the thermal profile. 2. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. 6.2 Table 6-9.
Thermal Specifications 3. 4. 5. 6. Figure 6-5. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. These specifications are based on silicon characterization. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® Processor L5300 Series may be shipped under multiple VIDs for each frequency.
Thermal Specifications Table 6-11. Quad-Core Intel® Xeon® Processor L5318 Nominal Thermal Profile Power (W) TCASE_MAX (° C) P_PROFILE_MIN=0 45.0 5 48.4 10 51.8 15 55.2 20 58.6 25 62.0 30 65.4 35 68.8 40 72.2 Table 6-12. Quad-Core Intel® Xeon® Processor L5318 Short Term Thermal Profile Power (W) 6.2.1 TCASE_MAX (° C) P_PROFILE_MIN=0 60.0 5 63.4 10 66.8 15 70.2 20 73.6 25 77.0 30 80.4 35 83.8 40 87.
Thermal Specifications temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines Figure 6-6. Case Temperature (TCASE) Measurement Location Note: Figure is not to scale and is for reference only. 6.3 Processor Thermal Features 6.3.
Thermal Specifications configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the TM1 is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning off and on at a duty cycle specific to the processor (typically 30 - 50%).
Thermal Specifications rapidly, on the order of 5 µs. During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator.
Thermal Specifications the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 6.3.
Thermal Specifications 6.3.7 THERMTRIP# Signal Regardless of whether or not TM1 or TM2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 5-1). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 5-1. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.
Thermal Specifications Figure 6-9. Conceptual Fan Control Diagram For A PECI-Based Platform TCONTROL Setting TCC Activation Temperature Max PECI = 0 Fan Speed (RPM) PECI = -10 Min PECI = -20 Temperature (not intended to depict actual implementation) 6.4.1.2 Processor Thermal Data Sample Rate and Filtering The DTS provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals.
Thermal Specifications 6.4.2.2 PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification. Please refer to this document for details on supported PECI command function and codes 6.4.2.3 PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other compatible industry standard interfaces.
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. Quad-Core Intel® Xeon® Processor 5300 Series sample its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states. Refer to the applicable chipset specification and the Conroe and Woodcrest Processor Family BIOS Writer’s Guide for more information. 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. Refer to the Conroe and Woodcrest Processor Family BIOS Writer’s Guide.
Features Table 7-2.
Features Figure 7-1.
Features A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 7.2.4.1). While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state.
Features support this feature will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5300 Series NDA Specification Update when available. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points.
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Quad-Core Intel® Xeon® Processor 5300 Series will be offered as an Intel boxed processor.
Boxed Processor Specifications Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5300 Series 2U Passive Heat Sink Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5300 Series Processor Thermal Solution (Exploded View) Heat sink screws Heat sink screw springs Heat sink Heat sink standoffs Thermal Interface Material Motherboard and processor Protective Tape CEK spring Chassis pan Note: 1.
Boxed Processor Specifications 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor. 8.2.1 Boxed Processor Heat Sink Dimensions (CEK) The boxed processor will be shipped with an unattached thermal solution. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8-4 through Figure 8-8.
Boxed Processor Specifications Figure 8-4.
Boxed Processor Specifications Figure 8-5.
Boxed Processor Specifications Figure 8-6.
Boxed Processor Specifications Figure 8-7.
Boxed Processor Specifications Figure 8-8.
Boxed Processor Specifications Figure 8-9.
Boxed Processor Specifications Figure 8-10.
Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2100 grams total mass in the heat sinks. This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration.
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
Boxed Processor Specifications 8.3.2.1 1U Passive/3U+ Active Combination Heat Sink Solution (1U Rack Passive) In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0.38 in. H2O (25.5 m3/hr at 94.6 Pa) of flow impedance. The duct should be carefully designed to minimize the airflow bypass around the heatsink. It is assumed that a 40°C TLA is met.
Boxed Processor Specifications The other items listed in Figure 8-3 that are required to compete this solution will be shipped with either the chassis or boards.
Debug Tools Specifications 9 Debug Tools Specifications Please refer to the Debug Port Design Guide for UP/DP Systems and the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Quad-Core Intel® Xeon® Processor 5300 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.
