C141-E120-02EN MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL
FOR SAFE OPERATION Handling of This Manual This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Revision History (1/1) Edition Date Revised section (*1) (Added/Deleted/Altered) Details 01 2001-02-28 — — 02 2001-09-03 Table 1.2 Order No. was added. Table 1.3 Current and power dissipation were changed. Table 1.6 Condition and specification were corrected. 1.10 Load/Unload Function "Soft Reset"was deleted. 3-1 page Account was added. 3.1 Dimension Tolerance was corrected. (6)Handling caution 3.2 Recommended equipment were changed. Table 5.3 Command was added.
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Preface This manual describes the MHN Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.
Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly.
Preface Liability Exception “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly. Task Normal Operation Alert message Page Data corruption: Avoid mounting the disk near strong magnetic sources such as loud speakers.
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Manual Organization MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL (C141-E120) • • • • • • Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT • Maintenance and Diagnosis • Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL (C141-E120) C141-E120-02EN vii
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Contents CHAPTER 1 Device Overview........................................................................ 1-1 1.1 Features 1-2 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface 1.2 1-2 1-3 Device Specifications C141-E120-02EN 1-4 1.2.1 Specifications summary 1.2.2 Model and product number 1-4 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1-9 1.8 Error Rate 1-10 1.
Contents CHAPTER 3 Installation Conditions ............................................................. 3-1 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3-9 3.3.1 Device connector 3-9 3.3.2 Cable connector specifications 3.3.3 Device connection 3.3.4 Power supply connector (CN1) 3.4 CHAPTER 4 3-3 Jumper Settings 3-10 3-10 3-11 3-11 3.4.1 Location of setting jumpers 3.4.2 Factory default setting 3.4.3 Master drive-slave drive setting 3.4.
Contents 4.6.2 Write circuit 4-10 4.6.3 Read circuit 4-13 4.6.4 Digital PLL circuit 4.7 CHAPTER 5 4-15 4.7.1 Servo control circuit 4.7.2 Data-surface servo format 4.7.3 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 4-15 4-18 4-20 4-21 4-22 Interface ..................................................................................... 5-1 5.1 Physical Interface 5-2 5.1.1 Interface signals 5-2 5.1.2 Signal assignment on the connector 5.
Contents 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5-100 5-101 5.5.3.3 Pausing an Ultra DMA data in burst 5-101 5.5.3.4 Terminating an Ultra DMA data in burst 5.5.4 Ultra DMA data out commands 5-105 5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4.2 The data out transfer 5-102 5-105 5-105 5.5.4.3 Pausing an Ultra DMA data out burst 5-106 5.5.4.4 Terminating an Ultra DMA data out burst 5.5.5 Ultra DMA CRC rules 5.5.
Contents 6.2 Power Save 6.2.1 Power save mode 6-7 6.2.2 Power commands 6-8 6.3 Defect Management 6-9 6.3.1 Spare area 6.3.2 Alternating defective sectors 6.4 6-9 Read-Ahead Cache Data buffer configuration 6.4.2 Caching operation 6.4.3 Usage of read segment 6-14 6.4.3.2 Sequential read 6-15 6.4.3.3 Full hit (hit all) 6-18 Write Cache 6-12 6-12 6.4.3.1 Mis-hit (no hit) 6.5 6-9 6-11 6.4.1 6.4.3.4 Partially hit Glossary 6-7 6-14 6-19 6-20 .................................
Contents Illustrations Figures xiv Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Disk drive outerview 2-2 Configuration of disk media heads 1 drive system configuration 2-4 2 drives configuration 2-4 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.
Contents Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure 5.14 Figure 5.15 Figure 5.16 Figure 5.17 Figure 5.18 Figure 5.19 Figure 5.20 Figure 5.21 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.
Contents Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 5.9 Table 5.10 Table 5.11 Table 5.12 Table 5.13 Table 5.14 Table 5.15 Table 5.16 Table 5.17 Table 5.18 Table 5.
CHAPTER 1 Device Overview 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects 1.10 Load/Unload Function Overview and features are described in this chapter, and specifications and power requirement are described. The MHN Series are 2.5-inch hard disk drives with built-in disk controllers.
Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the MHN Series are described. (1) Compact The MHN2300AT, MHN2200AT, MHN2150AT and MHN2100AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch). (2) Large capacity The disk drive can record up to 15 GB (formatted) on one disk using the 16/17 MTR recording method and 15 recording zone technology.
1.1 Features 1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller, the disk drives (the MHN Series) can be connected to an ATA interface of a personal computer. (2) 2 MB data buffer The disk drives (the MHN Series) use a 2 MB data buffer to transfer data between the host and the disk media. In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.
Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHN Series). Table 1.1 Specifications (1/2) Format Capacity (*1) Number of Heads MHN2300AT MHN2200AT MHN2150AT MHN2100AT 30 GB 20 GB 15 GB 10 GB 4 3 2 2 29,498,112 19,640,880 Number of Cylinders (User) Number of Sectors (User) Bytes per Sector Recording Method Track Density Bit Density 28,416 58,605,120 39,070,080 512 16/17 MTR 1.98 K track/mm (50,400 TPI) 22.
1.3 Power Requirements Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Table 1.1 Specifications (2/2) Model Capacity No. of Cylinder No. of Heads No. of Sectors MHN2300AT 8.45 GB 16,383 16 63 MHN2200AT 8.45 GB 16,383 16 63 MHN2150AT 8.45 GB 16,383 16 63 MHN2100AT 8.45 GB 16,383 16 63 1.2.2 Model and product number Table 1.2 lists the model names and product numbers of the MHN Series.
Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) MHN Series MHN Series 0.9 A 4.5 W Idle 150 mA 0.75 W R/W (on track) (*2) 500 mA 2.5 W Seek (*5) 500 mA 2.5 W Standby 50 mA 0.25 W Sleep 20 mA 0.1 W — 0.025 W/GB (rank E / MHN2300AT) 0.025 W/GB (rank E / MHN2200AT) 0.050 W/GB (rank D / MHN2150AT) 0.
1.4 Environmental Specifications Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on (5) Power on/off sequence The voltage detector circuits (the MHN Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence. 1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.
Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification Sound Pressure • Idle mode (DRIVE READY) 24 dBA typical at 1 m Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Item Specification Vibration (Swept sine, 1/4 octave per minute) • Operating • Non-operating 5 to 400 Hz, 9.
1.7 Reliability 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time Operating time Power on/off Environment 250H/month or less 3000H/years or less 20% or less of power-on time 1/day or more needed.
Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 1014 bits.
1.7 Reliability Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.
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CHAPTER 2 Device Configuration 2.1 Device Configuration 2.2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. MHN Series Figure 2.1 Disk drive outerview (1) Disk The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The number of disks used varies with the model, as described below.
2.1 Device Configuration Head 3 Head 3 2 2 1 1 0 0 MHN2300AT Head 1 0 MHN2200AT MHN2150AT (Either of head 0 or head 3 is mounted.) MHN2100AT Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.
Device Configuration 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 transfer at 100 MB/s. 2.2.2 1 drive connection MHN2300AT MHN2200AT MHC2032AT MHN2150AT MHC2040AT MHN2100AT Figure 2.3 1 drive system configuration 2.2.
2.2 System Configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-5 interface. At high speed data transfer (PIO mode 4 or DMA mode 2 U-DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
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CHAPTER 3 Installation Conditions 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. 0.25 Figure 3.
3.2 Mounting 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (d) Vertical –2 (c) Vertical –1 gravity (e) Vertical –3 (f) Vertical –4 Figure 3.
Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N·m(5kgf·cm). When attaching the HDD to the system frame, do not allow the system frame to touch parts (cover and base) other than parts to which the HDD is attached.
3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around φ3 to block. Figure 3.
Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.
3.2 Mounting (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields. Damage: Do not press the cover of the disk drive.
Installation Conditions - General notes ESD mat Wrist strap Shock absorbing mat Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically to avoid falling down. Do not drop. Figure 3.7 Handling cautions - Installation (1) Please use the driver of a low impact when you use an electric driver. HDD is occasionally damaged by the impact of the driver.
3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. PCA Connector, setting pins Figure 3.
Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications ATA interface and power supply cable (44-pin type) Name Model Manufacturer Cable socket (44-pin type) 89361-144 BERG IMPORTANT For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.
3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions. Figure 3.
Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. 1 Open A C 1 C A Short Open 2 D B 2 D B Open (a) Master drive (b) Slave drive Figure 3.13 Jumper setting of master or slave drive Note: Pins A and C should be open.
3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open 1 C A 2 D B Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables. By connecting the CSEL of the master drive to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level. The drive is identified as a master drive.
Installation Conditions drive drive Figure 3.
CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on Sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA). The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter.
4.2 Subassemblies Head 3 Head 3 2 2 1 1 0 0 MHN2300AT Head 1 0 MHN2200AT MHN2150AT (Either of head 0 or head 3 is mounted.) MHN2100AT Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm ±1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.
Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.
4.3 Circuit Configuration 5.0V S-DRAM SVC HDIC F-ROM - 3.0V 3.3V 2.5V MCU & HDC RDC Figure 4.
Theory of Device Operation Figure 4.
4.3 Circuit Configuration 4.4 Power-on Sequence Figure 4.4 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor. b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.
Theory of Device Operation Power-on a) Start Self-diagnosis 1 - MPU bus test - Internal register write/read test - Work RAM write/read test The spindle motor starts. b) c) Self-diagnosis 2 - Data buffer write/read test d) Confirming spindle motor speed e) Load the head assembly f) Initial on-track and read out of system information Execute self-calibration Drive ready state (command waiting state) End Figure 4.4 Power-on operation sequence 4.
4.5 Self-calibration The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varying by the cylinder, the disk is divided into 23 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the SA cylinder.
Theory of Device Operation 4.5.3 Command processing during self-calibration If the disk drive receives a command execution request from the host while executing self-calibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration.
4.6 Read/write Circuit Table 4.
Theory of Device Operation HDIC WDX/WDY RDX/RDY SD RDC Write PreCompensation SC SE Serial I/O AGC Amplifier Registers Digital PLL Programmable Filter Flash Digitizer ServoPulse Detector MEEPR Viterbi Detect 16/17 ENDEC Position A/B/C/D (to reg) WTGATE REFCLK RDGATE DATA RWCLK [7:0] SRV_CLK SRV_OUT[1:0] Figure 4.
4.6 Read/write Circuit 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
Theory of Device Operation (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosineequalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.
4.7 Servo Control 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand. 4.7.1 Servo control circuit Figure 4.7 is the block diagram of the servo control circuit.
Theory of Device Operation The major internal operations are listed below. a. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0). c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d.
4.7 Servo Control (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.9 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head. The servo signals do A/D-convert by Fourierdemodulator in the servo burst capture circuit.
Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving. (2) Data area This area is used as the user data area SA area.
4.7 Servo Control Servo frame (120 servo frames per revolution) IGB OGB Data area expand CYLn CYLn + 1 CYLn – 1 (n: even number) Diameter direction W/R Recovery Servo Mark Gray Code W/R Recovery Servo Mark Gray Code W/R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase Circumference Direction Erase: DC erase area PAD Figure 4.
Theory of Device Operation 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code, servo A to D, and PAD. Figure 4.9 shows the servo frame format. Figure 4.
4.7 Servo Control (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and positiondemodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.
Theory of Device Operation d) If the head is stopped at the reference cylinder from there. Track following control starts. (2) Seek operation Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read/write instruction is issued, the MPU seeks the desired track. The MPU feeds the VCM current via the D/A converter and power amplifier to move the head.
4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.
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CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing This chapter gives details about the interface, and the interface commands and timings.
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals.
5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No.
Interface [signal] ENCSEL [I/O] [Description] I This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- I MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting Pin A, B Short: Slave setting RESET- I Reset signal from the host. This signal is low active and is asserted for a minimum of 25 µs during power on.
5.1 Physical Interface [signal] [I/O] [Description] CS0- I Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- I Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers. DA 0-2 I Binary decoded address signals asserted by the host to access task file registers.
Interface [signal] DMARQ [I/O] [Description] O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals. This signal hand shakes with the DMACK-signal.
5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through inputoutput (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers. Table 5.
Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
5.2 Logical Interface [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X’01’ to X’05’).
Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. (7) Cylinder High register (X’1F5’) The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
5.2 Logical Interface (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset. - Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track. In the IDD, this bit is always set to 1 after the spin-up control is completed. - Bit 3: Data Request (DRQ) bit.
5.3 Host Commands 5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written. Table 5.
5.3 Host Commands Table 5.
Interface Y*: Necessary to set parameters under the LBA mode. N: Not necessary to set parameters (The parameter is ignored if it is set.) N*: May set parameters D: The device parameter is valid, and the head parameter is ignored. D*: The command is addressed to the master device, but both the master device and the slave device execute it. X: Do not care 5.3.
5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note: 1.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 0 1F6H(DH) x L x DV 0 0 0 R Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx (R: Retry) At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No.
5.3 Host Commands final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”). If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error. Figure 5.2 shows an example of the execution of the READ MULTIPLE command.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB] 1F2H(SC) 00(*1) 1F1H(ER) Error information *1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) x L x DV 1 0 0 R Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 0 1 0 0 1F6H(DH) x L x DV 0 0 0 R Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No.
5.3 Host Commands If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 1 1F6H(DH) x L x DV 0 0 0 R Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No.
Interface (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command. The DRQ bit of the Status register is required to set only at the start of the data block, not on each sector. The number of sectors per block is defined by a successful SET MULTIPLE MODE command.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) x L x DV 0 1 0 1 Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No.
Interface A host system can select the following transfer mode using the SET FEATURES command. • Multiword DMA transfer mode 0 to 2 • Ultra DMA transfer mode 0 to 5 At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) x L x DV 1 0 1 R Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 1 1F6H(DH) x L x DV 1 1 0 0 Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx x x x x xx At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information DV xx Note: Also executable in LBA mode.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 0 1 1 1 1F6H(DH) x L x DV x x x x Head No. / LBA [MSB] 1F5H(CH) Cylinder No. [MSB] / LBA 1F4H(CL) Cylinder No. [LSB] / LBA 1F3H(SN) Sector No. / LBA [LSB] 1F2H(SC) xx 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x L x DV Head No. / LBA [MSB] 1F5H(CH) Cylinder No. [MSB] / LBA 1F4H(CL) Cylinder No. [LSB] / LBA 1F3H(SN) Sector No.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 0 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) Number of sectors/track 1F1H(FR) xx 0 0 0 1 Max. head No. At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) Number of sectors/track 1F1H(ER) Error information Max. head No.
5.3 Host Commands (13) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx 1 1 0 0 xx At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information DV xx Table 5.
5.3 Host Commands Table 5.
Interface Table 5.
5.3 Host Commands Bit 13: Standby timer value. Factory default is '0.' ATA spec is '1.
Interface Bit 1: 1 = Mode 4 Bit 0: 1 = Mode 3 *9 WORD 80 Bit 15-7: Reserved Bit 6: 1 = ATA/ATAPI-6 supported Bit 5: 1 = ATA/ATAPI-5 supported Bit 4: 1 = ATA/ATAPI-4 supported Bit 3: 1 = ATA-3 supported Bit 2: 1 = ATA-2 supported Bit 1-0: Undefined *10 WORD 82 Bit 15: Undefined Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command. Bit 12: '1' = Supports the WRITE BUFFER command.
5.3 Host Commands Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10: '1' = 48 bit LBA feature set. Bit 9: '1' = Automatic Acoustic Management feature set. Bit 8: '1' = Supports the SET MAX Security extending command. Bit 7: Reserved Bit 6: '1' = When the power is turned on, spin is started by the SET FEATURES sub-command. Bit 5: '1' = Supports the Power-Up In Standby set.
Interface Bit 5: '1' = Enables the write cache function. Bit 4: '1' = Enables the P PACKET command set. Bit 3: '1' = Enables the Power Management function. Bit 2: '1' = Enables the Removable Media function. Bit 1: '1' = Enables the Security Mode function. Bit 0: '1' = Enables the SMART function. *14 WORD 86 Bits 15-14: Reserved Bit 13-10: Same definition as WORD 83. Bit 9: '1' = Enables the Automatic Acoustic Management function. Bit 8: '1' = Enables the SET MAX Security extending function.
5.3 Host Commands *17 WORD 93 Bits 15-14: Reserved Bit 13: '1' = CBLID- is a level higher than VIH. '0' = CBLID- is a level lower than VIL. Bits 12-8: In the case of Device 1 (slave drive), a valid value is set. Bit 12: Reserved Bit 11: '1' = Device asserts PDIAG-. Bit 10, 9: Method for deciding the device No. of Device 1. '00' = Reserved '01' = Using a jumper. '10' = Using the CSEL signal. '11' = Other method. Bit 8: Bits 7-0: Reserved In the case of Device 0 (master drive), a valid value is set.
Interface Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2: '1' = Security locked Bit 1: '1' = Security enabled Bit 0: '1' = Security supported (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register.
5.3 Host Commands Table 5.5 Features register values and settable modes Features Register Drive operation mode X’02’ Enables the write cache function. X’03’ Set the data transfer mode. *1 X’05’ Enables the advanced power management function. *2 X’42’ Enables the Acoustic management function. *3 X’55’ Disables read cache function. X’66’ Disables the reverting to power-on default settings after software reset. X’82’ Disables the write cache function.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx or *1~3 1F1H(FR) [See Table 5.5] 1 1 1 xx At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information DV xx *1) Data Transfer Mode The host sets X’03’ to the Features register.
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Interface then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets. AAM Level Standard Seek Slow Seek Reserved Standard Seek Slow Seek Sector Count register C0h-FEh, 00h 80h-BFh 01h-7Fh, FFh : Maximum performance : Minimum acoustic emanation (15) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) Sector count/block 1F1H(FR) xx 0 1 1 0 xx After power-on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.
Interface • SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.
5.3 Host Commands At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) • Status information x x x DV Max head/LBA [MSB] 1F5H(CH) Max. cylinder [MSB]/Max. LBA 1F4H(CL) Max. cylinder [LSB]/Max. LBA 1F3H(SN) Max. sector/Max. LBA [LSB] 1F2H(SC) xx 1F1H(ER) Error information SET MAX SET PASSWORD (FR = 01h) This command requests a transfer of 1 sector of data from the host, and defines the contents of SET MAX password.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information Password information Words • Contents 0 Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
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Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) 03 1 0 0 1 xx At command completion (I/O registers contents to be read) • 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information SET MAX FREEZE LOCK (FR=04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
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Interface At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information x x x DV Max head/LBA [MSB] 1F5H(CH) Max. cylinder [MSB]/Max. LBA 1F4H(CL) Max. cylinder [LSB]/Max. LBA 1F3H(SN) Max. sector/Max. LBA [LSB] 1F2H(SC) xx 1F1H(ER) Error information (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device.
5.3 Host Commands Table 5.6 Diagnostic code Code Result of diagnostic X’01’ No error detected. X’03’ Data buffer compare error X’05’ ROM sum check error X’8x’ Failure of device 1 attention: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting contents) 1F7H(CM) 1 0 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx 0 0 0 0 Head No.
Interface (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command. The READ LONG command supports only single sector operation.
5.3 Host Commands (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation. The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command.
Interface (21) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.
5.3 Host Commands (22) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the buffer, then generates an interrupt.
Interface (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
5.3 Host Commands At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information DV xx (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.
Interface (25) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
5.3 Host Commands (26) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence.
Interface (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode. In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive.
5.3 Host Commands (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.
Interface (29) SMART (X’B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command. If the keys are set incorrectly, the Aborted Command error is posted. In the default setting, the failure prediction feature is enabled.
5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister X’D0’ X’D1’ X’D2’ X’D3’ X’D4’ Function SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host. * For information about the format of the attribute value information, see Table 5.8.
Interface Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister X’D5’ Function SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer. SN: 00: 01h: 06h: 80h-9Fh: X’D6’ Log sector SMART log directory SMART error log SMART self test log Host vendor log * See Table 5.
5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister X’DA’ X’DB’ Function SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers.
Interface At command completion (I-O registers setting contents) 1F7H(ST) 1F6H(DH) Status information x x x DV xx 1F5H(CH) Key-failure prediction status (C2h/2Ch) 1F4H(CL) Key-failure prediction status (4Fh/F4h) 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information The attribute value information is 512-byte data; the format of this data is shown the following table 5.8. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h).
5.3 Host Commands Table 5.8 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status flag 05 Current attribute value 06 Attribute value for worst case so far 07 to 0C Raw attribute value 0D 0E to 169 Reserved Attribute 2 to attribute 30 (The format of each attribute value is the same as that of bytes 02 to 0D.
Interface • Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated. • Attribute ID The attribute ID is defined as follows: Attribute ID 0 (Indicates unused attribute data.
5.3 Host Commands Bit Meaning 3 If this bit 1, it indicates the attribute that represents an error rate. 4 If this bit 1, it indicates the attribute that represents the number of occurrences. 5 If this bit 1, it indicates the attribute that can be collected/saved even if the drive fault prediction function is disabled. 6 to 15 • Reserve bit Current attribute value The current attribute value is the normalized raw attribute data. The value varies between 01h and 64h.
Interface Self-test execution status 0 Self-test has been completed normally or has not been executed. 1 Self-test has been stopped by the host computer. 2 Self-test has been suspended by hard or soft reset. 3 Self-test has been aborted by a fatal error. 4 Self-test has been completed abnormally by an unknown meaning. 5 Self-test has been completed abnormally by write test. 6 Self-test has been completed abnormally by serbo test. 7 Self-test has been completed abnormally by read test.
5.3 Host Commands • Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. • Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Table 5.
Interface Table 5.
5.3 Host Commands • Error log index Indicates the latest error log number. If an error has not occurred, 00 is displayed. • Error log 1 to 5 When an error occurs, the error log index value is incremented and information at the time the error occurred is recorded in the error log area specified by this value. When the error log index exceeds 05, it returns to 01. • Command data 1 to 5 Indicates five commands data in order received by the device until the error occurs.
Interface Table 5.12 SMART self test log data format Byte Item 00, 01 02 Self test log data format version number Self test log 1 03 Self test mode (SN Register Value) Self test execution status 04, 05 Total power on time until the self test is completed. [hours] 06 Self test error No. 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 1FA, 1FB Vendor unique 1FC Self test index 1FD, 1FE 1FF (Each log data format is the same as that in byte 02 to 19.
5.3 Host Commands Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error. (The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE.) Table 5.13 Contents of security password Word 0 Contents Control word Bit 0: Identifier 0 = Compares the user passwords. 1 = Compares the master passwords.
Interface (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
5.3 Host Commands Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password. If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned. Issuing this command while in FROZEN MODE returns the Aborted Command error.
Interface • SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off, or when hardware is reseted. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged. Issuing this command during LOCKED MODE returns the Aborted Command error.
5.3 Host Commands (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.13 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data. (Table 5.14) Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error. Table 5.
Interface At command issuance (I-O register contents) 1F7h(CM) 1 1 1 1 1F6h(DH) x x x DV 1F5h(CH) xx 1F4h(CL) xx 1F3h(SN) xx 1F2h(SC) xx 1F1h(FR) xx 0 0 0 1 xx At command completion (I-O register contents) 1F7h(ST) Status information 1F6h(DH) x x x 1F5h(CH) xx 1F4h(CL) xx 1F3h(SN) xx 1F2h(SC) xx 1F1h(ER) Error information DV xx (35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.12 to the device.
5.3 Host Commands UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted Command error until the device is turned off and then on, or until a hardware reset is executed. Issuing this command with LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter. Issuing this command in FROZEN MODE returns the Aborted Command error.
Interface At command issuance (I-O register contents) 1F7h(CM) 1 1 1 0 1F6h(DH) x x x DV 1F5h(CH) xx 1F4h(CL) xx 1F3h(SN) xx 1F2h(SC) xx 1F1h(FR) xx 0 1 1 1 xx At command completion (I-O register contents to be read) 1F7h(ST) Status information 1F6h(DH) x x x 1F5h(CH) xx 1F4h(CL) xx 1F3h(SN) xx 1F2h(SC) xx 1F1h(ER) Error information DV xx (37) DEVICE CONFIGURATION (B1) Individual Device Configuration Overlay feature set commands are identified by the value placed
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Interface If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power-up, an aborted error is posted. • DEVICE CONFIGURATION IDENTIFY (FR=C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5.16. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting.
5.3 Host Commands Table 5.
Interface 5.3.3 Error posting Table 5.15 lists the defined errors that are valid for each command. Table 5.
5.3 Host Commands Table 5.
Interface 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0. • EXECUTE DEVICE DIAGNOSTIC • INITIALIZE DEVICE PARAMETERS 5.4.
5.4 Command Protocol words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal.
Interface device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed. When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed. Figure 5.4 Protocol for command abort 5.4.
5.4 Command Protocol The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register.
Interface Figure 5.5 WRITE SECTOR(S) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
5.
Interface 5.4.4 Other commands • READ MULTIPLE • SLEEP • WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • READ DMA • WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance. Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed.
5.4 Command Protocol The interrupt processing for the DMA transfer differs the following point. • The interrupt processing for the DMA transfer differs the following point. a) The host writes any parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head register. b) The host initializes the DMA channel c) The host writes a command code in the Command register. d) The device sets the BSY bit of the Status register.
Interface f g d d f e Figure 5.
5.5 Ultra DMA Feature Set 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
Interface device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred. 5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts.
5.5 Ultra DMA Feature Set 8) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst. 9) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e.
Interface NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait tRP before asserting STOP. 3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
5.5 Ultra DMA Feature Set 6) The host shall drive DD (15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
Interface after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. 5) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. 6) The device shall negate DMARQ within tLI after the host has asserted STOP.
5.5 Ultra DMA Feature Set 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated. 2) The device shall assert DMARQ to initiate an Ultra DMA burst. 3) Steps (3), (4), and (5) may occur in any order or at the same time.
Interface Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode. 3) The host shall not change the state of DD (15:0) until at least tDVH after generating an HSTROBE edge to latch the data. 4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first. 5.5.4.
5.5 Ultra DMA Feature Set 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges. 2) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge.
Interface b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred. 2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.
5.5 Ultra DMA Feature Set 13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.
Interface i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last. 5.5.
5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. t0 Addresses t1 t9 t2 DIOR-/DIOW- t2i Write data DD0-DD15 t3 t4 Read data DD0-DD15 t5 t6 t10 IORDY t11 t12 Symbol Timing parameter Min. Max.
Interface 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. t0 DMARQ DMACK- tJ tC tI tK tD DIOR-/DIOW- Write data DD0-DD15 tG tH Read data DD0-DD15 tE Symbol tF Timing parameter Min. Max.
5.6 Timing 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.20 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t2CYCTYP 240 160 120 90 60 40 tCYC 112 73 54 39 25 16.
5.6 Timing Table 5.
Interface Table 5.19 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tDSIC 14.7 9.7 6.8 6.8 4.8 2.3 Recipient IC data setup time (from data valid until STROBE edge) (*1) tDHIC 4.8 4.8 4.8 4.8 4.8 2.8 Recipient IC data hold time (from STROBE edge until data may become invalid) (*1) tDVSIC 72.9 50.9 33.9 22.6 9.
5.6 Timing 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tRP STOP (host) HDMARDY(host) tRFS DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) After negating HDMARDY-, the host may receive zero, one, two or three more data words from the device. Figure 5.
5.6 Timing 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tMLI DMACK(host) STOP (host) tACK tLI tLI tACK tLI HDMARDY(host) tSS tIORDYZ DSTROBE (device) tZAH tAZ DD(15:0) tCVS tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tLI tMLI DMACK(host) tAZ tRP tZAH tACK STOP (host) tACK HDMARDY(host) tRFS tLI tMLI tIORDYZ DSTROBE (device) tCVS DD(15:0) tCVH CRC tACK DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6 Timing 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tUI DMACK(host) tACK tENV STOP (host) tZIORDY tLI tUI DDMARDY(device) tACK HSTROBE (host) tDZFS tDVS tDVH DD(15:0) (host) tACK DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted. Figure 5.
Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6 Timing 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tRP DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) tRFS HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) After negating DDMARDY-, the device may receive zero, one two or three more data words from the host. Figure 5.
Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tLI DMARQ (device) tMLI DMACK(host) tLI tACK tSS STOP (host) tLI tIORDYZ DDMARDY(device) tACK HSTROBE (host) tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6 Timing 5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tLI tACK tMLI STOP (host) tRP tIORDYZ DDMARDY(device) tRFS HSTROBE (host) tLI tMLI tACK tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
Interface 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset tM tN BSY DASPtP *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device] tN BSY DASP[Slave device] BSY tQ tP PDIAG- tS DASPtR Symbol Timing parameter Min. Max.
CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Power Save 6.3 Defect Management 6.4 Read-Ahead Cache 6.
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).
6.1 Device Response to the Reset Power on Master device Power On ResetStatus Reg. BSY bit Max. 31 sec. Checks DASP- for up to 450 ms. If presence of a slave device is confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On ResetBSY bit Max. 1 ms. PDIAG- Max. 30 sec. DASPMax. 400 ms. Figure 6.1 Response to power-on Note: Figure 6.1 has a assumption that the device is kept on the power-off condition for more than 5 sec before the device power is turned on. 6.1.
Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 400 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. ResetMaster device Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to 450 ms. If presence of a slave device is confirmed, PDIAG- is checked for up to 31 seconds. Slave device BSY bit PDIAG- Max. 1 ms. Max.
6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAGsignal for up to 6 seconds to see if the slave device has completed the selfdiagnosis successfully. The master device does not check the DASP- signal.
6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are four types of power consumption state of the device including active mode where all circuits are active. In the power save mode, power supplying to the part of the circuit is turned off.
Operations takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately. The drive enters the standby mode under the following conditions: • A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode. • When automatic power down sequence is enabled, the timer has elapsed. • A reset is issued in the sleep mode. When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode.
6.3 Defect Management 6.3 Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment. All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6.1. 6.3.1 Spare area Following two types of spare area are provided for every physical head.
Operations 0 1 2 3 4 5 6 7 657 658 659 0 1 2 3 (unused) 4 5 6 656 657 658 Note: If an access request to logical sector 4 is specified, the device accesses physical sector 5 instead of sector 4. Figure 6.5 Sector slip processing (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder.
6.4 Read-Ahead Cache Index Sector (Physical) 0 1 2 3 4 5 6 658 659 5 6 658 659 Cylinder 0 Defective sector Head 0 0 1 2 3 4 (unused) Sector (Logical) Alternate cylinder Already assigned Head 0 Defective sector is assigned to unassigned sector. Notes: 1) 4 alternate cylinders are provided for each head in zone 14 (inner side). 2) When an access request to logical sector 4 is specified, the device accesses the alternated sector in the alternate cylinder instead of sector 4.
Operations When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium. The host can thus access data at higher speed. 6.4.1 Data buffer configuration The drive has a 2 MB data buffer. The buffer is used by divided into three parts; for read/write commands, and for MPU work (see Figure 6.9). 2048 KB for read/write commands for MPU works 80 KB 1968 KB Figure 6.
6.4 Read-Ahead Cache 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation. 2) Data transferred to the host system once by requesting with the command that are object of caching operation (except for the cache invalid data by some reasons).
Operations 6) The device enters the sleep mode. 7) Under the state that the write data is kept in the data buffer for write command as a caching data, new write command is issued. (write data kept until now are invalidated) 6.4.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. 6.4.3.1 Mis-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media.
6.4 Read-Ahead Cache 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation. HAP (stopped) Empty area Read-requested data (stopped) DAP 4) Following shows the cache enabled data for next read command. Empty area Cache enabled data Start LBA Last LBA 6.4.3.
Operations 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data. HAP Requested data Mis-hit data Empty area DAP 3) After completion of the reading and transferring the requested data to the host system, the disk drive performs the read-ahead operation continuously.
6.4 Read-Ahead Cache 1) In the case that the contents of buffer is as follows at receiving a read command; HAP (Continued from the previous read request data) Read-ahead data Hit data DAP Last LBA Start LBA 2) The disk drive starts the read-ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data.
Operations 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA c. Non-sequential command immediately after sequential command When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received. (Refer to 6.5.3.1.
6.4 Read-Ahead Cache 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.4.3.4 Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly. The disk drive does not perform the read-ahead operation after data transfer.
Operations 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.5 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
6.5 Write Cache The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed. If an error occurs during the write operation, the device retries the processing. If the error cannot be recovered by retry, automatic alternate assignment is performed. For details about automate alternate assignment, see item (3) of Section 6.4.2.
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Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors. Interfaces based on this standard are called ATA interfaces.
Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. VCM Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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Acronyms and Abbreviations HDD Hard disk drive A ABRT AIC AMNF ATA AWG Aborted command Automatic idle control Address mark not found AT attachment American wire gage B BBK BIOS Bad block detected Basic input-output system C CORR CH CL CM CSR CSS CY Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start/stop Cylinder register I IDNF IRQ14 L LED dB A-scale weighting Disk enclosure Device/head register Drive ready Ddata request bit Drive seek
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Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E120-02EN Manual name MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance Technical level Organization Clarity Accuracy ( ( ( ( ( ) ) ) ) ) Illustration Glossary Acronyms & Abbreviations Index ( ( ( ( ) ) ) ) Comments & Suggestions List any errors or suggestions for improvement.
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MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL C141-E120-02EN MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL C141-E120-02EN
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