MPG3xxxAH-E DISK DRIVES PRODUCT MANUAL C141-E116-01EN
REVISION RECORD Edition Date published 01 Oct., 2000 Revised contents Specification No.: C141-E116-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved.
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MANUAL ORGANIZATION MPG3xxxAH-E DISK DRIVES PRODUCT MANUAL (C141-E116) MPG3xxxAH-E DISK DRIVES MAINTENANCE MANUAL (C141-F050) • • • • • • DEVICE OVERVIEW DEVICE CONFIGURATION INSTALLATION CONDITIONS THEORY OF DEVICE OPERATION INTERFACE OPERATIONS • MAINTENANCE AND DIAGNOSIS • REMOVAL AND REPLACEMENT PROCEDURE C141-E116-01EN iii
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PREFACE This manual describes the MPG3xxxAH-E series, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation likely to result in serious personal injury if the user does not perform the procedure correctly.
LIABILITY EXCEPTION "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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CONTENTS page CHAPTER 1 DEVICE OVERVIEW..........................................................................................1 - 1 1.1 Features .................................................................................................................................1 - 1 1.1.1 Functions and performance ...................................................................................................1 - 1 1.1.2 Adaptability...................................................................
3.4.2 Cable connector specifications ..............................................................................................3 - 9 3.4.3 Device connection .................................................................................................................3 - 9 3.4.4 Power supply connector (CN1) .............................................................................................3 - 10 3.4.5 System configuration for Ultra DMA..................................................
CHAPTER 5 INTERFACE .........................................................................................................5 - 1 5.1 Physical Interface ..................................................................................................................5 - 2 5.1.1 Interface signals.....................................................................................................................5 - 2 5.1.2 Signal assignment on the connector.............................................
5.6.3 Ultra DMA data transfer........................................................................................................5 - 97 5.6.3.1 Initiating an Ultra DMA data in burst....................................................................................5 - 97 5.6.3.2 Ultra DMA data burst timing requirements ...........................................................................5 - 98 5.6.3.3 Sustained Ultra DMA data in burst .............................................................
FIGURES page 1.1 Current fluctuation (Typ.) when power is turned on .............................................................1 - 7 2.1 Disk drive outerview .............................................................................................................2 - 1 2.2 1 drive system configuration .................................................................................................2 - 3 2.3 2 drives configuration....................................................................
5.3 Protocol for command abort..................................................................................................5 - 79 5.4 WRITE SECTOR(S) command protocol ..............................................................................5 - 80 5.5 Protocol for the command execution without data transfer ...................................................5 - 81 5.6 Normal DMA data transfer....................................................................................................
TABLES page 1.1 Specifications ........................................................................................................................1 - 4 1.2 Model names and product numbers.......................................................................................1 - 5 1.3 Current and power dissipation...............................................................................................1 - 6 1.4 Environmental specifications .....................................................
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CHAPTER 1 DEVICE OVERVIEW 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MPG3xxxAH-E series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable. 1.1 Features 1.1.
(4) Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 8.5 ms (at read). 1.1.2 Adaptability (1) Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor. (2) Wide temperature range The disk drive can be used over a wide temperature range (5°C to 55°C).
(5) Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has improved buffer error correction for correctable data errors. (6) Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media. This feature reduces the access time at writing.
1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. Table 1.1 Specifications MPG3204AH-E MPG3307AH-E MPG3409AH-E 20.49 GB 30.74 GB 40.
1.2.2 Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors MPG3204AH-E 20,496 MB 16,383 16 63 MPG3307AH-E 30,743 MB 16,383 16 63 MPG3409AH-E 40,992 MB 16,383 16 63 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Model Name Capacity (user area) Mounting Screw MPG3204AH-E 20.49 GB No. 6-32UNC CA05762-B521 — MPG3307AH-E 30.74 GB No. 6-32UNC CA05762-B544 — MPG3409AH-E 40.99 GB No. 6-32UNC CA05762-B542 — 1.
(3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS current (*1) [mA] Mode of Operation Typical Power (*2) [watts] +12 V +5 V Model MPG 3204AH-E MPG 3307AH-E MPG 3409AH-E All Models MPG 3204AH-E MPG 3307AH-E MPG 3409AH-E Spin up 1950 peak 1950 peak 1950 peak 800 peak 27.4 27.4 27.4 Idle (Ready) (*3) 350 400 400 490 6.7 7.3 7.3 R/W (On Track) (*4) 370 450 450 600 7.4 8.4 8.
(4) Current fluctuation (Typ.) when power is turned on Note: Maximum current is 1.95A. Figure 1.1 (5) Current fluctuation (Typ.) when power is turned on Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence.
1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.
1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Vibration (swept sine, one octave per minute) • Operating • Non-operating 4.9 m/s2 (0.5G0-P); 5 to 300 Hz (without non-recovered errors) 39.2 m/s2 (4.0G0-P); 5 to 400 Hz (no damage) Shock (half-sine pulse, Operating) • 2 ms duration 392 m/s2 (40G0-P) (without non-recovered error) Shock (half-sine pulse, Non-operating) • 2 ms duration 2940 m/s2 (300G0-P) (Typical, no damage) 1.
(4) Service life In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.3 for the measurement point of the DE surface temperature.
CHAPTER 2 2.1 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.
(1) Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 50,000 start/stop operations. MPG3204AH-E: 1 disks MPG3307AH-E: 2 disks MPG3409AH-E: 2 disks (2) Head The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.
2.2 System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4), and the ultra DMA transfer till 100 MB/s (Ultra mode 5). 2.2.2 1 drive connection HA (Host adaptor) Host ATA interface AT bus (Host interface) Figure 2.2 2.2.
IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-5 interface. At high speed data transfer (PIO mode 3, mode 4, DMA mode 2, ultra DMA mode 4 or ultra DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
CHAPTER 3 3.1 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Handling Cautions 3.3 Mounting 3.4 Cable Connections 3.5 Jumper Settings Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.
Figure 3.
3.2 Handling Cautions Please keep the following cautions, and handle the HDD under the safety environment. 3.2.1 General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically to avoid falling down. Do not drop. Figure 3.2 Handling cautions 3.2.
3.3 Mounting (1) Direction Figure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in any direction. Horizontal mounting with the PCB facing down Figure 3.3 (2) Direction Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground. These are electrically shorted. Note: Use No.6-32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3.5.
Use these screw holes Do not use this screw holes Figure 3.4 Limitation of side-mounting Side surface mounting 2.5 Bottom surface mounting 2.5 DE DE 2.5 2 PCA A Frame of system cabinet B Frame of system cabinet 4.5 or less Screw Screw 5.0 or less Details of A Details of B Figure 3.
(4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface temperatures of the DE.
(5) Service area Figure 3.7 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [Q side] - Mounting screw hole [P side] - Cable connection - Mode setting switches [R side] - Mounting screw hole Figure 3.7 (6) Service area External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.
3.4 Cable Connections 3.4.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. • • Power supply connector (CN1) ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins ATA interface connector Figure 3.
3.4.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors for Host system that do not support Ultra DMA modes greater than mode 2. For Host system that support Ultra DMA modes greater than mode 2, the 80-conductor cable assemblies shall be used. The 80-conductor cable assemblies are manufactured by AMP or 3M. Table 3.
3.4.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). 1 2 3 4 1 +12VDC 2 +12V RETURN 3 +5V RETURN 4 +5VDC (Viewed from cable side) Figure 3.10 Power supply connector pins (CN1) 3.4.5 System configuration for Ultra DMA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports. They shall provide separate drivers and separate receivers for each cable.
254.0 to 457.2 mm (10 to 18 inch) 127.0 to 304.8 mm 101.6 to 152.4 mm (5 to 12 inch) (4 to 6 inch) Pin 40 (Ground) open Pin 34 Pin 34 contact (PDIAG-:CBLID- signal) Pin 30 (Ground) Pin 26 (Ground) Pin 24 (Ground) Pin 22 (Ground) Pin 19 (Ground) Symbolizes Pin 34 Conductor being cut Position 1 Pin 2 (Ground) System Board Connector Connector 1 Connector 2 Figure 3.
Host detected CBLID- below VIL Host detected CBLID- above VIH open PDIAG-: CBLID- conductor Host Device 1 Device 0 PDIAG-: CBLID- conductor Host with 40-conductor cable Device 1 Device 0 with 80-conductor cable Figure 3.
3.5 Jumper Settings 3.5.1 Location of setting jumpers Figure 3.14 shows the location of the jumpers to select drive configuration and functions. DC Power Connector Interface Connector 2 40 1 1 Figure 3.
3.5.2 Factory default setting Figure 3.15 shows the default setting position at the factory. (Master device setting) DC Power Connector Interface Connector Figure 3.15 Factory default setting 3.5.3 Jumper configuration (1) Device type Master device (device #0) or slave device (device #1) is selected. 2 4 6 8 2 4 6 8 = shorted 1 3 5 7 9 (a) Master device 1 3 5 7 9 (b) Slave device Figure 3.
2 4 6 8 1 3 5 7 9 CSEL connected to the interface cable selection can be done by the special interface cable. Figure 3.17 Jumper setting of Cable Select Figures 3.18 and 3.19 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level. The device is identified as a master device. At this time, the CSEL of the slave device does not have a conductor.
(3) Special jumper settings (a) 2.1 GB clip (Limit capacity to 2.1 GB) / 33.8 GB clip (Limit capacity to 33.8 GB) If the drive cannot be recognized by system with legacy BIOS’s which do not allow single volume sizes greater than approximately 2.1 GB, the following jumper settings should be applied. This jumper settings is also used as the 33.8 GB clip for MPG3409AH-E. (MPG3409AH-E does not have the 2.1 GB clip feature.
CHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks. 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive.
4.2.2 Head Figure 4.1 shows the read/write head structures. The Numerals 0 to 3 indicate read/write heads. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. MPG3204AH-E Spindle Actuator 1 0 MPG3307AH-E / MPG3409AH-E Spindle Actuator 3 2 1 0 Figure 4.1 4.2.3 Head structure Spindle The spindle consists of a disk stack assembly and spindle motor.
4.2.4 Actuator The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head. 4.2.5 Air filter There are two types of air filters: a breather filter and a circulation filter.
4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.
ATA Interface PCA HDC & MCU & RDC CL-SH8671 (Himalaya-2) Data Buffer SDRAM MCU ARM7TDMI HDC CL-SH7660 Flash ROM RDC Number-B FROM SVC Resonator HA13627 20MHz DE SP Motor VCM Temp. Sensor R/W Pre-Amp HEAD Media SR1756 or M61850 Figure 4.
4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor. b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.
Power on a) Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. b) Self-diagnosis 2 • Data buffer write/read test c) Confirming spindle motor speed Release heads from actuator lock d) Initial on-track and read out of system information e) Execute self-calibration f) Drive ready state (command waiting state) End Figure 4.
4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.
4.5.2 Execution timing of self-calibration Self-calibration is executed when: • • The power is turned on. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. After power-on, self-calibration is performed about every 30 minutes, when the host command is not issued for 15 seconds. 4.5.
4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the synthesizer in the read channel (RDC). 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC. The PreAMP consists of a 4-channel read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the serial port (SDEN, SCLK, SDATA).
4.6.3 Read circuit The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 48/52 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
4.6.4 Synthesizer circuit The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.
4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand. 4.7.1 Servo control circuit Figure 4.4 is the block diagram of the servo control circuit.
b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0). c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value.
Servo frame (96 servo frames per revolution) Figure 4.5 (2) Physical sector servo configuration on disk surface Servo burst capture circuit The four servo signals can be synchronously detected by the DEMOD signal (internal), full-wave rectified integrated. (3) A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit.
(4) D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier. (5) Power amplifier The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM. (6) Spindle motor control circuit The spindle motor control circuit controls the sensor-less spindle motor.
4.7.3 Servo frame format As the servo information, the drive uses the two-phase servo generated from the gray code and Pos A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, Pos A to D and PAD. Figure 4.6 shows the servo frame format. 0.72 µs 0.17 µs 0.16 µs 0.53 µs 0.74 µs 0.56 µs 0.56 µs 0.56 µs 0.80 µs 1.
(1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark (ASM, SSM) This area generates a timing for demodulating the gray code and position-demodulating Pos A to D by detecting the servo mark. (3) Preamble This area is used to synchronize with the PLL, which is used to search the SSM by detecting the ASM. (4) Gray code (including index bit) (SCD) This area is used as cylinder address.
b) A current is fed to the VCM to move the head toward the outer circumference. c) When the servo mark is detected the head is moved slowly toward the outer circumference at a constant speed. d) If the head is stopped at the reference cylinder from there. Track following control starts. (2) Seek operation Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read or instruction is issued, the MPU seeks the desired track.
d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.
CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature set 5.
5.1 Physical Interface 5.1.1 Interface signals Table 5.1 shows the interface signals. Table 5.
5.1.2 Signal assignment on the connector Table 5.2 shows the signal assignment on the interface connector. Table 5.2 Signal assignment on the interface connector Pin No. Signal Pin No.
[signal] 5-4 [I/O] [Description] DIOR– I DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– I HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts. The host may negate HDMARDY- to pause an Ultra DMA data in burst. HSTROBE I HSTROBE is the data out strobe signal from the host for an Ultra DMA data out burst.
[signal] [I/O] [Description] IORDY O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– O DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate DDMARDY– to pause an Ultra DMA data out burst.
5.2 Logical Interface The device can operate for command execution in either address-specified mode; cylinder-headsector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.
Table 5.
5.2.2 Command block registers (1) Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
[Diagnostic code] (3) X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X'01' to X'05').
(6) Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any diskaccess. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. (7) Cylinder High register (X'1F5') The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
(9) Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt).
(10) - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error. Command register (X'1F7') The Command register contains a command code being sent to the device.
5.2.3 Control block registers (1) Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
5.3.1 Command code and parameters Table 5.4 lists the supported commands, command code and the registers that needed parameters are written. Table 5.
Table 5.
5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) Bit 7 6 5 4 3 2 1 0 1F7H(CM) 0 0 1 0 0 0 0 0 1F6H(DH) × L × DV Head No. / LBA [MSB] Start cylinder address [MSB] / LBA Start cylinder address [LSB] / LBA Start sector No.
Note: (1) 1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). 2. At error occurrence, the SC register indicates the remaining sector count of data transfer. 3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
Figure 5.1 shows an example of the execution of the READ MULTIPLE command. • • Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) ↓ Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter Write Status read ~ BSY Status read Status read DRDY INTRQ DRQ 1 Sector transferred 2 3 5 4 6 Block Figure 5.
(3) READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. • The device posts a status as the result of command execution only once at completion of the data transfer.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × L × DV 0 1 0 1 Start head No. /LBA [MSB] Start cylinder No. [MSB] / LBA Start cylinder No. [LSB] / LBA Start sector No.
1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × L × DV 1 0 1 R Start head No. /LBA [MSB] Start cylinder No. [MSB] / LBA Start cylinder No. [LSB] / LBA Start sector No.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
(10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.
(11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt. When the SC register is specified to X'00', an ABORTED COMMAND error is posted.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 1 0 0 xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Table 5.
Table 5.
Table 5.5 *1 Information to be read by IDENTIFY DEVICE command (3 of 6) Word 0: General configuration Bit 15: 0 = ATA device Bit 14-8: Vendor specific Bit 7: 1 = Removable media device Bit 6: 1 = not removable controller and/or device Bit 5-1: Vendor specific Bit 0: Reserved 0 0 1 0 *2 Number of Cylinders, *3 Number of Heads, *11 Total number of user addressable sectors (LBA mode only.
Table 5.
Table 5.
Table 5.5 Information to be read by IDENTIFY DEVICE command (6 of 6) *20 Word 89: Time required for SECURITY ERASE UNIT command to complete. MPG3204AH-E = 0004H: 8 minutes MPG3307AH-E = 0006H: 12minutes MPG3409AH-E = 0008H: 16 minutes *21 Word 93: Hardware reset result. The contents of bits 12-0 of this word shall change only during the execution of a hardware reset.
(13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.
Table 5.6 Features Register Features register values and settable modes Drive operation mode X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘04’ No operation. X‘05’ Enable the advanced power management function. X‘33’ No operation. X‘42’ Enable Automatic Acoustic Management feature set X‘54’ No operation. X‘55’ Disables the read cache function.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 1 1 1 xx xx xx xx xx or transfer mode [See Table 5.6] At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × DV xx xx xx xx xx Error information The host sets X'03' to the Features register.
Subcommand code 42h allows the host to enable the Automatic Acoustic Management feature set. To enable the Automatic Acoustic Management feature set, the host writes the Sector Count register with the requested automatic acoustic management level and executes a SET FEATURES command with subcommand code 42h. The acoustic management level is selected on a scale from 01h to FEh. Following table shows the acoustic management level values.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 1 0 xx xx xx xx Sector count/block xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × DV xx xx xx xx Sector count/block Error information After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the
• • • • • Both devices shall execute self-diagnosis. The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal. If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X‘80’ to its own diagnostic status. The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.) A diagnostic status of the device 0 is read by the host system.
(17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte format parameter transfer from the host system. After completion of transfer, the device clears the DRQ bits, sets the BSY bit. However the device does not perform format operation, but the drive clears the BYS bit and generates an interrupt soon. When the command execution completes, the device clears the BSY bit and generates an interrupt.
• The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.) If above condition is not satisfied, the command operation is not guaranteed. At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 1 1F6H(DH) × L × DV 0 0 1 R Head No. /LBA [MSB] Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (21) DV xx xx xx xx xx Error information WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.
(22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (23) DV xx xx xx xx xx Error information IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.
(24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) X'94' or X'E0' × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (26) DV xx xx xx xx xx Error information SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (27) × DV xx xx xx xx xx Error information CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers. The device sets the BSY bit and sets the following register value.
At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) X'98' or X'E5' × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (28) Status information × × × DV xx xx xx xx X'00' or X'FF' Error information SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.
Table 5.8 Features Register values (subcommands) and functions (1/2) Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host. * For information about the format of the attribute value information, see Table 5.9.
Table 5.8 Features Register values (subcommands) and functions (2/2) X’D5’ X’D6’ X’D8’ X’D9’ X’DA’ X’DB’ SMART Read Logging Data: This subcommand is used to transfer logging data that transfer length specified in SC register is to the host. The setting of SN register is described Log Sector Address below. When SN register is set 00h, 01h, or 06h, SC register should be set to 01h. When SN register is set 80h-9Fh, SC register should be set 01h to maximum value that shows in the Log Directory.
The host must regularly issue the SMART Read Attribute Values subcommand (FR register = D0h), SMART Save Attribute Values subcommand (FR register = D3h), or SMART Return Status subcommand (FR register = DAh) to save the device attribute value data on a medium. Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.
Table 5.9 Device attribute data structure Byte (Hex) Description 00 01 Data structure revision number *1 02 1st attribute Attribute ID number *2 03 04 Status flag *3 05 Normalized attribute values *4 06 Worst ever normalized *5 07 to 0C Raw attribute values *6 0D Reserved 0E to 169 2nd to 30th attribute Reserved 16A Off-line data collection Off-line data collection status *7 16B (Each attribute format is the same as 1st attribute.
Table 5.10 Warranty failure threshold data structure Byte (Hex) Description 00 01 Data structure revision number *1 02 1st drive threshold Attribute ID number *2 03 04 Attribute threshold *15 05 Reserved 06 07 to 0C 0D 0E to 169 2nd to 30th drive threshold 16A to 17B 17C to 1FE Reserved 1FF Reserved (Each threshold format is the same as 1st drive threshold.
*2 Attribute ID The attribute ID is defined as follows: Attribute ID (Dec) Description 0 (Indicates unused attribute data) 1 Read error rate 2 Throughput performance 3 Spin up time 4 Number of times the spindle motor is activated 5 Number of alternative sectors 6 Read channel margin (Not supported) 7 Seek error rate 8 Seek time performance 9 Power-on time 10 Number of retries made to activate the spindle motor 11 Number of retries to calibration 12 Number of turn on/off times 13
*3 Status flag Bit Description 0 If this bit is set to 1, it indicates the attribute is guaranteed for normal operation when an attribute value exceeds the threshold. 1 If this bit is set to 1 (0), it indicates the attribute is updated only by on-line test (off-line test). 2 If this bit is set to 1, it indicates a performance attribute. 3 If this bit is set to 1, it indicates an error-rate attribute. 4 If this bit is set to 1, it indicates an event count attribute.
*7 Off-line data collection status Values Description 00h or 80h Off-line data collection is not started. 01h or 81h Reserved 02h or 82h Off-line data collection has been completed without error. 03h or 83h Reserved 04h or 84h Off-line data collection has been suspended by an interrupt command from the host. 05h or 85h Off-line data collection has been aborted by an interrupt command from the host. 06h or 86h Off-line data collection has been aborted with a fatal error.
*9 Off-line data collection capability [16Fh] Bit 0 If this bit is set to 1, it indicates SMART EXECUTE OFF-LINE IMMEDIATE subcommand is supported. (FR register = D4) 1 Vendor unique 2 If this bit is set to 1, it indicates off-line data collection being aborted when a new command is received. 3 If this bit is set to 1, it indicates SMART off-line read scanning is supported. 4 If this bit is set to 1, it indicates SMART Self Test is supported.
*15 Attribute threshold The limit of a varying attribute value. thresholds to identify a failure. The host compares the attribute values with the Table 5.
Table 5.
Table 5.13 Self Test log data structure Byte 0 to 1 2 3 4 to 5 6 7 to 10 11 to 25 26 to 49 … 482 to 505 506 to 507 508 509 to 510 511 • • • • *16 Description Data Structure Revision Number = 0x0001 1st Descriptor Entry Self Test Number Self Test Execution Status Life time power on hours Self Test Error No. Error LBA Vender Specific bytes 2nd Descriptor Entry … 21st Descriptor Entry Vender Specific Self Test Index Reserved Checksum Self Test Number This byte shows executed Self Test Number.
(29) FLUSH CACHE (X ‘E7’) This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The device should use all error recovery methods available to ensure the data is written successfully.
(30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table5.14 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same. Although this command invalidates the user password, the master password is retained.
At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 1 0 xx xx xx xx xx xx At command completion (I-O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (31) DV xx xx xx xx xx Error information SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SE
At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 1 1 xx xx xx xx xx xx At command completion (I-O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (32) × DV xx xx xx xx xx Error information SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 0 0 xx xx xx xx xx xx At command completion (I-O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (33) DV xx xx xx xx xx Error information SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE.
• READ DMA • WRITE LONG • SECURITY DISABLE PASSWORD • READ LONG • WRITE MULTIPLE • SECURITY FREEZE LOCK • READ MULTIPLE • WRITE SECTORS • SECURITY SET PASSWORD • READ SECTORS • WRITE VERIFY • FORMAT TRACK • READ VERIFY • SET MAX ADDRESS • FLASH CACHE • WRITE DMA At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 0 1 xx xx xx xx xx xx At command completion (I-O registers contents to be read)
Table 5.15 Contents of SECURITY SET PASSWORD data Word 0 Contents Control word Bit 0 Identifier 0 = Sets a user password. 1 = Sets a master password. Bits 1 to 7 Reserved Bit 8 Security level 0 = High 1 = Maximum Bits 9 to 15 Reserved 1 to 16 17 to 255 Table 5.16 Indentifier 5 - 68 Password (32 bytes) Reserved Relationship between combination of Identifier and Security level, and operation of the lock function Level Description User High The specified password is saved as a new user password.
At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 0 1 xx xx xx xx xx xx At command completion (I-O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (35) × DV xx xx xx xx xx Error information SECURITY UNLOCK (F2h) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.14 to the device.
At command issuance (I-O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 1 0 xx xx xx xx xx xx At command completion (I-O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (36-1) × × DV xx xx xx xx xx Error information SET MAX ADDRESS (F9) This command allows the maximum address accessible by the user to be set in LBA or CHS mode.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1 0 0 1 Max head/LBA [MSB] Max. cylinder [MSB]/Max. LBA Max. cylinder [LSB]/Max. LBA Max. sector/Max. LBA [LSB] 1F2H(SC) xx 1F1H(FR) VV xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × DV Max head/LBA [MSB] Max. cylinder [MSB]/Max. LBA Max. cylinder [LSB]/Max. LBA Max. sector/Max.
At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) 1 L 1 DV xx xx xx xx xx Error information 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) SET MAX SET PASSWORD data content Word Content 0 1 - 16 17 - 255 (36-3) Reserved Password (32 bytes) Reserved SET MAX LOCK (F9) After this command is completed any other Set Max commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected.
(36-4) SET MAX UNLOCK (F9) This command requests a transfer of a single sector of data from the host. The password supplied in the sector of data transferred shall be compared with the stored SET MAX password. If the password compare fails, then the device returns command aborted and decrements the unlock counter. On the acceptance of the SET MAX LOCK command, this counter is set to a value of five and shall be decremented for each password mismatch when SET MAX UNLOCK is issued and the device is locked.
• • • • SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) 1 L 1 DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1 0 0 1 0 0 xx xx xx xx xx 1F1H(FR) 0 0 0 0 0 1 At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) 1 L 1 xx xx xx xx xx Error information 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (37) DV READ NATIVE MAX ADDRESS (F8) This command
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × × × DV Max head/LBA [MSB] Max. cylinder [MSB]/Max. LBA Max. cylinder [LSB]/Max. LBA Max. sector/Max.
5.3.3 Error posting Table 5.17 lists the defined errors that are valid for each command. Table 5.
5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0. • • 5.4.
Command Parameter write ~ Status read a BSY Status read b c •••• e d DRDY f e d •••• DRQ INTRQ Data transfer Expanded Command Min. 30 µs (*1) ••• DRQ INTRQ Data Reg. Selection Data •••• •••• IOR- •••• Word 0 1 2 255 IOCS16*1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register. e) The device clears the DRQ bit and sets the BSY bit.
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
5.4.4 Other commands • • • READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • • READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance. The interrupt processing for the DMA transfer differs the following point. • 5 - 82 The interrupt processing for the DMA transfer differs the following point.
Parameter write Command ~ BSY Status read c, d a •• DRDY f g INTRQ e •• DRQ •• Data transfer Expanded [Multiword DMA transfer] •••• DRQ •••• DMARQ DMACK- •••• •••• IOR- or IOWWord 0 Figure 5.
5.5 Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).
11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving the first word of data onto DD (15:0). 5.5.3.
3) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-. 4) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5). 12) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places the result of its CRC calculation on DD (15:0).
9) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation. 11) To transfer the first word of data: the host shall negate HSTROBE no sooner than tLI after the device has asserted DDMARDY-.
b) Device pausing an Ultra DMA data out burst 1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The device shall pause an Ultra DMA burst by negating DDMARDY-. 3) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-. 4) If the device negates DDMARDY- within tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words.
9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 10) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. 11) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-.
11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 12) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. 13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.
i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last. 5.5.
5.6 Timing 5.6.1 PIO data transfer Figure 5.8 shows of the data transfer timing between the device and the host system. t0 Addresses t1 t9 t2 DIOR-/DIOW- t2i Write data DD0-DD15 t3 t4 Read data DD0-DD15 t5 t6 t10 IORDY t11 t12 Symbol Timing parameter Min. Max.
5.6.2 Multiword data transfer Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system. t0 DMARQ DMACK- tJ tC tI tK tD DIOR-/DIOW- Write data DD0-DD15 tG tH Read data DD0-DD15 tE Symbol Timing parameter tF Min. Max.
5.6.3 Ultra DMA data transfer Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts. Table 5.19 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6.3.2 Ultra DMA data burst timing requirements Table 5.19 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) MODE 3 (in ns) MODE 4 (in ns) MODE 5 (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t2CYCTYP 240 160 120 90 60 40 Typical sustained average two cycle time tCYC 112 73 54 39 25 16.
Table 5.
Table 5.20 Ultra DMA sender and recipient timing requirements NAME MODE 0 (in ns) MODE 1 (in ns) MODE 2 (in ns) MODE 3 (in ns) MODE 4 (in ns) MODE 5 (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tDSIC 14.7 9.7 6.8 6.8 4.8 2.3 Recipient IC data setup time (from data valid until STROBE edge) (*1) tDHIC 4.8 4.8 4.8 4.8 4.8 2.8 Recipient IC data hold time (from STROBE edge until data may become invalid) (*1) tDVSIC 72.9 50.9 33.9 22.6 9.
5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tRP STOP (host) HDMARDY(host) tRFS DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) After negating HDMARDY-, the host may receive zero, one, two or three more data words from the device. Figure 5.
5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tMLI DMACK(host) STOP (host) tACK tLI tLI tACK tLI HDMARDY(host) tSS tIORDYZ DSTROBE (device) tZAH tAZ tCVS DD(15:0) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tLI tMLI DMACK(host) tAZ tRP tZAH tACK STOP (host) tACK HDMARDY(host) tRFS tLI tMLI tIORDYZ DSTROBE (device) tCVS DD(15:0) tCVH CRC tACK DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tUI DMACK(host) tACK tENV STOP (host) tZIORDY tLI tUI DDMARDY(device) tACK HSTROBE (host) tDZFS tDVS tDVH DD(15:0) (host) tACK DA0, DA1, DA2 CS0-, CS1Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted. Figure 5.
5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tRP DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) tRFS HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) After negating DDMARDY-, the device may receive zero, one two or three more data words from the host. Figure 5.
5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tLI DMARQ (device) tMLI DMACK(host) tLI tACK tSS STOP (host) tLI tIORDYZ DDMARDY(device) tACK HSTROBE (host) tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tLI tACK tMLI STOP (host) tRP tIORDYZ DDMARDY(device) tRFS tLI HSTROBE (host) tMLI tACK tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6.4 Power-on and reset Figure 5.20 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset tM tN BSY DASPtP *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device] tN BSY DASP[Slave device] BSY tQ tP PDIAG- tS DASPtR Symbol Timing parameter Min. Max.
CHAPTER 6 6.1 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command.
6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASPsignal. Then, the master device checks a PDIAG- signal to see if the slave device has successfully completed the power-on diagnostics.
6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal. Then the master device checks a PDIAG- signal to see if the slave device has successfully completed the self-diagnostics.
6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.
6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.
6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.
6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.
(2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track. Figure 6.6 shows an example of (assuming there is no track skew).
(1) Active mode In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation. A device enters the active mode under the following conditions: • (2) A command with Seek or Write or Read is issued. Idle mode In this mode, circuits on the device is set to power save mode. The device enters the Idle mode under the following conditions: • A IDLE or IDLE IMMEDIATE command is issued in the active or standby mode.
• (4) CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset. The drive enters the sleep mode under the following condition: • A SLEEP command is issued. Issued commands are invalid (ignored) in this mode. 6.3.2 Power commands The following commands are available as power commands. 6.
6.4.1 Spare area Following two types of spare area are provided in the user space. 1) Spare sector for sector slip: used for alternating defective sectors at formatting in shipment (128 sectors/32 cylinders) 2) Spare cylinder for alternative assignment: used by automatic alternative assignment. (4 cylinders/drive) 6.4.
(2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when a physical track contains three or more defective sectors, and when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0.
6.5 Read-Ahead Cache After a read command which reads the data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data in the data buffer. When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium. The host can access the data at higher speed. 6.5.1 Data buffer configuration The device has a 2MB data buffer.
6.5.2 Caching operation The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer. • • All sector data to be processed by the command A part of data including the starting sector to be processed by the command When a part of data to be processed exist in the data buffer, the remaining data are read from the disk medium and are transferred to the host system.
6.5.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. (1) Miss-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media. 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the sequential address to the last read segment.
(3) Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the buffer space with the read ahead data. a. Sequential command just after non-sequential command 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.
b. Sequential hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.
(3) Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.
1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. HAP Partially hit data Lack data DAP 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.
6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium. After transferring data of sectors requested by the host system, the drive generates the interrupt of command complete.
At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state. The default state is “write cache enable”, and can be disable by the SET FEATURES command.
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